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21. 发明授权

US08710560B2 Embedded bonding pad for image sensors 有权
标题翻译：用于图像传感器的嵌入式焊盘
公开(公告)号：US08710560B2
公开(公告)日：2014-04-29
申请号：US11835814
申请日：2007-08-08
申请人： Yuan-Chih Hsieh , Shih-Chang Liu , Shih-Chi Fu , Tzu-Hsuan Hsu , Chung-Yi Yu , Gwo-Yuh Shiau , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Shih-Chang Liu , Shih-Chi Fu , Tzu-Hsuan Hsu , Chung-Yi Yu , Gwo-Yuh Shiau , Chia-Shiung Tsai
IPC分类号： H01L31/062
CPC分类号： H01L27/14643 , H01L24/05 , H01L27/14636 , H01L2224/05556 , H01L2924/12043 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate having a front surface and a back surface, elements formed on the substrate, interconnect metal layers formed over the front surface of the substrate, including a topmost interconnect metal layer, an inter-metal dielectric for insulating each of the plurality of interconnect metal layers, and a bonding pad disposed within the inter-metal dielectric, the bonding pad in contact with one of the interconnect metal layers other than the topmost interconnect metal layer.
摘要翻译：半导体器件包括具有前表面和后表面的半导体衬底，形成在衬底上的元件，形成在衬底的前表面上的互连金属层，包括最上面的互连金属层，用于绝缘的金属间电介质所述多个互连金属层和设置在所述金属间电介质内的接合焊盘，所述接合焊盘与所述互连金属层中的一个互连金属层之外的最上面的互连金属层接触。

22. 发明申请

US20080121975A1 Split-gate memory cells and fabrication methods thereof 有权
标题翻译：分离栅存储单元及其制造方法
公开(公告)号：US20080121975A1
公开(公告)日：2008-05-29
申请号：US11592290
申请日：2006-11-03
申请人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.
摘要翻译：分离栅存储单元及其制造方法。分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。源极线沿第二方向设置在该对控制栅极之间。一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

23. 发明申请

US20080105917A1 Split-gate memory cells and fabrication methods thereof 失效
标题翻译：分离栅存储单元及其制造方法
公开(公告)号：US20080105917A1
公开(公告)日：2008-05-08
申请号：US11785382
申请日：2007-04-17
申请人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/788 , H01L27/115
CPC分类号： H01L27/115 , H01L27/11521
摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.
摘要翻译：分离栅存储单元及其制造方法。分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。活动区域的顶层低于隔离区域的顶层。一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。源极线沿第二方向设置在该对控制栅极之间。一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

24. 发明授权

US08344343B2 Composite film for phase change memory devices 有权
标题翻译：用于相变存储器件的复合膜
公开(公告)号：US08344343B2
公开(公告)日：2013-01-01
申请号：US12750323
申请日：2010-03-30
申请人： Tung-Ti Yeh , Neng-Kuo Chen , Cheng-Yuan Tsai , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Tung-Ti Yeh , Neng-Kuo Chen , Cheng-Yuan Tsai , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/04 , H01L29/02 , H01L47/00 , H01L21/06
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/144 , H01L45/1675
摘要： A phase change memory device and a method of manufacture are provided. The phase change memory device includes a phase change layer electrically coupled to a top electrode and a bottom electrode, the phase change layer comprising a phase change material. A mask layer is formed overlying the phase change layer. A first sealing layer is formed overlying the mask layer, and a second sealing layer is formed overlying the first sealing layer.
摘要翻译：提供了一种相变存储器件及其制造方法。相变存储器件包括电耦合到顶电极和底电极的相变层，所述相变层包括相变材料。掩模层形成在相变层上。形成覆盖在掩模层上的第一密封层，并且形成覆盖在第一密封层上的第二密封层。

25. 发明授权

US07544982B2 Image sensor device suitable for use with logic-embedded CIS chips and methods for making the same 有权
标题翻译：适用于逻辑嵌入式CIS芯片的图像传感器装置及其制造方法
公开(公告)号：US07544982B2
公开(公告)日：2009-06-09
申请号：US11542064
申请日：2006-10-03
申请人： Chung-Yi Yu , Chia-Shiung Tsai , Shih-Chi Fu
发明人： Chung-Yi Yu , Chia-Shiung Tsai , Shih-Chi Fu
IPC分类号： H01L31/062
CPC分类号： H01L27/14627 , H01L27/14621 , H01L27/14632 , H01L27/14636 , H01L27/14685 , H01L27/14687
摘要： An image sensor device is provided. A substrate has a photosensor region formed therein and/or thereon. An interconnection structure is formed over the substrate, and includes metal lines formed in inter-metal dielectric (IMD) layers. At least one IMD-level micro-lens is/are formed in at least one of the IMD layers over the photosensor region. Preferably, barrier layers are located between the IMD layers. Preferably, each of the barrier layers at each level has a net thickness limited to 100 angstroms or less at locations over the photosensor region, except at locations where the IMD-level micro-lenses are located. The IMD-level micro-lenses and the etch stop layers preferably have a refractive index greater than that of the IMD layers. A cap layer is preferably formed on the metal lines, especially when the metal lines include copper. An upper-level micro-lens may be located on a level that is above the interconnection structure.
摘要翻译：提供图像传感器装置。衬底在其中和/或其上形成有光电传感器区域。在衬底上形成互连结构，并且包括在金属间电介质（IMD）层中形成的金属线。在光电传感器区域中的至少一个IMD层中形成至少一个IMD级微透镜。优选地，阻挡层位于IMD层之间。优选地，除了在IMD级微透镜所在的位置之外，每个级别的每个阻挡层的净厚度在光电传感器区域之外的位置处具有限制在100埃或更小的净厚度。 IMD级微透镜和蚀刻停止层优选具有大于IMD层的折射率的折射率。优选在金属线上形成覆盖层，特别是当金属线包括铜时。上级微透镜可以位于互连结构之上的层上。

26. 发明申请

US20070048965A1 Reduced refractive index and extinction coefficient layer for enhanced photosensitivity 有权
$Reduced refractive index and extinction coefficient layer for enhanced photosensitivity$
标题翻译：降低折射率和消光系数层，提高光敏性
公开(公告)号：US20070048965A1
公开(公告)日：2007-03-01
申请号：US11291880
申请日：2005-12-01
申请人： Yuan-Chih Hsieh , Chung-Yi Yu , Tsung-Hsun Huang , Tzu-Hsuan Hsu , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Chung-Yi Yu , Tsung-Hsun Huang , Tzu-Hsuan Hsu , Chia-Shiung Tsai
IPC分类号： H01L21/76
CPC分类号： H01L27/14632 , H01L27/14621 , H01L27/14627 , H01L27/14687
摘要： An image sensor device includes a semiconductor substrate and a plurality of pixels on the substrate. An etch-stop layer is formed over the pixels and has a thickness less than about 600 Angstroms. The image sensor device further includes an interlayer dielectric (ILD) overlying the etch stop layer. The etch-stop layer has a refractive index less than about 2 and an extinction coefficient less than about 0.1.
摘要翻译：图像传感器装置包括半导体衬底和衬底上的多个像素。在像素上方形成蚀刻停止层，其厚度小于约600埃。图像传感器装置还包括覆盖在蚀刻停止层上的层间电介质（ILD）。蚀刻停止层的折射率小于约2，消光系数小于约0.1。

27. 发明授权

US08173518B2 Method of wafer bonding 有权
标题翻译：晶圆接合方法
公开(公告)号：US08173518B2
公开(公告)日：2012-05-08
申请号：US12414910
申请日：2009-03-31
申请人： Martin Liu , Alex Hsu , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Martin Liu , Alex Hsu , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L21/30
CPC分类号： H01L27/1469 , H01L21/76256 , H01L27/14634 , H01L27/1464
摘要： Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side, a back side, and a first edge portion, forming a material layer over a portion of the front side of the device substrate, trimming the first edge portion, removing the material layer, bonding the front side of the device substrate to a carrier substrate, thinning the device substrate from the back side, and trimming a second edge portion of the thinned device substrate.
摘要翻译：提供一种制造半导体器件的方法。该方法包括提供具有前侧，后侧和第一边缘部分的器件基板，在器件基板的正面的一部分的一部分上形成材料层，修整第一边缘部分，去除材料层，接合将器件基板的正面侧支撑到载体基板，从背面侧使器件基板变薄，以及修整变薄的器件基板的第二边缘部分。

28. 发明申请

US20100248446A1 METHOD AND APPARATUS OF HOLDING A DEVICE 有权
标题翻译：控制装置的方法和装置
公开(公告)号：US20100248446A1
公开(公告)日：2010-09-30
申请号：US12414861
申请日：2009-03-31
申请人： Martin Liu , Chung-Yi Yu , Che Ying Hsu , Yeur-Luen Tu , Da-Hsiang Chou , Chia-Shiung Tsai
发明人： Martin Liu , Chung-Yi Yu , Che Ying Hsu , Yeur-Luen Tu , Da-Hsiang Chou , Chia-Shiung Tsai
IPC分类号： H01L21/30 , B25B11/00
CPC分类号： H01L21/6838 , H01L21/304
摘要： Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure.
摘要翻译：提供了一种保持装置的装置和方法。该装置包括具有穿过其延伸的第一和第二孔的晶片卡盘，以及压力控制结构，其能够在高于和低于环境压力的压力之间独立地和选择性地改变在第一和第二孔中的每一个中的流体压力。该方法包括提供具有延伸穿过其中的第一和第二孔的晶片卡盘，并且在高于和低于环境压力的压力之间独立地和选择性地改变在每个第一和第二孔中的流体压力。

29. 发明申请

US20100248414A1 METHOD OF WAFER BONDING 有权
标题翻译： WAFER BONDING的方法
公开(公告)号：US20100248414A1
公开(公告)日：2010-09-30
申请号：US12414910
申请日：2009-03-31
申请人： Martin Liu , Alex Hsu , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Martin Liu , Alex Hsu , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L31/02 , H01L21/762 , H01L21/304
CPC分类号： H01L27/1469 , H01L21/76256 , H01L27/14634 , H01L27/1464
摘要： Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side, a back side, and a first edge portion, forming a material layer over a portion of the front side of the device substrate, trimming the first edge portion, removing the material layer, bonding the front side of the device substrate to a carrier substrate, thinning the device substrate from the back side, and trimming a second edge portion of the thinned device substrate.
摘要翻译：提供一种制造半导体器件的方法。该方法包括提供具有前侧，后侧和第一边缘部分的器件基板，在器件基板的正面的一部分的一部分上形成材料层，修整第一边缘部分，去除材料层，接合将器件基板的正面侧支撑到载体基板，从背面侧使器件基板变薄，以及修整变薄的器件基板的第二边缘部分。

30. 发明授权

US07786552B2 Semiconductor device having hydrogen-containing layer 有权
标题翻译：具有含氢层的半导体装置
公开(公告)号：US07786552B2
公开(公告)日：2010-08-31
申请号：US11149575
申请日：2005-06-10
申请人： Tsung-Hsun Huang , Kuo-Yin Lin , Chung-Yi Yu , Chih-Ta Wu , Chia-Shiung Tsai
发明人： Tsung-Hsun Huang , Kuo-Yin Lin , Chung-Yi Yu , Chih-Ta Wu , Chia-Shiung Tsai
IPC分类号： H01L23/58
CPC分类号： H01L21/76829 , H01L21/3003 , H01L21/3105 , H01L21/3143 , H01L21/76828
摘要： A method for reducing leakage current in a semiconductor structure is disclosed. One or more dielectric layers are formed on a semiconductor substrate, on which at least one device is constructed. A hydrogen-containing layer is formed over the dielectric layers. A silicon nitride passivation layer covers the dielectric layers and the hydrogen-containing layer. The hydrogen atoms of the hydrogen-containing layer are introduced into the dielectric layers without being blocked by the silicon nitride layer, thereby reducing leakage current therein.
摘要翻译：公开了一种用于减小半导体结构中的漏电流的方法。一个或多个电介质层形成在半导体衬底上，其上构造有至少一个器件。在电介质层上形成含氢层。氮化硅钝化层覆盖电介质层和含氢层。含氢层的氢原子被引入到电介质层中而不被氮化硅层阻挡，从而减少其中的漏电流。

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