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21. 发明授权

US06602775B1 Method to improve reliability for flip-chip device for limiting pad design 有权
标题翻译：提高倒装芯片器件限制焊盘设计可靠性的方法
公开(公告)号：US06602775B1
公开(公告)日：2003-08-05
申请号：US09930677
申请日：2001-08-16
申请人： Yen-Ming Chen , Chia-Fu Lin , Kai-Ming Ching , Hsin-Hui Lee , Chao-Yuan Su , Li-Chi Chen
发明人： Yen-Ming Chen , Chia-Fu Lin , Kai-Ming Ching , Hsin-Hui Lee , Chao-Yuan Su , Li-Chi Chen
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/11472 , H01L2224/11474 , H01L2224/11912 , H01L2224/131 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01059 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2224/13099 , H01L2224/05005 , H01L2224/05541
摘要： A method of fabricating a solder bump including the following steps. A UBM over a substrate.having an exposed pad portion is provided. The UBM being in electrical contact with the pad portion. A first patterning layer is formed over the UBM. The first patterning layer including a photosensitive material sensitive to light having a first wavelength. A second patterning layer is formed over the first patterning layer. The second patterning layer including a photosensitive material sensitive to light having a second wavelength. The first patterning layer is selectively exposed with the light having the first wavelength, leaving a first unexposed portion substantially centered over the pad portion between first exposed portions. The second patterning layer is selectively exposed with the light having the second wavelength, leaving a second unexposed portion wider than, and substantially centered over, the first unexposed portion of the exposed first patterning layer. The second unexposed portion of the exposed second patterning layer being between exposed portions. The second unexposed portion of the exposed second patterning layer and the first unexposed portion of the exposed first patterning layer are removed to form opening. A solder plug is formed within the opening. The exposed portions of the exposed first patterning layer and the exposed portions of the exposed second patterning layer are removed. The solder plug is reflowed to form a solder bump.
摘要翻译：一种制造焊料凸块的方法，包括以下步骤。提供了具有裸露焊盘部分的衬底上的UBM。 UBM与焊盘部分电接触。在UBM上形成第一图案化层。第一图案化层包括对具有第一波长的光敏感的感光材料。在第一图案化层上形成第二图案化层。第二图案化层包括对具有第二波长的光敏感的感光材料。利用具有第一波长的光选择性地暴露第一图案化层，留下第一未曝光部分，其基本上位于第一曝光部分之间的焊盘部分的中心。用第二波长的光选择性地暴露第二图案化层，留下第二未曝光部分比暴露的第一图案形成图案的第一未曝光部分宽且基本上居中。曝光的第二图案化层的第二未曝光部分在曝光部分之间。暴露的第二图案形成层的第二未曝光部分和暴露的第一图案形成层的第一未曝光部分被去除以形成开口。在开口内形成焊塞。暴露的第一图案形成层的暴露部分和暴露的第二图案形成层的暴露部分被去除。焊料回流焊以形成焊料凸点。

22. 发明授权

US06426281B1 Method to form bump in bumping technology 有权
公开(公告)号：US06426281B1
公开(公告)日：2002-07-30
申请号：US09759911
申请日：2001-01-16
申请人： Kuo-Wei Lin , Cheng-Yu Chu , Yen-Ming Chen , Yang-Tung Fan , Fu-Jier Fan , Chiou-Shian Peng , Shih-Jang Lin
发明人： Kuo-Wei Lin , Cheng-Yu Chu , Yen-Ming Chen , Yang-Tung Fan , Fu-Jier Fan , Chiou-Shian Peng , Shih-Jang Lin
IPC分类号： H01L2144
CPC分类号： H01L24/12 , H01L24/11 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05568 , H01L2224/1147 , H01L2224/11902 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/3025 , H01L2224/05552
摘要： A new method and processing sequence is provided for the creation of interconnect bumps. A layer of passivation is deposited over a contact pad and patterned, creating an opening in the layer of passivation that aligns with the contact pad. A layer of UBM metal is deposited over the layer of passivation, the layer of UBM is overlying the contact pad and limited to the immediate surroundings of the contact pad. The central surface of the layer of UBM is selectively electroplated after which a layer of solder or solder alloy is solder printed over the electroplated surface of the layer of UBM. A solder flux or paste is applied over the surface of the solder printed solder compound or solder alloy. Flowing of the solder or solder alloy creates the solder bump of the invention.

23. 发明授权

US6077733A Method of manufacturing self-aligned T-shaped gate through dual damascene 有权
标题翻译：通过双镶嵌制造自对准T形门的方法
公开(公告)号：US6077733A
公开(公告)日：2000-06-20
申请号：US389885
申请日：1999-09-03
申请人： Yen-Ming Chen , Wei-Jen Liu , Shih-Chi Lin , Kuo-Chou Liu
发明人： Yen-Ming Chen , Wei-Jen Liu , Shih-Chi Lin , Kuo-Chou Liu
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51 , H01L21/338
CPC分类号： H01L29/66583 , H01L21/28114 , H01L21/28167 , H01L21/28202 , H01L21/28211 , H01L29/42376 , H01L29/518
摘要： A new method is provided to manufacture a T-shaped gate. A layer of insulation is deposited over a semiconductor surface (typically the surface of a substrate), a dual damascene structure containing a via opening and a conducting line trench is created in the layer of insulation. A layer of sacrificial oxide is grown and subsequently removed (preventing initial surface defects and providing protection during subsequent steps of etching). A layer of gate oxide is selectively grown on the bottom of the dual damascene opening. A layer of poly is deposited over the layer of insulation thereby including the dual damascene opening, the poly is planarized down to essentially the top of the dual damascene structure and the insulation is removed from above the surface of the substrate in the regions surrounding the dual damascene structure leaving the dual damascene structure in place.
摘要翻译：提供了一种制造T形门的新方法。绝缘层沉积在半导体表面（通常是衬底的表面）上，在绝缘层中形成包含通孔和导线沟槽的双镶嵌结构。生长一层牺牲氧化物并随后去除（防止初始表面缺陷并在随后的蚀刻步骤期间提供保护）。选择性地在双镶嵌开口的底部生长一层栅极氧化物。一层多晶硅沉积在绝缘层上，从而包括双镶嵌开口，多晶平面化到基本上是双镶嵌结构的顶部，并且在围绕双镶嵌结构的区域中从基板表面上方去除绝缘体镶嵌结构离开双镶嵌结构就位。

24. 发明授权

US08647986B2 Semiconductor process 有权
标题翻译：半导体工艺
公开(公告)号：US08647986B2
公开(公告)日：2014-02-11
申请号：US13220692
申请日：2011-08-30
申请人： Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chun-Wei Hsu , Yen-Ming Chen , Chih-Hsun Lin , Chang-Hung Kung
发明人： Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chun-Wei Hsu , Yen-Ming Chen , Chih-Hsun Lin , Chang-Hung Kung
IPC分类号： H01L21/306 , H01L21/321 , H01L21/3105 , H01L21/768
CPC分类号： H01L21/3212 , H01L21/3105 , H01L21/31051 , H01L21/31053 , H01L21/7684 , H01L21/823835 , H01L29/665
摘要： A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.
摘要翻译：半导体工艺包括以下步骤。第一栅极结构和第二栅极结构形成在基板上，其中第一栅极结构的顶部包括盖层，使得第一栅极结构的垂直高度高于第二栅极结构的垂直高度。在基板上形成介电层。执行第一化学机械抛光工艺以暴露盖层的顶表面。执行第二化学机械抛光工艺以暴露第二栅极结构的顶表面，或执行蚀刻工艺以去除位于第二栅极结构上的介电层。然后执行第二化学机械抛光工艺以除去盖层。

25. 发明授权

US08404544B1 Fabrication methods of integrated semiconductor structure 有权
标题翻译：集成半导体结构的制作方法
公开(公告)号：US08404544B1
公开(公告)日：2013-03-26
申请号：US13446769
申请日：2012-04-13
申请人： Jin-Mu Yin , Shyh-Wei Wang , Yen-Ming Chen
发明人： Jin-Mu Yin , Shyh-Wei Wang , Yen-Ming Chen
IPC分类号： H01L21/8234
CPC分类号： H01L21/28202 , H01L21/823842 , H01L21/823857 , H01L29/4975 , H01L29/518 , H01L29/66545 , H01L29/66553 , H01L29/78
摘要： A method for manufacturing the integrated circuit device comprises providing a substrate having a first region, a second region, and a third region. A first gate stack, a second gate stack, and a third gate stack are formed over the substrate in the first region, the second region, and the third region, respectively. The first gate stack, the second gate stack, and the third gate stack comprise a sacrificial layer over a first dielectric layer. The first gate stack and the second gate stack are removed and a second dielectric layer is formed in the first region and the second region. The portion of second dielectric layer in the first region is transformed into a third dielectric layer by a treatment.
摘要翻译：一种用于制造集成电路器件的方法包括提供具有第一区域，第二区域和第三区域的衬底。分别在第一区域，第二区域和第三区域中的衬底上形成第一栅极堆叠，第二栅极堆叠和第三栅极堆叠。第一栅极堆叠，第二栅极堆叠和第三栅极堆叠包括在第一介电层上的牺牲层。去除第一栅极堆叠和第二栅极堆叠，并且在第一区域和第二区域中形成第二电介质层。通过处理将第一区域中的第二电介质层的部分转变成第三电介质层。

26. 发明申请

US20110312145A1 SOURCE AND DRAIN FEATURE PROFILE FOR IMPROVING DEVICE PERFORMANCE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：用于改进装置性能的源和排出特征轮廓及其制造方法
公开(公告)号：US20110312145A1
公开(公告)日：2011-12-22
申请号：US12816519
申请日：2010-06-16
申请人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
发明人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66515 , H01L21/265 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
摘要翻译：公开了一种用于制造集成电路器件的集成电路器件和方法。所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。掺杂区域注入与LDD区域相反的掺杂剂类型。

27. 发明授权

US07652893B2 Single or dual electronic package with footprint and pin sharing 有权
标题翻译：单或双电子封装，具有占位面积和引脚共享
公开(公告)号：US07652893B2
公开(公告)日：2010-01-26
申请号：US10908122
申请日：2005-04-28
申请人： Yen-Ming Chen
发明人： Yen-Ming Chen
IPC分类号： H05K1/18
CPC分类号： H05K1/181 , H05K3/3421 , H05K2201/09954 , H05K2201/10166 , H05K2201/10522 , Y02P70/611
摘要： A 6-pin electronic package includes a first side including a pair of first outer pins and a first middle pin, and a second side including a pair of second outer pins and a second middle pin. The first outer pins and the second middle pin are operatively coupled to a first circuit to provide a first function. The second outer pins and the first middle pin are operatively coupled to a second circuit to provide a second function. The 6-pin electronic package can be replaced on a circuit substrate with a first electronic package and a second electronic package that collectively include at least six pins. The 6-pin electronic package and the first and second electronic packages can be interchangeably used on a circuit substrate of an electronic device. The circuit substrate may include any one of the 6-pin electronic package mountable to the circuit substrate, and the first and second electronic packages. The first electronic package is mountable on the circuit substrate on a same footprint as the 6-pin electronic package. The second electronic package is mountable on the circuit substrate adjacent the first electronic package such that six pins of the first and second electronic packages share the same footprint as the pins of the 6-pin electronic package.
摘要翻译： 6引脚电子封装包括包括一对第一外部引脚和第一中间引脚的第一侧和包括一对第二外部引脚和第二中间引脚的第二侧。第一外部引脚和第二中间引脚可操作地耦合到第一电路以提供第一功能。第二外部引脚和第一中间引脚可操作地耦合到第二电路以提供第二功能。 6针电子封装可以在具有第一电子封装的电路基板上被替换，而第二电子封装共同包括至少六个引脚。 6针电子封装以及第一和第二电子封装可以互换地用于电子设备的电路基板上。电路基板可以包括可安装到电路基板的6针电子封装以及第一和第二电子封装中的任何一个。第一个电子封装以与6针电子封装相同的占位面安装在电路基板上。第二电子封装可安装在邻近第一电子封装的电路基板上，使得第一和第二电子封装的六个引脚与6针电子封装的引脚共用相同的封装。

28. 发明授权

US07468321B2 Application of impressed-current cathodic protection to prevent metal corrosion and oxidation 有权
标题翻译：应用电流阴极保护，防止金属腐蚀和氧化
公开(公告)号：US07468321B2
公开(公告)日：2008-12-23
申请号：US11382500
申请日：2006-05-10
申请人： Kai-Ming Ching , Chia-Fu Lin , Wen-Hsiang Tseng , Ta-Min Lin , Yen-Ming Chen , Hsin-Hui Lee , Chao-Yuan Su , Wen-Hsiang Tseng
发明人： Kai-Ming Ching , Chia-Fu Lin , Wen-Hsiang Tseng , Ta-Min Lin , Yen-Ming Chen , Hsin-Hui Lee , Chao-Yuan Su , Wen-Hsiang Tseng
IPC分类号： H01L21/44
CPC分类号： H01L23/544 , H01L21/76838 , H01L24/11 , H01L24/12 , H01L2223/54453 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/1147 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01051 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/01084 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/30105 , H01L2224/05647 , H01L2924/00014 , H01L2224/05671 , H01L2224/05124 , H01L2224/05147
摘要： A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.
摘要翻译：提供了一种新的方法来处理金属，特别是铜，以防止这些金属暴露表面的损坏。在半导体加工的步骤中，导致将金属表面暴露于具有pH值的湿物质的步骤中，向暴露的金属施加电压。施加电压的值可以根据湿物质的pH常数的值来选择，使得暴露的金属表面被保护免受湿物质的碱性影响。

29. 发明申请

US20070247370A1 Chip Antenna Apparatus for Receiving Global Positioning System Signals 失效
标题翻译：用于接收全球定位系统信号的芯片天线装置
公开(公告)号：US20070247370A1
公开(公告)日：2007-10-25
申请号：US11564067
申请日：2006-11-28
申请人： Chuan-Lin Hu , Yu-Wei Chen , Chang-Lun Liao , Shun-Tian Lin , Chang-Fa Yang , Yen-Ming Chen , Chao-Wei Wang
发明人： Chuan-Lin Hu , Yu-Wei Chen , Chang-Lun Liao , Shun-Tian Lin , Chang-Fa Yang , Yen-Ming Chen , Chao-Wei Wang
IPC分类号： H01Q1/38
CPC分类号： H01Q15/0006 , H01Q9/30
摘要： A chip antenna apparatus for receiving global positioning system signals, includes a L-shaped ground area and an omni-directional chip antenna. The L-shaped ground area is disposed on a circuit board. The omni-directional chip antenna is disposed in a gap of the L-shaped ground area on the circuit board and electrically connected to the L-shaped ground area.
摘要翻译：用于接收全球定位系统信号的芯片天线装置包括L形接地区域和全向芯片天线。 L形接地区域设置在电路板上。全向芯片天线设置在电路板上的L形接地区域的间隙中并电连接到L形接地区域。

30. 发明申请

US20070194996A1 Chip Antenna Mounting Apparatus 失效
标题翻译：芯片天线安装装置
公开(公告)号：US20070194996A1
公开(公告)日：2007-08-23
申请号：US11564033
申请日：2006-11-28
申请人： Chuan-Lin Hu , Yu-Wei Chen , Chang-Lun Liao , Shun-Tian Lin , Chang-Fa Yang , Yen-Ming Chen , Chao-Wei Wang
发明人： Chuan-Lin Hu , Yu-Wei Chen , Chang-Lun Liao , Shun-Tian Lin , Chang-Fa Yang , Yen-Ming Chen , Chao-Wei Wang
IPC分类号： H01Q1/24
CPC分类号： H01Q1/243 , H01Q1/125
摘要： A connection apparatus for a chip antenna includes a connection base and at least one chip slot. The connection base is disposed on a circuit board and connects to the electronic components of the circuit board via a connection wire. The chip slot is disposed on the connection base for inserting the chip antenna. Thus, the chip antenna is connected to the electronic components of the circuit board via the connection wire.
摘要翻译：用于芯片天线的连接装置包括连接基座和至少一个芯片槽。连接基座设置在电路板上，经由连接线与电路基板的电子部件连接。芯片槽设置在连接基座上，用于插入芯片天线。因此，芯片天线通过连接线连接到电路板的电子部件。

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