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21. 发明授权

US08378698B2 Integrated circuit testing apparatus and method 有权
标题翻译：集成电路测试仪器及方法
公开(公告)号：US08378698B2
公开(公告)日：2013-02-19
申请号：US12798605
申请日：2010-04-07
申请人： Jae-Young Choi , Chang-Hyun Cho
发明人： Jae-Young Choi , Chang-Hyun Cho
IPC分类号： G01R31/20
CPC分类号： G01R31/318511
摘要： A testing apparatus includes a test controller configured to output a plurality of chip selection signals for selecting chips to be tested from among a plurality of chips, a plurality of first control signals for controlling supply of a power supply voltage to the chips selected by the chip selection signals, and a plurality of second control signals for controlling receiving of test voltages output from the chips supplied with the power supply voltage, and a probe card including one or more test blocks each having a plurality of signal transmitters configured to respectively transfer the power supply voltage to the corresponding chips in response to the different first control signals and respectively apply the test voltages output from the corresponding chips to the test controller in response to the different second control signals.
摘要翻译：测试装置包括：测试控制器，被配置为从多个芯片中输出用于选择要测试的芯片的多个芯片选择信号;多个第一控制信号，用于控制向由芯片选择的芯片提供的电源电压选择信号和多个第二控制信号，用于控制从提供有电源电压的芯片输出的测试电压的接收;以及探针卡，其包括一个或多个测试块，每个测试块具有多个信号发射机，其被配置为分别传输功率响应于不同的第一控制信号向相应的芯片提供电压，并且响应于不同的第二控制信号分别将从相应芯片输出的测试电压施加到测试控制器。

22. 发明申请

US20100225345A1 APPARATUS AND METHOD FOR TESTING A SEMICONDUCTOR DEVICE 有权
标题翻译：用于测试半导体器件的装置和方法
公开(公告)号：US20100225345A1
公开(公告)日：2010-09-09
申请号：US12710650
申请日：2010-02-23
申请人： Yanggi KIM , Chang-Hyun Cho , HoonJung Kim
发明人： Yanggi KIM , Chang-Hyun Cho , HoonJung Kim
IPC分类号： G01R31/02
CPC分类号： G01R31/2887
摘要： Provided are an apparatus and a method of testing a semiconductor device. A horizontal maintaining unit provided inside a test head applies load to a probe card in a direction perpendicular to the probe card to hold the probe card in a horizontal state. Probe needles of the probe card are uniformly placed on a central region of pads of the semiconductor device, thereby providing an apparatus and a method of testing a semiconductor device capable of improving productivity and reducing a yield loss of a test process.
摘要翻译：提供了一种测试半导体器件的装置和方法。设置在测试头内部的水平保持单元沿垂直于探针卡的方向向探针卡施加负载，以将探针卡保持在水平状态。探针卡的探头针均匀地放置在半导体器件的焊盘的中心区域上，从而提供能够提高生产率并降低测试过程的屈服损失的半导体器件的测试装置和方法。

23. 发明授权

US07670910B2 Method of forming self-aligned inner gate recess channel transistor 有权
标题翻译：形成自对准内门凹沟道晶体管的方法
公开(公告)号：US07670910B2
公开(公告)日：2010-03-02
申请号：US11641845
申请日：2006-12-20
申请人： Ji-Young Kim , Chang-Hyun Cho , Soo-Ho Shin , Tae-Young Chung
发明人： Ji-Young Kim , Chang-Hyun Cho , Soo-Ho Shin , Tae-Young Chung
IPC分类号： H01L21/336
CPC分类号： H01L21/28114 , H01L29/42376 , H01L29/66553 , H01L29/66621 , H01L29/7834
摘要： A self-aligned inner gate recess channel in a semiconductor substrate includes a recess trench formed in an active region of the substrate, a gate dielectric layer formed on a bottom portion of the recess trench, recess inner sidewall spacers formed on sidewalls of the recess trench, a gate formed in the recess trench so that an upper portion of the gate protrudes above an upper surface of the substrate, wherein a thickness of the recess inner sidewall spacers causes a center portion of the gate to have a smaller width than the protruding upper portion and a lower portion of the gate, a gate mask formed on the gate layer, gate sidewall spacers formed on the protruding upper portion of gate and the gate mask, and a source/drain region formed in the active region of the substrate adjacent the gate sidewall spacers.
摘要翻译：半导体衬底中的自对准内门凹槽通道包括形成在衬底的有源区中的凹槽，形成在凹槽的底部的栅介电层，形成在凹槽沟槽的侧壁上的凹陷内侧壁形成在所述凹槽中的栅极，使得所述栅极的上部突出于所述基板的上表面之上，其中所述凹陷内侧壁间隔物的厚度使得所述栅极的中心部分具有比所述突出的上部栅极的部分和下部，形成在栅极层上的栅极掩模，形成在栅极的突出上部上的栅极侧壁间隔物和栅极掩模，以及形成在邻近基板的基板的有源区域中的源极/漏极区域门侧壁间隔件。

24. 发明申请

US20100025682A1 Interface device for wireless testing, semiconductor device and semiconductor package including the same, and method for wirelessly testing using the same 审中-公开
标题翻译：用于无线测试的接口设备，包括其的半导体器件和半导体封装以及使用其的无线测试的方法
公开(公告)号：US20100025682A1
公开(公告)日：2010-02-04
申请号：US12462373
申请日：2009-08-03
申请人： Sang-Hoon Lee , Eun-Jo Byun , Se-Jang Oh , Young-Soo An , Chang-Hyun Cho
发明人： Sang-Hoon Lee , Eun-Jo Byun , Se-Jang Oh , Young-Soo An , Chang-Hyun Cho
IPC分类号： H01L21/66 , H01L23/00
CPC分类号： G01R31/2889 , G01R31/3025 , G01R31/303 , H01L2224/48472 , H01L2924/3011 , H01L2924/00
摘要： In an interface device for wireless testing capable of testing a semiconductor chip in a non-contact manner, a semiconductor device and a semiconductor package including the same, and a method for wirelessly testing a semiconductor device using the same are provided, the interface device for wireless testing includes an interface substrate, interface antennas on the interface substrate, and interface transmitting and receiving circuits on the interface substrate, wherein the interface transmitting and receiving circuits are electrically connected to input/output pads of a semiconductor chip via interface vias passing through the interface substrate.
摘要翻译：在能够以非接触方式测试半导体芯片的无线测试用接口装置中，提供一种半导体器件和包括该半导体器件的半导体封装以及使用其的半导体器件的无线测试方法，无线测试包括接口基板，接口基板上的接口天线和接口基板上的接口发射和接收电路，其中接口发射和接收电路通过经过接口基板的接口通孔电连接到半导体芯片的输入/输出焊盘界面基板。

25. 发明申请

US20080297185A1 Multi probe card unit, probe test device including the multi probe card unit, and methods of fabricating and using the same 审中-公开
标题翻译：多探针卡单元，包括多探针卡单元的探针测试装置及其制造和使用方法
公开(公告)号：US20080297185A1
公开(公告)日：2008-12-04
申请号：US12155185
申请日：2008-05-30
申请人： Sang-gu Kang , Chang-Hyun Cho , Sung-mo Kang , Sang-kyo Yoo , Joon-yeon Kim
发明人： Sang-gu Kang , Chang-Hyun Cho , Sung-mo Kang , Sang-kyo Yoo , Joon-yeon Kim
IPC分类号： G01R1/073 , H01R43/00
CPC分类号： G01R1/07314 , G01R31/2891 , Y10T29/49222
摘要： A multi probe card unit, a probe test device including the multi probe card unit, and methods of fabricating and using the same are provided. The multi probe card unit may include at least one probe card including a first plurality of probes on a first surface of the at least one probe card and a second plurality of probes on a second surface of the at least one probe card.
摘要翻译：提供了多探针卡单元，包括多探针卡单元的探针测试装置及其制造和使用方法。多探针卡单元可以包括至少一个探针卡，其包括在所述至少一个探针卡的第一表面上的第一多个探针和在所述至少一个探针卡的第二表面上的第二多个探针。

26. 发明申请

US20080252327A1 SUBSTRATE TEST PROBING EQUIPMENT HAVING FORCING PART FOR TEST HEAD AND FORCE-RECEIVING PATTERN FOR PROBE CARD AND METHODS OF USING THE SAME 有权
标题翻译：具有用于检测头的测试头和接收模式的强制部件的基板测试探测设备及其使用方法
公开(公告)号：US20080252327A1
公开(公告)日：2008-10-16
申请号：US12098778
申请日：2008-04-07
申请人： Chang-Hyun Cho , Joon-Yeon Kim , Sang-Gu Kang , Sung-Mo Kang , Sang-Kyu Yoo
发明人： Chang-Hyun Cho , Joon-Yeon Kim , Sang-Gu Kang , Sung-Mo Kang , Sang-Kyu Yoo
IPC分类号： G01R31/02
CPC分类号： G01R31/2889 , G01R31/2891
摘要： Substrate test probing equipment having a force-receiving pattern for a probe card and a forcing part for a test head, and methods of using the same, in which with the force-receiving pattern for the probe card and the forcing part for the test head, thermal expansion and contraction of the probe card can be suppressed when the semiconductor substrate is being tested at high and low temperatures. To this end, to substrate test probing equipment having a substrate mover, a probe card, and a test head is prepared, in which the test head has a forcing part and the probe card has a force-receiving plate. A semiconductor substrate is placed on the substrate mover to be electrically connected with the probe card. The semiconductor substrate is electrically tested by the probe card and the test head. When the semiconductor substrate is being tested, the forcing part of the test head is brought into contact with the force-receiving pattern of the probe card.
摘要翻译：具有用于探针卡的力接收图案和用于测试头的强制部件的基板测试探测设备及其使用方法，其中用于探针卡的受力图案和用于测试头的强制部件当在高温和低温下测试半导体衬底时，可以抑制探针卡的热膨胀和收缩。为此，制备具有基板移动器，探针卡和测试头的基板测试探测设备，其中测试头具有强制部分，探针卡具有受力板。将半导体衬底放置在衬底移动器上以与探针卡电连接。半导体衬底由探针卡和测试头电测试。当半导体衬底被测试时，测试头的强制部分与探针卡的受力图案接触。

27. 发明授权

US07279741B2 Semiconductor device with increased effective channel length and method of manufacturing the same 有权
标题翻译：具有增加有效通道长度的半导体器件及其制造方法
公开(公告)号：US07279741B2
公开(公告)日：2007-10-09
申请号：US10845688
申请日：2004-05-13
申请人： Chang-Hyun Cho , Soo-Ho Shin , Yong-Gyu Choi , Tae-Young Chung
发明人： Chang-Hyun Cho , Soo-Ho Shin , Yong-Gyu Choi , Tae-Young Chung
IPC分类号： H01L29/76
CPC分类号： H01L29/6659 , H01L21/823418 , H01L21/823468 , H01L29/6656
摘要： A semiconductor device with an increased effective channel length and a method of manufacturing the same. The device includes a semiconductor substrate, a gate insulating layer disposed on the semiconductor substrate, a gate electrode structure disposed on a predetermined portion of the gate insulating layer, an insulating layer for preventing short channel disposed on the surface of the resultant structure where the gate electrode structure is disposed, and a source region and a drain region disposed in the semiconductor substrate on either side of the gate electrode structure. Both the source region and the drain region are spaced apart from the gate electrode structure by the thickness of the insulating layer. The channel length of a MOS transistor can be thereby increased.
摘要翻译：具有增加的有效通道长度的半导体器件及其制造方法。该器件包括半导体衬底，设置在半导体衬底上的栅极绝缘层，设置在栅极绝缘层的预定部分上的栅极电极结构，用于防止短路通道的绝缘层，所述绝缘层设置在所述结构的表面上，电极结构，以及设置在栅电极结构的任一侧的半导体衬底中的源区和漏区。源极区域和漏极区域与栅电极结构隔开绝缘层的厚度。可以提高MOS晶体管的沟道长度。

28. 发明申请

US20060205147A1 Self-aligned buried contact pair 有权
标题翻译：自对准埋地接触对
公开(公告)号：US20060205147A1
公开(公告)日：2006-09-14
申请号：US11430036
申请日：2006-05-09
申请人： Cheol-Ju Yun , Chang-Hyun Cho , Tae-Young Chung
发明人： Cheol-Ju Yun , Chang-Hyun Cho , Tae-Young Chung
IPC分类号： H01L21/8242
CPC分类号： H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L28/91
摘要： A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls thereof; a first interlayer dielectric (ILD) layer formed over the bit lines and the oxide layer; a pair of BC pads formed between adjacent bit lines and within the first ILD layer, each BC pad being aligned with one of the pair of exposed diffusion regions in the substrate; and a pair of capacitors, each of the pair of BC pads having one of the pair of capacitors formed thereon, wherein a pair of the bit line sidewall spacers is adjacent to each of the BC pads and the pair of bit line sidewall spacers has an asymmetrical shape.
摘要翻译：自对准埋层接触（BC）对包括具有扩散区域的衬底; 暴露形成在所述基板上的一对扩散区域的氧化物层; 在相邻扩散区之间和氧化物层上形成的位线，每个位线在其侧壁上形成有位线侧壁间隔物; 形成在位线和氧化物层上的第一层间电介质（ILD）层; 一对BC焊盘，形成在相邻位线之间并在第一ILD层内，每个BC焊盘与衬底中一对暴露的扩散区域中的一个对准; 和一对电容器，所述一对BC焊盘中的每一对具有形成在其上的一对电容器中的一个，其中一对位线侧壁间隔件与每个BC焊盘相邻，并且所述一对位线侧壁间隔件具有不对称形状。

29. 发明申请

US20050046048A1 Self-aligned buried contact pair and method of forming the same 有权
标题翻译：自对准掩埋接触对及其形成方法
公开(公告)号：US20050046048A1
公开(公告)日：2005-03-03
申请号：US10762380
申请日：2004-01-23
申请人： Cheol-Ju Yun , Chang-Hyun Cho , Tae-Young Chung
发明人： Cheol-Ju Yun , Chang-Hyun Cho , Tae-Young Chung
IPC分类号： H01L21/28 , H01L21/02 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/417
CPC分类号： H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L28/91
摘要： A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls thereof; a first interlayer dielectric (ILD) layer formed over the bit lines and the oxide layer; a pair of BC pads formed between adjacent bit lines and within the first ILD layer, each BC pad being aligned with one of the pair of exposed diffusion regions in the substrate; and a pair of capacitors, each of the pair of BC pads having one of the pair of capacitors formed thereon, wherein a pair of the bit line sidewall spacers is adjacent to each of the BC pads and the pair of bit line sidewall spacers has an asymmetrical shape.
摘要翻译：自对准埋层接触（BC）对包括具有扩散区域的衬底; 暴露形成在所述基板上的一对扩散区域的氧化物层; 在相邻扩散区之间和氧化物层上形成的位线，每个位线在其侧壁上形成有位线侧壁间隔物; 形成在位线和氧化物层上的第一层间电介质（ILD）层; 一对BC焊盘，形成在相邻位线之间并且在第一ILD层内，每个BC焊盘与衬底中一对暴露的扩散区域中的一个对准; 和一对电容器，所述一对BC焊盘中的每一对具有形成在其上的一对电容器中的一个，其中一对位线侧壁间隔件与每个BC焊盘相邻，并且所述一对位线侧壁间隔件具有不对称形状。

30. 发明授权

US08493087B2 Probe card, and apparatus and method for testing semiconductor device using the probe card 有权
标题翻译：探针卡，以及使用探针卡测试半导体器件的装置和方法
公开(公告)号：US08493087B2
公开(公告)日：2013-07-23
申请号：US12654235
申请日：2009-12-15
申请人： Chang-Hyun Cho , Joonyeon Kim , Sang-Gu Kang , Sanghoon Lee
发明人： Chang-Hyun Cho , Joonyeon Kim , Sang-Gu Kang , Sanghoon Lee
IPC分类号： G01R31/00
CPC分类号： G01R1/07378
摘要： A probe card transmitting electrical test signals between a tester and a semiconductor device includes a main circuit board configured to receive and transmit electrical signals from the tester, an interface unit electrically connected to the main circuit board, the interface unit including a signal line and a signal connection terminal, and at least one probe unit connected to the interface unit, the probe unit being detachable and including a plurality of probe needles arranged in a pattern corresponding to a pattern of electrode pads of the semiconductor device.
摘要翻译：在测试器和半导体器件之间传输电测试信号的探针卡包括：主电路板，被配置为接收和发送来自测试器的电信号，电连接到主电路板的接口单元，所述接口单元包括信号线和信号连接端子和连接到接口单元的至少一个探针单元，探针单元可拆卸并且包括以对应于半导体器件的电极焊盘图案的图案布置的多个探针。

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