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21. 发明申请

US20080064160A1 CMOS DEVICES INCORPORATING HYBRID ORIENTATION TECHNOLOGY (HOT) WITH EMBEDDED CONNECTORS 失效
标题翻译：嵌入式连接器的混合定向技术（HOT）的CMOS器件
公开(公告)号：US20080064160A1
公开(公告)日：2008-03-13
申请号：US11470819
申请日：2006-09-07
申请人： Byeong Y. Kim , Xiaomeng Chen , Yoichi Otani
发明人： Byeong Y. Kim , Xiaomeng Chen , Yoichi Otani
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207
摘要： The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.
摘要翻译：本发明涉及具有混合通道取向并由嵌入在半导体衬底中的导电连接器连接的诸如n-FET和p-FET的互补器件。具体地，半导体衬底具有至少具有不同表面晶取向（即混合取向）的第一和第二器件区域。 n-FET形成在第一和第二器件区域中的一个处，并且p-FET形成在第一和第二器件区域中的另一个处。 n-FET和p-FET通过位于第一和第二器件区域之间的导电连接器电连接并嵌入在半导体衬底中。优选地，介电隔离件首先设置在第一和第二器件区域之间并且凹入以在它们之间形成间隙。然后将导电连接器形成在凹入的电介质间隔物上方的间隙中。

22. 发明授权

US07803708B2 Method for reducing amine based contaminants 失效
标题翻译：还原胺类污染物的方法
公开(公告)号：US07803708B2
公开(公告)日：2010-09-28
申请号：US11537378
申请日：2006-09-29
申请人： Xiaomeng Chen , William Cote , Anthony K Stamper , Arthur C Winslow
发明人： Xiaomeng Chen , William Cote , Anthony K Stamper , Arthur C Winslow
IPC分类号： H01L21/302
CPC分类号： H01L21/76831 , H01L21/02046 , H01L21/02052 , H01L21/02126 , H01L21/02129 , H01L21/02131 , H01L21/02164 , H01L21/0234 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/312 , H01L21/31612 , H01L21/31625 , H01L21/31629 , H01L21/31633 , H01L21/76801 , H01L21/76807 , H01L21/76826
摘要： Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing.
摘要翻译：降低抗药性中毒的方法该方法包括以下步骤：在衬底上的电介质中形成第一结构，在衬底上形成第二结构之前，从电介质和衬底中还原胺相关的污染物，使得胺相关的污染物不会从任一种基底或电介质，其中所述还原利用等离子体处理，其中所述等离子体处理中的一种化学结合所述胺相关的污染并在随后的处理步骤期间结合，捕集或消耗胺相关污染物，在所述基底上形成所述第二结构，形成第一结构，防止在随后的还原过程中中和抗蚀剂层。

23. 发明申请

US20100006926A1 METHODS FOR FORMING HIGH PERFORMANCE GATES AND STRUCTURES THEREOF 失效
标题翻译：形成高性能门和其结构的方法
公开(公告)号：US20100006926A1
公开(公告)日：2010-01-14
申请号：US12170687
申请日：2008-07-10
申请人： HUILONG ZHU , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
发明人： HUILONG ZHU , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823842 , H01L21/82385 , H01L21/823857
摘要： Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.
摘要翻译：公开了在MOSFET中形成高性能栅极的方法及其结构。一个实施例包括提供包括第一短沟道有源区，第二短沟道有源区和长沟道有源区的衬底的方法，每个有源区通过浅沟槽隔离（STI）与另一个分离。以及在所述长沟道有源区上形成具有多晶硅栅极的场效应晶体管（FET），在所述第一短沟道有源区上具有第一功函数调节材料的第一双金属栅极FET和具有第二双金属栅极FET的第二双金属栅极FET，第二短通道有源区域上的功函数调整材料，其中第一和第二功函数调节材料不同。

24. 发明申请

US20090256207A1 FINFET DEVICES FROM BULK SEMICONDUCTOR AND METHODS FOR MANUFACTURING THE SAME 审中-公开
标题翻译：来自大块半导体的FINFET器件及其制造方法
公开(公告)号：US20090256207A1
公开(公告)日：2009-10-15
申请号：US12102333
申请日：2008-04-14
申请人： Xiaomeng Chen , Bachir Dirahoui , William K. Henson , Michael D. Hulvey , Amit Kumar , Mahender Kumar , Amanda L. Tessier , Clement H. Wann
发明人： Xiaomeng Chen , Bachir Dirahoui , William K. Henson , Michael D. Hulvey , Amit Kumar , Mahender Kumar , Amanda L. Tessier , Clement H. Wann
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L29/785 , H01L21/76283 , H01L21/823431 , H01L21/823481 , H01L29/66795
摘要： Disclosed herein is a transistor comprising a first fin having a first gate electrode disposed across the first fin; the gate electrode contacting opposing surfaces of the fin; and a planar oxide layer having a second gate electrode disposed across the planar oxide layer to form a planar metal oxide semiconductor field effect transistor; the first fin and the planar oxide layer being disposed upon a surface of a wafer.
摘要翻译：本文公开了一种晶体管，包括：第一鳍片，其具有横跨第一鳍片设置的第一栅电极; 所述栅电极接触所述翅片的相对表面; 以及平面氧化物层，具有跨过所述平面氧化物层设置的第二栅极，以形成平面金属氧化物半导体场效应晶体管; 第一鳍片和平面氧化物层设置在晶片的表面上。

25. 发明申请

US20140064034A1 DISTANCE MEASUREMENTS BETWEEN COMPUTING DEVICES 有权
标题翻译：计算设备之间的距离测量
公开(公告)号：US20140064034A1
公开(公告)日：2014-03-06
申请号：US13599823
申请日：2012-08-30
申请人： Zengbin Zhang , David Chiyuan Chu , Thomas Moscibroda , Xiaomeng Chen , Feng Zhao
发明人： Zengbin Zhang , David Chiyuan Chu , Thomas Moscibroda , Xiaomeng Chen , Feng Zhao
IPC分类号： G01S3/80
CPC分类号： G01S11/14
摘要： Some implementations provide techniques and arrangements for distance measurements between computing devices. Some examples determine a distance between devices based at least in part on a propagation time of audio tones between the devices. Further, some examples determine the arrival time of the audio tones by performing autocorrelation on streaming data corresponding to recorded sound to determine a timing of an autocorrelation peak indicative of a detection of an audio tone in the streaming data. In some cases, cross correlation may be performed on the streaming data in a search window to determine a timing of a cross correlation peak indicative of the detection of the audio tone in the streaming data. The location of the search window in time may be determined based at least in part on the timing of the detected autocorrelation peak.
摘要翻译：一些实现提供了用于计算设备之间的距离测量的技术和布置。一些示例至少部分地基于设备之间的音频音调的传播时间来确定设备之间的距离。此外，一些示例通过对与记录的声音相对应的流数据执行自相关来确定音频音调的到达时间，以确定指示流数据中的音频音调的检测的自相关峰值的定时。在一些情况下，可以在搜索窗口中对流数据执行互相关，以确定指示流数据中的音频音调的检测的互相关峰值的定时。可以至少部分地基于检测到的自相关峰值的定时来确定搜索窗口在时间上的位置。

26. 发明授权

US08242544B2 Semiconductor structure having reduced amine-based contaminants 有权
标题翻译：半导体结构具有减少的胺基污染物
公开(公告)号：US08242544B2
公开(公告)日：2012-08-14
申请号：US11004845
申请日：2004-12-07
申请人： Xiaomeng Chen , William Cote , Anthony K. Stamper , Arthur C. Winslow
发明人： Xiaomeng Chen , William Cote , Anthony K. Stamper , Arthur C. Winslow
IPC分类号： H01L21/70
CPC分类号： H01L21/76831 , H01L21/02046 , H01L21/02052 , H01L21/02126 , H01L21/02129 , H01L21/02131 , H01L21/02164 , H01L21/0234 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/312 , H01L21/31612 , H01L21/31625 , H01L21/31629 , H01L21/31633 , H01L21/76801 , H01L21/76807 , H01L21/76826
摘要： A method for reducing resist poisoning is provided. The method includes forming a first structure in a dielectric on a substrate and reducing amine related contaminants from the dielectric and the substrate created after the formation of the first structure. The method further includes forming a second structure in the dielectric. A first organic film may be formed on the substrate which is then heated and removed from the substrate to reduce the contaminant. Alternatively, a plasma treatment or cap may be provided. A second organic film is formed on the substrate and patterned to define a second structure in the dielectric.
摘要翻译：提供了减少抗蚀剂中毒的方法。该方法包括在基板上的电介质中形成第一结构，并且在形成第一结构之后，从电介质和基板上还原胺相关的污染物。该方法还包括在电介质中形成第二结构。可以在衬底上形成第一有机膜，然后将其从衬底加热并除去以减少污染物。或者，可以提供等离子体处理或盖。在基板上形成第二有机膜并图案化以在电介质中限定第二结构。

27. 发明授权

US07790553B2 Methods for forming high performance gates and structures thereof 失效
标题翻译：形成高性能栅极的方法及其结构
公开(公告)号：US07790553B2
公开(公告)日：2010-09-07
申请号：US12170687
申请日：2008-07-10
申请人： Huilong Zhu , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
发明人： Huilong Zhu , Xiaomeng Chen , Mahender Kumar , Brian J. Greene , Bachir Dirahoui , Jay W. Strane , Gregory G. Freeman
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842 , H01L21/82385 , H01L21/823857
摘要： Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.
摘要翻译：公开了在MOSFET中形成高性能栅极的方法及其结构。一个实施例包括提供包括第一短沟道有源区，第二短沟道有源区和长沟道有源区的衬底的方法，每个有源区通过浅沟槽隔离（STI）与另一个分离。以及在所述长沟道有源区上形成具有多晶硅栅极的场效应晶体管（FET），在所述第一短沟道有源区上具有第一功函数调节材料的第一双金属栅极FET和具有第二双金属栅极FET的第二双金属栅极FET，第二短通道有源区域上的功函数调整材料，其中第一和第二功函数调节材料不同。

28. 发明申请

US20090321828A1 STRUCTURES, FABRICATION METHODS, DESIGN STRUCTURES FOR STRAINED FIN FIELD EFFECT TRANSISTORS (FINFETS) 有权
标题翻译：结构，制造方法，应变金属场效应晶体管的设计结构（FINFETS）
公开(公告)号：US20090321828A1
公开(公告)日：2009-12-31
申请号：US12146728
申请日：2008-06-26
申请人： Xiaomeng Chen , Byeong Yeol Kim , Mahender Kumar , Huilong Zhu
发明人： Xiaomeng Chen , Byeong Yeol Kim , Mahender Kumar , Huilong Zhu
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L29/7848 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure, a fabrication method, and a design structure for a FinFet. The FinFet includes a dielectric layer, a central semiconductor fin region on the dielectric layer, a first semiconductor seed region on the dielectric layer, and a first strain creating fin region. The first semiconductor seed region is sandwiched between the first strain creating fin region and the dielectric layer. The first semiconductor seed region includes a first semiconductor material. The first strain creating fin region includes the first semiconductor material and a second semiconductor material different than the first semiconductor material. A first atom percent of the first semiconductor material in the first semiconductor seed region is different than a second atom percent of the first semiconductor material in the first strain creating fin region.
摘要翻译： FinFet的半导体结构，制造方法和设计结构。 FinFet包括电介质层，电介质层上的中央半导体鳍片区域，电介质层上的第一半导体种子区域和第一应变产生鳍片区域。第一半导体种子区域夹在第一应变产生鳍区域和电介质层之间。第一半导体种子区域包括第一半导体材料。第一应变产生鳍区域包括第一半导体材料和与第一半导体材料不同的第二半导体材料。第一半导体晶种区域中的第一半导体材料的第一原子百分比不同于第一应变产生鳍区域中的第一半导体材料的第二原子百分比。

29. 发明申请

US20050095841A1 Method for reducing amine based contaminants 有权
标题翻译：还原胺类污染物的方法
公开(公告)号：US20050095841A1
公开(公告)日：2005-05-05
申请号：US11004845
申请日：2004-12-07
申请人： Xiaomeng Chen , William Cote , Anthony Stamper , Arthur Winslow
发明人： Xiaomeng Chen , William Cote , Anthony Stamper , Arthur Winslow
IPC分类号： H01L21/306 , H01L21/3105 , H01L21/311 , H01L21/312 , H01L21/316 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/02046 , H01L21/02052 , H01L21/02126 , H01L21/02129 , H01L21/02131 , H01L21/02164 , H01L21/0234 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/312 , H01L21/31612 , H01L21/31625 , H01L21/31629 , H01L21/31633 , H01L21/76801 , H01L21/76807 , H01L21/76826
摘要： A method for reducing resist poisoning is provided. The method includes forming a first structure in a dielectric on a substrate and reducing amine related contaminants from the dielectric and the substrate created after the formation of the first structure. The method further includes forming a second structure in the dielectric. A first organic film may be formed on the substrate which is then heated and removed from the substrate to reduce the contaminant. Alternatively, a plasma treatment or cap may be provided. A second organic film is formed on the substrate and patterned to define a second structure in the dielectric.
摘要翻译：提供了减少抗蚀剂中毒的方法。该方法包括在基板上的电介质中形成第一结构，并且在形成第一结构之后，从电介质和基板上还原胺相关的污染物。该方法还包括在电介质中形成第二结构。可以在衬底上形成第一有机膜，然后将其从衬底加热并除去以减少污染物。或者，可以提供等离子体处理或盖。在基板上形成第二有机膜并图案化以在电介质中限定第二结构。

30. 发明授权

US06503834B1 Process to increase reliability CuBEOL structures 失效
标题翻译：提高可靠性CuBEOL结构的工艺
公开(公告)号：US06503834B1
公开(公告)日：2003-01-07
申请号：US09677585
申请日：2000-10-03
申请人： Xiaomeng Chen , Mahadevaiyer Krishnan , Judith M. Rubino , Carlos J. Sambucetti , Soon-Cheon Seo , James A. Tornello
发明人： Xiaomeng Chen , Mahadevaiyer Krishnan , Judith M. Rubino , Carlos J. Sambucetti , Soon-Cheon Seo , James A. Tornello
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/288
摘要： The invention provides a process to increase the reliability of BEOL interconnects. The process comprises forming an array of conductors on a dielectric layer on a wafer substrate, polishing the upper surface so that the surfaces of the conductors are substantially co-planar with the upper surface of the dielectric layer, forming an alloy film on the upper surfaces of the conductors, and brush cleaning the upper surfaces of the conductors and the dielectric layer.
摘要翻译：本发明提供了增加BEOL互连的可靠性的过程。该方法包括在晶片衬底上的电介质层上形成导体阵列，抛光上表面，使得导体的表面与电介质层的上表面基本上共面，在上表面上形成合金膜的导体，并刷清洁导体和电介质层的上表面。

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