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21. 发明授权

US08383474B2 Thin channel device and fabrication method with a reverse embedded stressor 有权
标题翻译：具有反向嵌入式应力源的薄通道器件和制造方法
公开(公告)号：US08383474B2
公开(公告)日：2013-02-26
申请号：US12789699
申请日：2010-05-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/8238
CPC分类号： H01L29/7849 , H01L21/26506 , H01L29/66772 , H01L29/785 , H01L29/78654
摘要： A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer. A removable buried layer is provided on or in the second semiconductor layer. A gate structure with side spacers is formed on the first semiconductor layer. Recesses are formed down to the removable buried layer in areas for source and drain regions. The removable buried layer is etched away to form an undercut below the dielectric layer below the gate structure. A stressor layer is formed in the undercut, and source and drain regions are formed.
摘要翻译：用于在半导体层中诱发应力的装置和方法包括提供在第一半导体层和第二半导体层之间形成介电层的基板。可移除的掩埋层设置在第二半导体层上或第二半导体层中。在第一半导体层上形成具有侧面间隔物的栅极结构。在源区和漏区的区域中形成凹陷到可移除的掩埋层。蚀刻掉可移除的掩埋层，以在栅极结构下面的介电层下方形成底切。在底切中形成应力层，形成源区和漏区。

22. 发明授权

US08278175B2 Compressively stressed FET device structures 有权
标题翻译：压应力FET器件结构
公开(公告)号：US08278175B2
公开(公告)日：2012-10-02
申请号：US12813311
申请日：2010-06-10
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/335
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译：公开了用于制造FET器件结构的方法。所述方法包括接收Si基材料的翅片，以及将鳍片的区域转换为氧化物元件。氧化物元件在制造Fin-FET器件的鳍片上施加压力。施加的压力在Fin-FET器件的器件沟道中引起压应力。所述方法还包括接收Si基材料的矩形构件并将所述构件的区域转换为氧化物元件。所述方法进一步包括在与N个翅片施加压力的同时被N型翅片平行地形成的构件图案化。 Fin-FET器件制造在压缩鳍片中，这导致压缩应力器件通道。还公开了FET器件结构。 FET器件结构具有具有Si基材料的翅片的Fin-FET器件。氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。另外的FET器件结构具有各自具有鳍片的Fin-FET器件。垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

23. 发明申请

US20120193713A1 FinFET device having reduce capacitance, access resistance, and contact resistance 有权
标题翻译： FinFET器件具有降低电容，访问电阻和接触电阻
公开(公告)号：US20120193713A1
公开(公告)日：2012-08-02
申请号：US13017966
申请日：2011-01-31
申请人： Pranita Kulkarni , Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Ghavam Shahidi , Hemanth Jagannathan
发明人： Pranita Kulkarni , Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Ghavam Shahidi , Hemanth Jagannathan
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66803 , H01L29/41791 , H01L29/785
摘要： A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each is second spacer adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers.
摘要翻译：形成具有减小的电容，存取电阻和接触电阻的鳍状场效应晶体管（finFET）器件。提供掩埋氧化物，鳍状物，栅极和第一间隔物。该鳍被掺杂以形成在栅极下方延伸的延伸结。第二间隔件形成在延伸接头的顶部。每个是与栅极的任一侧相邻的第一间隔件之间的第二间隔件。延伸结和未被栅极保护的埋入氧化物，第一间隔物和第二间隔物被回蚀刻以产生空隙。空隙填充有半导体材料，使得半导体材料的顶表面延伸到延伸接头的顶表面之下，以形成凹陷的源极 - 漏极区域。在凹陷的源极 - 漏极区域，延伸结点和不被第一间隔物和第二间隔物保护的栅极上形成硅化物层。

24. 发明授权

US08207038B2 Stressed Fin-FET devices with low contact resistance 有权
标题翻译：具有低接触电阻的强调Fin-FET器件
公开(公告)号：US08207038B2
公开(公告)日：2012-06-26
申请号：US12786397
申请日：2010-05-24
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858
摘要： A method for fabricating an FET device is disclosed. The method includes Fin-FET devices with fins that are composed of a first material, and then merged together by epitaxial deposition of a second material. The fins are vertically recesses using a selective etch. A continuous silicide layer is formed over the increased surface areas of the first material and the second material, leading to smaller resistance. A stress liner overlaying the FET device is afterwards deposited. An FET device is also disclosed, which FET device includes a plurality of Fin-FET devices, the fins of which are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device.
摘要翻译：公开了一种用于制造FET器件的方法。该方法包括具有由第一材料构成的翅片的Fin-FET器件，然后通过外延沉积第二材料而合并在一起。翅片是使用选择性蚀刻的垂直凹部。在第一材料和第二材料的增加的表面积上形成连续的硅化物层，导致较小的电阻。覆盖FET器件的应力衬垫之后被沉积。还公开了一种FET器件，该FET器件包括多个Fin-FET器件，其翅片由第一材料构成。 FET器件包括第二材料，其外延地融合鳍片。翅片相对于第二材料的上表面垂直凹入。 FET器件还包括形成在鳍片上方和第二材料上的连续硅化物层，以及覆盖该器件的应力衬垫。

25. 发明申请

US20110309333A1 SEMICONDUCTOR DEVICES FABRICATED BY DOPED MATERIAL LAYER AS DOPANT SOURCE 有权
标题翻译：由掺杂材料层组成的半导体器件作为掺杂源
公开(公告)号：US20110309333A1
公开(公告)日：2011-12-22
申请号：US12819440
申请日：2010-06-21
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L29/775 , H01L21/34 , H01L27/12 , H01L21/84
CPC分类号： H01L29/785 , B82Y10/00 , H01L21/2254 , H01L21/2255 , H01L21/2257 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L21/845 , H01L27/1211 , H01L29/165 , H01L29/42392 , H01L29/66439 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/66803 , H01L29/775 , H01L29/78 , H01L29/7833 , H01L29/7834 , H01L29/7848 , H01L29/78696
摘要： A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.
摘要翻译：提供一种形成半导体器件的方法，其中用于源极和漏极区的掺杂剂从掺杂的介电层引入。在一个示例中，栅极结构形成在半导体层的厚度小于10nm的SOI衬底的半导体层上。在与栅极结构相邻的半导体层的至少一部分上形成掺杂介电层。来自掺杂介电层的掺杂剂被驱动到与栅极结构相邻的半导体层的部分中。扩散到半导体中的掺杂剂提供了源极和漏极延伸区域。

26. 发明申请

US20110291189A1 THIN CHANNEL DEVICE AND FABRICATION METHOD WITH A REVERSE EMBEDDED STRESSOR 有权
标题翻译：具有反向嵌入式应力的薄通道器件和制造方法
公开(公告)号：US20110291189A1
公开(公告)日：2011-12-01
申请号：US12789699
申请日：2010-05-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7849 , H01L21/26506 , H01L29/66772 , H01L29/785 , H01L29/78654
摘要： A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer. A removable buried layer is provided on or in the second semiconductor layer. A gate structure with side spacers is formed on the first semiconductor layer. Recesses are formed down to the removable buried layer in areas for source and drain regions. The removable buried layer is etched away to form an undercut below the dielectric layer below the gate structure. A stressor layer is formed in the undercut, and source and drain regions are formed.
摘要翻译：用于在半导体层中诱发应力的装置和方法包括提供在第一半导体层和第二半导体层之间形成介电层的基板。可移除的掩埋层设置在第二半导体层上或第二半导体层中。在第一半导体层上形成具有侧面间隔物的栅极结构。在源区和漏区的区域中形成凹陷到可移除的掩埋层。蚀刻掉可移除的掩埋层，以在栅极结构下面的介电层下方形成底切。在底切中形成应力层，形成源区和漏区。

27. 发明申请

US20110221003A1 MOSFETs WITH REDUCED CONTACT RESISTANCE 有权
标题翻译：具有降低接触电阻的MOSFET
公开(公告)号：US20110221003A1
公开(公告)日：2011-09-15
申请号：US12719934
申请日：2010-03-09
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/417 , H01L29/78 , H01L21/336 , H01L21/3205
CPC分类号： H01L29/66477 , H01L21/28518 , H01L23/485 , H01L29/0847 , H01L29/165 , H01L29/41725 , H01L29/41766 , H01L29/41783 , H01L29/45 , H01L29/456 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for forming a field effect transistor with reduced contact resistance are provided. The reduced contact resistance is manifested by a reduced metal semiconductor alloy contact resistance and a reduced conductively filled via contact-to-metal semiconductor alloy contact resistance. The reduced contact resistance is achieved in this disclosure by texturing the surface of the transistor's source region and/or the transistor's drain region. Typically, both the source region and the drain region are textured in the present disclosure. The textured source region and/or the textured drain region have an increased area as compared to a conventional transistor that includes a flat source region and/or a flat drain region. A metal semiconductor alloy, e.g., a silicide, is formed on the textured surface of the source region and/or the textured surface of the drain region. A conductively filled via contact is formed atop the metal semiconductor alloy.
摘要翻译：提供了形成具有降低的接触电阻的场效应晶体管的方法和结构。降低的接触电阻由金属半导体合金接触电阻降低和导电填充通孔接触 - 金属半导体合金接触电阻表现出来。在本公开内容中通过纹理化晶体管的源极区域和/或晶体管的漏极区域的表面来实现降低的接触电阻。通常，在本公开内容中，源极区域和漏极区域都被纹理化。与包括平坦源极区域和/或平坦漏极区域的常规晶体管相比，纹理化源极区域和/或织构化漏极区域具有增加的面积。在源极区域的纹理表面和/或漏极区域的纹理化表面上形成金属半导体合金，例如硅化物。在金属半导体合金的顶部形成导电填充的通孔接触。

28. 发明申请

US20110169089A1 EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT WITH ON-CHIP RESISTORS AND METHOD OF FORMING THE SAME 有权
标题翻译：具有片上电阻的超薄半导体绝缘体（ETSOI）集成电路及其形成方法
公开(公告)号：US20110169089A1
公开(公告)日：2011-07-14
申请号：US12687273
申请日：2010-01-14
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L27/1214 , H01L21/84 , H01L27/1203 , H01L27/13
摘要： An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.
摘要翻译：提供了一种电气装置，其在一个实施例中包括具有厚度小于10nm的半导体层的绝缘体上半导体（SOI）基板。在半导体层的第一表面上存在具有第一导电性的单晶半导体材料的升高的源极区域和升高的漏极区域的半导体器件。由第一导电性的单晶半导体材料构成的电阻器存在于半导体层的第二表面上。还提供了形成上述电气装置的方法。

29. 发明授权

US09041116B2 Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs) 有权
公开(公告)号：US09041116B2
公开(公告)日：2015-05-26
申请号：US13478154
申请日：2012-05-23
申请人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号： H01L27/092 , H01L27/12 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

30. 发明授权

US08933515B2 Device structure, layout and fabrication method for uniaxially strained transistors 有权
标题翻译：单轴应变晶体管的器件结构，布局和制造方法
公开(公告)号：US08933515B2
公开(公告)日：2015-01-13
申请号：US13531175
申请日：2012-06-22
申请人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
发明人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
IPC分类号： H01L27/088 , H01L21/8238 , H01L27/02 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/6656 , H01L29/66628 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
摘要翻译：一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构在活跃地区。在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。

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