专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06413819B1 Memory device and method for using prefabricated isolated storage elements 有权
标题翻译：使用预制隔离存储元件的存储器件和方法
公开(公告)号：US06413819B1
公开(公告)日：2002-07-02
申请号：US09595821
申请日：2000-06-16
申请人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
发明人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
IPC分类号： H01L21336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/7883 , H01L29/7888
摘要： A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements (18) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer (12) upon which a first gate insulator (14) is formed. A plurality of pre-fabricated isolated storage elements (18) is then deposited on the first gate insulator (14). This deposition step may be accomplished by immersion in a colloidal solution (16) that includes a solvent and pre-fabricated isolated storage elements (18). Once deposited, the solvent of the solution (16) can be removed, leaving the pre-fabricated isolated storage elements (18) deposited on the first gate insulator (14). After depositing the pre-fabricated isolated storage elements (18), a second gate insulator (20) is formed over the pre-fabricated isolated storage elements (18). A gate electrode (24) is then formed over the second gate insulator (20), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region (32) and a drain region (34) are then formed in the semiconductor layer (12) such that a channel region is formed between underlying the gate electrode (24).
摘要翻译：提供了一种半导体器件，其包括由多个预先形成的隔离存储元件（18）构成的浮动栅极和用于制造这种器件的方法。该器件通过首先提供形成第一栅极绝缘体（14）的半导体层（12）形成。然后，多个预制隔离存储元件（18）沉积在第一栅极绝缘体（14）上。该沉积步骤可以通过浸入包括溶剂和预制隔离存储元件（18）的胶体溶液（16）中来实现。一旦沉积，可以除去溶液（16）的溶剂，留下沉积在第一栅极绝缘体（14）上的预制隔离存储元件（18）。在沉积预制隔离存储元件（18）之后，在预制隔离存储元件（18）上形成第二栅极绝缘体（20）。然后，在第二栅极绝缘体（20）之上形成栅电极（24），并且选择性地去除不在栅电极下面的第一和第二栅极绝缘体和多个预制隔离存储元件的部分。然后在半导体层（12）中形成源极区（32）和漏极区（34），使得在栅电极（24）下方形成沟道区。

22. 发明授权

US5665202A Multi-step planarization process using polishing at two different pad pressures 失效
标题翻译：使用两种不同压力下的抛光进行多步平面化处理
公开(公告)号：US5665202A
公开(公告)日：1997-09-09
申请号：US562440
申请日：1995-11-24
申请人： Chitra K. Subramanian , Asanga H. Perera , James D. Hayden , Subramoney V. Iyer
发明人： Chitra K. Subramanian , Asanga H. Perera , James D. Hayden , Subramoney V. Iyer
IPC分类号： H01L21/3105 , H01L21/306
CPC分类号： H01L21/31053
摘要： A process for polish planarizing a fill material (40) overlying a semiconductor substrate (30) includes a multi-step polishing process. In one embodiment, a second planarization layer (42) is deposited over a fill material (40) and a portion of the fill material (40) is removed leaving a remaining portion (44). The pad pressure of a CMP apparatus (20) is adjusted such that a first pressure is generated during the polishing process. Then, the remaining portion (44) is removed, while operating the CMP apparatus (20) at a second pad pressure. The selectivity of the polishing process is maintained by reducing the pad pressure during the second polishing step. In a second embodiment, after the first polishing step is performed, the remaining portion (44) is removed by an etching process using a portion (46) of second planarization layer (42).
摘要翻译：抛光平面化覆盖半导体衬底（30）的填充材料（40）的工艺包括多步抛光工艺。在一个实施例中，第二平坦化层（42）沉积在填充材料（40）上，并且去除填充材料（40）的一部分，留下剩余部分（44）。调整CMP装置（20）的衬垫压力，使得在抛光过程中产生第一压力。然后，在第二焊盘压力下操作CMP装置（20）的同时去除剩余部分（44）。通过在第二抛光步骤期间减小垫压力来维持抛光工艺的选择性。在第二实施例中，在执行第一抛光步骤之后，通过使用第二平坦化层（42）的部分（46）的蚀刻工艺去除剩余部分（44）。

23. 发明授权

US5481126A Semiconductor-on-insulator electronic devices having trench isolated monocrystalline active regions 失效
标题翻译：具有沟槽隔离单晶有源区的绝缘体上半导体电子器件
公开(公告)号：US5481126A
公开(公告)日：1996-01-02
申请号：US313893
申请日：1994-09-27
申请人： Chitra K. Subramanian , Gerold W. Neudeck
发明人： Chitra K. Subramanian , Gerold W. Neudeck
IPC分类号： H01L27/06 , H01L29/06 , H01L29/786 , H01L29/80 , H01L31/112
CPC分类号： H01L29/0653 , H01L27/0623 , H01L29/0649 , H01L29/78654
摘要： A semiconductor-on-insulator (SOI) electronic device includes a monocrystalline semiconductor substrate and at least one trench therein. A trench insulating layer is provided on a bottom the trench for electrical isolation and a monocrystalline semiconducting region is also included in the trench, on the trench insulating layer. The semiconducting region preferably includes epitaxially overgrown silicon (EOS) which is grown from an exposed sidewall of the trench. An active region of the electronic device is also included in the semiconductor layer. Second, third, and additional active regions of the electronic device, if any, may also be included in the semiconducting region or in additional semiconducting regions which are provided in additional trenches. The semiconductor substrate may also include one or more active regions of the electronic device.
摘要翻译：绝缘体上半导体（SOI）电子器件包括单晶半导体衬底及其中的至少一个沟槽。沟槽绝缘层设置在用于电隔离的沟槽的底部，并且在沟槽绝缘层中的沟槽中还包括单晶半导体区域。半导体区域优选地包括从沟槽的暴露的侧壁生长的外延长满的硅（EOS）。电子器件的有源区也包括在半导体层中。电子器件的第二，第三和另外的有源区（如果有的话）也可以被包括在半导体区域中或在另外的沟槽中提供的附加的半导体区域中。半导体衬底还可以包括电子器件的一个或多个有源区。

24. 发明授权

US06297095B1 Memory device that includes passivated nanoclusters and method for manufacture 有权
标题翻译：包含钝化纳米簇的记忆体装置及其制造方法
公开(公告)号：US06297095B1
公开(公告)日：2001-10-02
申请号：US09596399
申请日：2000-06-16
申请人： Ramachandran Muralidhar , Chitra K. Subramanian , Sucharita Madhukar , Bruce E. White , Michael A. Sadd , Sufi Zafar , David L. O'Meara , Bich-Yen Nguyen
发明人： Ramachandran Muralidhar , Chitra K. Subramanian , Sucharita Madhukar , Bruce E. White , Michael A. Sadd , Sufi Zafar , David L. O'Meara , Bich-Yen Nguyen
IPC分类号： H01L21336
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/66439 , H01L29/7888
摘要： A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are then formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).
摘要翻译：提出了一种具有浮动栅极的半导体存储器件，其包括多个纳米团簇（21）和用于制造这种器件的技术。该器件通过首先提供其上形成有隧道介电层（14）的半导体衬底（12）形成。然后在隧道介电层（14）上生长多个纳米团簇（19）。在纳米团簇（21）生长之后，在纳米团簇（21）上形成控制电介质层（20）。为了防止形成的纳米团簇（21）的氧化，可以在形成控制电介质层（20）之前使用各种技术将纳米团簇（21）进行封装。然后在控制电介质（20）上形成栅极（24），并且选择性地去除不在栅电极下面的控制电介质，多个纳米团簇和栅极电介质的部分。在形成间隔物（35）之后，然后通过注入在半导体层（12）中形成源极和漏极区域（32,34），使得沟道区域形成在栅极下面的源极和漏极区域（32,34）之间电极（24）。

25. 发明授权

US5494837A Method of forming semiconductor-on-insulator electronic devices by growing monocrystalline semiconducting regions from trench sidewalls 失效
标题翻译：通过从沟槽侧壁生长单晶半导体区域来形成绝缘体上半导体电子器件的方法
公开(公告)号：US5494837A
公开(公告)日：1996-02-27
申请号：US312874
申请日：1994-09-27
申请人： Chitra K. Subramanian , Gerold W. Neudeck
发明人： Chitra K. Subramanian , Gerold W. Neudeck
IPC分类号： H01L21/8249 , H01L27/06 , H01L27/12 , H01L29/06 , H01L29/78 , H01L21/8232
CPC分类号： H01L27/1203 , H01L21/8249 , H01L27/0623 , H01L29/0653 , H01L29/7834
摘要： A method of forming a semiconductor-on-insulator (SOI) electronic device includes the steps of etching a semiconductor substrate to form a plurality of adjacent trenches therein and then forming electrically insulating layers on bottoms of the trenches. Epitaxial lateral overgrowth (ELO) is then performed to grow respective monocrystalline semiconducting regions in the trenches. These semiconducting regions are preferably grown from a sidewall of each trench onto a respective insulating layer and fill each trench. Monocrystalline active regions of the electronic device are then formed in the semiconducting regions and also in the substrate, adjacent the trench sidewalls. For example, a monocrystalline trench isolated extrinsic base region of a bipolar junction transistor (BJT) can be formed in a semiconducting region in a respective trench, and a corresponding intrinsic base region and an intrinsic collector region can be formed in the substrate, adjacent the semiconducting region. Alternatively, trench isolated source and drain regions of a field effect transistor (FET) can be formed in one or more adjacent semiconducting regions and the corresponding channel region of the FET can be formed therebetween.
摘要翻译：一种形成绝缘体上半导体（SOI）电子器件的方法包括以下步骤：蚀刻半导体衬底以在其中形成多个相邻的沟槽，然后在沟槽底部形成电绝缘层。然后进行外延横向过度生长（ELO）以在沟槽中生长相应的单晶半导体区域。这些半导体区域优选地从每个沟槽的侧壁生长到相应的绝缘层上并填充每个沟槽。然后，电子器件的单晶有源区形成在半导体区域中，并且在衬底中形成，与沟槽侧壁相邻。例如，可以在各沟槽中的半导体区域中形成双极结型晶体管（BJT）的单晶沟隔离外部基极区域，并且可以在衬底中形成相应的本征基极区域和固有集电极区域半导体区域。或者，可以在一个或多个相邻半导体区域中形成场效应晶体管（FET）的沟槽隔离源极和漏极区域，并且可以在其间形成FET的对应沟道区域。

26. 发明授权

US06738303B1 Technique for sensing the state of a magneto-resistive random access memory 有权
标题翻译：用于感测磁阻随机存取存储器的状态的技术
公开(公告)号：US06738303B1
公开(公告)日：2004-05-18
申请号：US10305736
申请日：2002-11-27
申请人： Chitra K. Subramanian , Bradley J. Garni
发明人： Chitra K. Subramanian , Bradley J. Garni
IPC分类号： G11C702
CPC分类号： G11C11/15
摘要： The state of a MRAM cell is detected when the magnetic tunnel junction (MTJ) of the MRAM cell has a reduced bias from the maximum voltage that is used for biasing. In one example, the MTJ of the selected cell and the MTJ of a reference cell are both biased to a first voltage. The MTJs then discharge this bias asymptotically (RC time constant based utilizing bit line capacitance and MTJ resistance) to a lower voltage such as ground but at rates that are different for the selected cell versus the reference cell due to MTJ resistance differential. At a predetermined time the voltage differential is detected. In another example, the MTJs are precharged to a low voltage then are driven asymptotically toward a higher voltage. Thus, at the time of sensing for both cases, the voltage across the MTJ is less than the bias voltage that is being used.
摘要翻译：当MRAM单元的磁隧道结（MTJ）具有从用于偏置的最大电压的偏差减小时，检测到MRAM单元的状态。在一个示例中，所选择的单元的MTJ和参考单元的MTJ均被偏置到第一电压。然后，MTJs渐近地将该偏置（基于利用位线电容和MTJ电阻的RC时间常数）放电到较低电压（例如接地），但是由于MTJ电阻差，对于所选择的单元与参考单元不同的速率。在预定时间，检测到电压差。在另一个例子中，MTJs被预充电到低电压，然后渐近地向更高的电压驱动。因此，在感测两种情况下，MTJ两端的电压小于所使用的偏置电压。

27. 发明授权

US5958508A Process for forming a semiconductor device 失效
标题翻译：用于形成半导体器件的工艺
公开(公告)号：US5958508A
公开(公告)日：1999-09-28
申请号：US828635
申请日：1997-03-31
申请人： Olubunmi Olufemi Adetutu , Dean J. Denning , James D. Hayden , Chitra K. Subramanian , Arkalgud R. Sitaram
发明人： Olubunmi Olufemi Adetutu , Dean J. Denning , James D. Hayden , Chitra K. Subramanian , Arkalgud R. Sitaram
IPC分类号： H01L29/43 , C23C16/44 , C23C16/455 , H01L21/02 , H01L21/205 , H01L21/28 , H01L21/768 , H01L21/8242 , H01L21/8244 , H01L21/8247 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , C23C16/00 , H01L21/285
CPC分类号： C23C16/45523 , H01L21/76895 , H01L28/60
摘要： A metal-semiconductor layer (26) is formed over an insulating layer (20) such that the metal-semiconductor layer (26) is graded to have varying amounts of the semiconductor and metal throughout the layer. In one embodiment, the metal-semiconductor layer (26) has relatively higher silicon content near the layer's lower and upper surfaces. At the midpoint, the layer is close to stoichiometric tungsten silicide. In another embodiment, a metal-semiconductor-nitrogen layer is formed having nitrogen nearer the lower surface and essentially no nitrogen near the upper surface. The layer (26) can be formed using chemical vapor deposition or sputtering.
摘要翻译：金属半导体层（26）形成在绝缘层（20）上，使得金属半导体层（26）被分级以在整个层中具有不同量的半导体和金属。在一个实施例中，金属半导体层（26）在层的下表面和上表面附近具有相对较高的硅含量。在中点处，该层接近化学计量的硅化钨。在另一个实施方案中，形成具有更靠近下表面的氮并且在上表面附近基本上不含氮的金属 - 半导体 - 氮层。层（26）可以使用化学气相沉积或溅射形成。

28. 发明授权

US5824579A Method of forming shared contact structure 失效
标题翻译：形成共同接触结构的方法
公开(公告)号：US5824579A
公开(公告)日：1998-10-20
申请号：US632207
申请日：1996-04-15
申请人： Chitra K. Subramanian , James D. Hayden
发明人： Chitra K. Subramanian , James D. Hayden
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , Y10S148/02
摘要： A shared contact structure (30) is formed to electrically connect three coupling layers (59,60,46) to each other and to an active region (33) in a semiconductor substrate (31). A first coupling layer (59) and a second coupling layer (60) are formed such that they are physically isolated from each other. The second coupling layer (60) is formed such that it is in physical contact with the active region (33). A contact opening (45) is formed, which exposes a portion of coupling layers (59, 60). The third coupling layer (46) is then formed so that it is in electrical contact with the second coupling layer (60) and the first coupling layer (59).
摘要翻译：形成共享接触结构（30）以将三个耦合层（59,60,46）彼此电连接到半导体衬底（31）中的有源区（33）。形成第一耦合层（59）和第二耦合层（60），使得它们彼此物理隔离。第二耦合层（60）形成为与活性区域（33）物理接触。形成接触开口（45），其露出一部分耦合层（59,60）。然后形成第三耦合层（46），使得其与第二耦合层（60）和第一耦合层（59）电接触。

29. 发明申请

US20130301346A1 SELF REFERENCING SENSE AMPLIFIER FOR SPIN TORQUE MRAM 有权
标题翻译：自适应感应放大器用于旋转扭矩MRAM
公开(公告)号：US20130301346A1
公开(公告)日：2013-11-14
申请号：US13872993
申请日：2013-04-29
申请人： Chitra K. Subramanian , Syed M. Alam
发明人： Chitra K. Subramanian , Syed M. Alam
IPC分类号： G11C11/16
CPC分类号： G11C11/1673
摘要： Circuitry and a method provide self-referenced sensing of a resistive memory cell by using its characteristic of resistance variation with applied voltage in one state versus a relatively constant resistance regardless of the applied voltage in its opposite state. Based on an initial bias state with equalized resistances, a current comparison at a second bias state between a mock bit line and a bit line is used to determine the state of the memory cell, since a significant difference in current implies that the memory cell state has a significant voltage coefficient of resistance. An offset current applied to the mock bit line optionally may be used to provide symmetry and greater sensing margin.
摘要翻译：电路和方法通过使用其在一个状态下的施加电压与相对恒定电阻的电阻变化的特性来提供电阻式存储器单元的自参考感测，而不管其相反状态下的施加电压如何。基于具有均衡电阻的初始偏置状态，使用模拟位线和位线之间的第二偏置状态下的电流比较来确定存储器单元的状态，因为电流的显着差异意味着存储单元状态具有显着的电阻系数。施加到模拟位线的偏移电流可选地可以用于提供对称性和更大的感测余量。

30. 发明授权

US5668021A Process for fabricating a semiconductor device having a segmented channel region 失效
标题翻译：具有分段通道区域的半导体器件的制造方法
公开(公告)号：US5668021A
公开(公告)日：1997-09-16
申请号：US658972
申请日：1996-06-04
申请人： Chitra K. Subramanian , James D. Hayden
发明人： Chitra K. Subramanian , James D. Hayden
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/78 , H01L21/266
CPC分类号： H01L29/66583 , H01L29/1045 , H01L29/42376 , H01L29/66553 , H01L29/66537 , H01L29/7833
摘要： A process for fabricating an MOS device (44) having a segmented channel region (48) includes the fabrication of a compound MOS gate electrode (46). Both the segmented channel region (48) and the MOS gate electrode (46) are formed by creating an opening (18) and an insulating layer (16) overlying a first polycrystalline silicon layer (14). The lateral extent of both the MOS gate electrode (46) and a buried junction region (24) formed in the semiconductor substrate (10) are defined by first sidewall spacer (22) and a second sidewall spacer (32) formed adjacent to the first sidewall spacer (22).
摘要翻译：制造具有分段沟道区（48）的MOS器件（44）的工艺包括制造复合MOS栅电极（46）。通过在第一多晶硅层（14）上形成开口（18）和绝缘层（16）来形成分段通道区域（48）和MOS栅电极（46）。形成在半导体衬底（10）中的MOS栅电极（46）和掩埋结区（24）的横向范围由第一侧壁间隔件（22）和与第一侧壁间隔件（32）相邻形成的第二侧壁间隔件侧壁间隔件（22）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式