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21. 发明授权

US5497032A Semiconductor device and lead frame therefore 失效
标题翻译：因此，半导体器件和引线框架
公开(公告)号：US5497032A
公开(公告)日：1996-03-05
申请号：US213720
申请日：1994-03-16
申请人： Kazuto Tsuji , Yoshiyuki Yoneda , Hideharu Sakoda , Michio Sono , Ichiro Yamaguchi , Toshio Hamano , Yoshihiro Kubota , Michio Hayakawa , Yoshihiko Ikemoto , Yukio Saigo , Naomi Miyaji
发明人： Kazuto Tsuji , Yoshiyuki Yoneda , Hideharu Sakoda , Michio Sono , Ichiro Yamaguchi , Toshio Hamano , Yoshihiro Kubota , Michio Hayakawa , Yoshihiko Ikemoto , Yukio Saigo , Naomi Miyaji
IPC分类号： H01L23/057 , H01L23/10 , H01L23/433 , H01L23/495 , H01L23/02 , H01L23/48 , H01L23/52
CPC分类号： H01L23/057 , H01L23/10 , H01L23/4334 , H01L23/49541 , H01L23/49548 , H01L24/29 , H01L24/49 , H01L2224/29339 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/48091 , H01L2224/48247 , H01L2224/48253 , H01L2224/48257 , H01L2224/49109 , H01L2224/4911 , H01L2224/49171 , H01L2224/73265 , H01L2224/83805 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/10329 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/16152 , H01L2924/16195 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011
摘要： A semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.
摘要翻译：具有密封半导体器件的封装的半导体器件包括基底，并且在基底的表面上形成金属膜。半导体芯片形成在金属膜上。形成在半导体芯片上的焊盘通过导线连接到金属膜。在金属膜上形成密封层。导线形成在玻璃层上。在金属膜上形成连接层，并含有导电粒子。连接层与用于电源系统的引线接触并将金属膜连接到引线。

22. 发明授权

US08097954B2 Adhesive layer forming a capacitor dielectric between semiconductor chips 有权
标题翻译：粘合层在半导体芯片之间形成电容器电介质
公开(公告)号：US08097954B2
公开(公告)日：2012-01-17
申请号：US11508289
申请日：2006-08-23
申请人： Kaname Ozawa , Mitsutaka Sato , Yoshiyuki Yoneda
发明人： Kaname Ozawa , Mitsutaka Sato , Yoshiyuki Yoneda
IPC分类号： H01L23/58
CPC分类号： H01L24/49 , H01L23/50 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/05554 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/48229 , H01L2224/48465 , H01L2224/4903 , H01L2224/4911 , H01L2224/49171 , H01L2224/4945 , H01L2224/73204 , H01L2224/73265 , H01L2224/85191 , H01L2225/06506 , H01L2225/0651 , H01L2225/06572 , H01L2225/06582 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15787 , H01L2924/16195 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2924/19107 , H01L2924/30105 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2924/00015
摘要： A semiconductor device of the invention includes a substrate in which a power-supply electrode and a ground electrode are provided. A first semiconductor chip is disposed over the substrate and has a first conductor layer formed on a surface facing a second semiconductor chip. A second conductor layer is disposed over the first semiconductor chip and has a second conductor layer formed on a surface facing the first semiconductor chip. And an adhesive layer is disposed between the first conductor layer and the second conductor layer and bonds together the first semiconductor chip and the second semiconductor chip. In the semiconductor device, the adhesive layer and the first and second conductor layers function as a capacitor.
摘要翻译：本发明的半导体器件包括其中设置有电源电极和接地电极的基板。第一半导体芯片设置在衬底上并且具有形成在面向第二半导体芯片的表面上的第一导体层。第二导体层设置在第一半导体芯片的上方，并且具有形成在面向第一半导体芯片的表面上的第二导体层。并且粘合剂层设置在第一导体层和第二导体层之间并且将第一半导体芯片和第二半导体芯片接合在一起。在半导体器件中，粘合剂层和第一和第二导体层用作电容器。

23. 发明申请

US20060223340A1 Manufacturing managing method of semiconductor devices and a semiconductor substrate 审中-公开
标题翻译：半导体器件和半导体衬底的制造管理方法
公开(公告)号：US20060223340A1
公开(公告)日：2006-10-05
申请号：US11229728
申请日：2005-09-20
申请人： Yoshiyuki Yoneda
发明人： Yoshiyuki Yoneda
IPC分类号： H01L21/00
CPC分类号： H01L21/67294 , H01L22/20 , H01L23/3114 , H01L23/5227 , H01L23/525 , H01L23/544 , H01L24/10 , H01L24/13 , H01L2223/54466 , H01L2224/0554 , H01L2224/05548 , H01L2224/05573 , H01L2224/05647 , H01L2224/13 , H01L2224/13082 , H01L2224/131 , H01L2224/1357 , H01L2224/136 , H01L2224/16 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/181 , H01L2224/13099 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A managing method of manufacturing semiconductor devices is disclosed. The method comprises the steps of: providing at least one tag region on a semiconductor substrate in which plural semiconductor devices have been formed, the tag region being provided with a tag which can read/write information without making physical contact; writing manufacturing managing information of each of the semiconductor devices into the tag without making contact with the semiconductor substrate; and reading the manufacturing managing information from the tag after dividing the semiconductor substrate, and selecting non-defective semiconductor devices based on the manufacturing managing information.
摘要翻译：公开了制造半导体器件的管理方法。该方法包括以下步骤：在形成有多个半导体器件的半导体衬底上提供至少一个标签区域，标签区域设置有可以在不进行物理接触的情况下读取/写入信息的标签; 将每个半导体器件的制造管理信息写入标签中而不与半导体衬底接触; 以及在划分半导体衬底之后从标签读取制造管理信息，并且基于制造管理信息选择无缺陷的半导体器件。

24. 发明申请

US20060040532A1 Method of designing circuit board 失效
标题翻译：电路板设计方法
公开(公告)号：US20060040532A1
公开(公告)日：2006-02-23
申请号：US11019156
申请日：2004-12-23
申请人： Kaname Ozawa , Mitsutaka Sato , Tetsuya Fujisawa , Yoshiyuki Yoneda , Ryuji Nomoto , Yoshitaka Aiba
发明人： Kaname Ozawa , Mitsutaka Sato , Tetsuya Fujisawa , Yoshiyuki Yoneda , Ryuji Nomoto , Yoshitaka Aiba
IPC分类号： H01R13/648
CPC分类号： G06F17/5068 , H05K3/0005
摘要： A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.
摘要翻译：一种能够高效率地绘制高密度导线的电路板的设计方法。大鼠巢通过连接电子装置的端子的连接垫和通过线路的外部连接端子形成。然后选择大鼠巢线密度最高的区域，并且在具有最大密度的大鼠巢的区域中设置与导线的路线和尺寸相关的设计规则。然后将导体线放置在具有最高密度的大鼠巢的区域，并且确定导线是否可以放置在具有最大密度的大鼠巢的密度的区域。如果导体线不能铺设，则设计规则和布线的设置，如果可以铺设导线，则通过设定的规则布置其余区域的导体线。

25. 发明申请

US20050244414A1 Method to ameliorate osteolysis and metastasis 审中-公开
标题翻译：改善骨质溶解和转移的方法
公开(公告)号：US20050244414A1
公开(公告)日：2005-11-03
申请号：US11109470
申请日：2005-04-18
申请人： Gregory Mundy , Yoshiyuki Yoneda , Theresa Guise
发明人： Gregory Mundy , Yoshiyuki Yoneda , Theresa Guise
IPC分类号： C12N15/09 , A61K9/08 , A61K31/66 , A61K31/675 , A61K38/00 , A61K39/395 , A61K45/06 , A61P35/00 , A61P43/00 , C07K16/22 , C07K16/24 , C07K16/26 , C12P21/08 , A61K31/663
CPC分类号： C07K16/244 , A61K38/00 , A61K45/06 , C07K16/22 , C07K16/241 , C07K16/26
摘要： A therapeutically effective amount of an antibody for a compound selected from the group consisting of PTHrp, TGFα, IL-1α, IL-1β, IL-6, Lymphotoxin, TNF, PGE; 1,25 dihydroxy vitamin D3 and an antigenic fragment thereof used in the treatment of cancer metastasis to bone and cancer cell growth in bone as well as osteolysis and symptomatic sequelae thereof. An antibody immunoreactive with parathyroid hormone-related protein (PTHrp) is particularly preferred. Antibodies with human characteristics are included in the invention for application of the invention method to human subjects. Also, the antibody can be administered in an injectable is formulation in combination with a therapeutically effective amount of a bisphosphonate or pyrophosphate having the general structure formula wherein X is a linking moiety allowing for the interconnection of the phosphonate groups, and pharmaceutically acceptable salts, hydrates and partial hydrates thereof. The antibody and bisphosphonate act synergistically in the treatment of cancer metastases to bone and symptomatic sequelae thereof and particularly as regards bone resorption.
摘要翻译：治疗有效量的选自PTHrp，TGFα，IL-1α，IL-1β，IL-6，淋巴毒素，TNF，PGE的化合物的抗体; 1,25二羟基维生素D 3及其抗原性片段用于治疗癌症转移至骨骼和骨细胞中的癌细胞，以及骨溶解及其症状后遗症。与甲状旁腺激素相关蛋白（PTHrp）免疫反应的抗体是特别优选的。具有人类特征的抗体包括在本发明中，用于将本发明方法应用于人类受试者。此外，抗体可以以可注射的制剂与治疗有效量的具有以下通式结构式的二膦酸盐或焦磷酸盐组合施用：其中X是允许膦酸酯基团互连的连接部分，以及药学上可接受的盐，水合物和其部分水合物。抗体和双膦酸盐协同作用于治疗癌症转移至骨骼及其有症状的后遗症，特别是关于骨吸收。

26. 发明授权

US06777250B1 Manufacture of wafer level semiconductor device with quality markings on the sealing resin 有权
公开(公告)号：US06777250B1
公开(公告)日：2004-08-17
申请号：US09686958
申请日：2000-10-12
申请人： Shinsuke Nakajyo , Yoshiyuki Yoneda , Hideharu Sakoda
发明人： Shinsuke Nakajyo , Yoshiyuki Yoneda , Hideharu Sakoda
IPC分类号： H01L2166
CPC分类号： H01L22/20 , H01L2223/5448 , H01L2224/274
摘要： A method of manufacturing semiconductor device in the method of manufacturing wafer level semiconductor device that can search the defective products from the marking information even when sealing resin is formed on the wafer and a semiconductor device manufactured with the same method. A method of manufacturing wafer level semiconductor comprises a process to seal with a resin material the surface of wafer having the front surface and rear surface and forming a plurality of semiconductor chips on the front surface, a first marking process for marking the position information corresponding to each chip to the region of each chip at the rear surface of the wafer, a process for performing the electrical test to each chip, a second marking process for marking the result of the electrical test to the region of each chip at the rear surface of the wafer and a dicing process for dicing the wafer to each chip.

28. 发明授权

US06376921B1 Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame 有权
标题翻译：半导体装置，半导体装置的制造方法，引线框架及其制造方法
公开(公告)号：US06376921B1
公开(公告)日：2002-04-23
申请号：US09192201
申请日：1998-11-16
申请人： Yoshiyuki Yoneda , Ryuji Nomoto , Toshiyuki Motooka , Kazuto Tsuji , Junichi Kasai , Toshimi Kawahara , Hideharu Sakoda , Kenji Itasaka , Terumi Kamifukumoto
发明人： Yoshiyuki Yoneda , Ryuji Nomoto , Toshiyuki Motooka , Kazuto Tsuji , Junichi Kasai , Toshimi Kawahara , Hideharu Sakoda , Kenji Itasaka , Terumi Kamifukumoto
IPC分类号： H01L2328
CPC分类号： H01L21/4832 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/6833 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L24/97 , H01L25/105 , H01L29/0657 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/1134 , H01L2224/13099 , H01L2224/16 , H01L2224/45015 , H01L2224/45144 , H01L2224/45565 , H01L2224/45644 , H01L2224/4569 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/48464 , H01L2224/48465 , H01L2224/48471 , H01L2224/4848 , H01L2224/48599 , H01L2224/49171 , H01L2224/73265 , H01L2224/78301 , H01L2224/7865 , H01L2224/83001 , H01L2224/85001 , H01L2224/85051 , H01L2224/85181 , H01L2224/85205 , H01L2224/85365 , H01L2224/85986 , H01L2224/92247 , H01L2224/97 , H01L2225/1035 , H01L2225/107 , H01L2225/1094 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01039 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10161 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/18165 , H01L2924/19043 , H01L2924/3011 , H05K1/181 , H05K3/303 , H05K3/305 , H05K3/3436 , H05K3/3442 , H05K2201/09045 , H05K2201/10727 , H05K2201/10977 , Y02P70/613 , H01L2224/85 , H01L2924/01004 , H01L2924/00011 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： A semiconductor device includes a semiconductor element, a resin package sealing the semiconductor element, resin projections protruding downward from a mounting surface of the resin package, metallic film portions provided to the resin projections, and connecting members electrically connecting the semiconductor elements to the metallic film parts.
摘要翻译：半导体器件包括半导体元件，密封半导体元件的树脂封装，从树脂封装的安装表面向下突出的树脂突起，设置在树脂突起上的金属膜部分和将半导体元件电连接到金属膜的连接构件部分。

29. 发明授权

US5891758A Semiconductor device and method for manufacturing semiconductor device 失效
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US5891758A
公开(公告)日：1999-04-06
申请号：US962395
申请日：1997-10-31
申请人： Toshiyuki Honda , Akihiro Oku , Takanori Watanabe , Kazuto Tsuji , Yoshiyuki Yoneda
发明人： Toshiyuki Honda , Akihiro Oku , Takanori Watanabe , Kazuto Tsuji , Yoshiyuki Yoneda
IPC分类号： H01L23/12 , H01L21/56 , H01L21/68 , H01L23/31 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/568 , H01L21/565 , H01L23/3107 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/49109 , H01L2224/49171 , H01L2224/73265 , H01L2924/181 , H01L2924/18165 , Y10T29/49169
摘要： A method of manufacturing a semiconductor device includes the steps of: mounting a semiconductor chip on a holding board having electrode accommodation recesses formed thereon, and mounting electrode members to the electrode accommodation recesses, the electrode members being formed separately from the semiconductor element; electrically connecting electrode pads formed on the semiconductor chip with the electrode members; forming a resin package for sealing the semiconductor chip on the holding board by using a die, the holding board serving as a part of the die; and separating the resin package including the electrode members from the holding board. A semiconductor device includes: a semiconductor chip; a resin package for sealing the semiconductor chip; electrode members which are embedded in and held by the resin package and which are partly exposed from a mounting surface so as to form external connection terminals; and connecting parts electrically connecting electrode pads on the semiconductor chip with the electrode members.
摘要翻译：一种制造半导体器件的方法包括以下步骤：将半导体芯片安装在其上形成有电极容纳凹部的保持板上，以及将电极构件安装到电极容置凹部，电极构件与半导体元件分开形成; 将形成在半导体芯片上的电极焊盘与电极部件电连接; 通过使用模具形成用于将所述保持板上的半导体芯片密封的树脂封装，所述保持板用作所述管芯的一部分; 以及将包括电极构件的树脂封装从保持板分离。半导体器件包括：半导体芯片; 用于密封半导体芯片的树脂封装; 电极构件，其嵌入并保持在树脂封装中，并且从安装表面部分露出以形成外部连接端子; 以及将半导体芯片上的电极焊盘与电极部件电连接的部分。

30. 发明授权

US5656550A Method of producing a semicondutor device having a lead portion with outer connecting terminal 失效
标题翻译：一种具有带有外部连接端子的引线部分的半导体器件的制造方法
公开(公告)号：US5656550A
公开(公告)日：1997-08-12
申请号：US611007
申请日：1996-03-05
申请人： Kazuto Tsuji , Yoshiyuki Yoneda , Hideharu Sakoda , Ryuji Nomoto , Eiji Watanabe , Seiichi Orimo , Masanori Onodera , Masaki Waki
发明人： Kazuto Tsuji , Yoshiyuki Yoneda , Hideharu Sakoda , Ryuji Nomoto , Eiji Watanabe , Seiichi Orimo , Masanori Onodera , Masaki Waki
IPC分类号： H01L21/56 , H01L21/68 , H01L23/31 , H01L23/495 , H01L21/60
CPC分类号： H01L24/49 , H01L21/565 , H01L21/6835 , H01L23/3107 , H01L23/3114 , H01L23/3128 , H01L23/49548 , H01L23/49551 , H01L24/97 , H01L2221/68377 , H01L2224/05554 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45164 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/49433 , H01L2224/73265 , H01L2224/97 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2924/00014 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/12042 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H01L2924/3011 , Y10T29/49121
摘要： This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion. Also, the semiconductor device has a semiconductor chip having a predetermined number of electrode pads, a predetermined number of leads electrically connected to the electrode pads, each of the leads having a projecting terminal portion formed by bending the lead, and a resin portion sealing the semiconductor chip and the leads, wherein the terminal portions are exposed from one face of the resin portion.
摘要翻译：本发明涉及一种半导体器件，其中多个外部端子以平坦表面的格子状排列。半导体器件具有半导体芯片，具有引线部分的引线部分和与引线部分整体连接的外部连接端子，引线部分电连接到半导体芯片，引线部分从半导体芯片向外延伸，外部连接从所述引线部分向下延伸的端子，密封所述半导体芯片和所述引线部分的密封树脂，所述半导体芯片的底面和所述引线部分的底面从所述密封树脂露出;以及绝缘构件，和半导体芯片的底面。此外，半导体器件具有预定数量的电极焊盘的半导体芯片，与电极焊盘电连接的预定数量的引线，每个引线具有通过弯曲引线形成的突出端子部分和密封半导体芯片和引线，其中端子部分从树脂部分的一个面露出。

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