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21. 发明申请

US20080150820A1 TUBULAR ENDFIRE SLOT-MODE ANTENNA ARRAY WITH INTER-ELEMENT COUPLING AND ASSOCIATED METHODS 有权
标题翻译：带有元件耦合和相关方法的管状端基槽模式天线阵列
公开(公告)号：US20080150820A1
公开(公告)日：2008-06-26
申请号：US12017183
申请日：2008-01-21
申请人： Timothy E. Durham , Griffin K. Gothard , Anthony Mark Jones , Jay Kralovec , Stephen R. Landers , Sean Ortiz , Chris Snyder , Ralph Trosa
发明人： Timothy E. Durham , Griffin K. Gothard , Anthony Mark Jones , Jay Kralovec , Stephen R. Landers , Sean Ortiz , Chris Snyder , Ralph Trosa
IPC分类号： H01Q13/10 , H01Q1/38 , H01P11/00
CPC分类号： H01Q21/065 , H01Q1/38 , Y10T29/49016
摘要： The tubular slot-mode antenna includes an array of slot antenna units carried by a tubular substrate, e.g. a cylindrical substrate, and each slot antenna unit having a pair of patch antenna elements arranged in laterally spaced apart relation about at least one central feed position. Adjacent patch antenna elements of adjacent slot-mode antenna units have respective spaced apart edge portions with predetermined shapes and relative positioning to provide increased capacitive coupling therebetween. The array of slot-mode antenna units may define a plurality of ring-shaped slots coaxial with an axis of the tubular substrate, and a feed arrangement may be coupled thereto to operate the array of slot-mode antenna units in an endfire mode.
摘要翻译：管状槽模式天线包括由管状衬底承载的缝隙天线单元的阵列，例如，圆柱形基板，每个缝隙天线单元具有一对沿着至少一个中央进给位置以横向隔开的关系布置的一对贴片天线元件。相邻槽模式天线单元的相邻贴片天线元件具有预定形状和相对定位的相应间隔开的边缘部分，以在它们之间提供增加的电容耦合。槽模式天线单元的阵列可以限定与管状衬底的轴线同轴的多个环形槽，并且馈送装置可以耦合到其上以在端点模式中操作槽模式天线单元阵列。

22. 发明申请

US20070237233A1 MOTION COMPENSATION IN DIGITAL VIDEO 审中-公开
标题翻译：数字视频中的运动补偿
公开(公告)号：US20070237233A1
公开(公告)日：2007-10-11
申请号：US11733135
申请日：2007-04-09
申请人： Anthony Mark Jones
发明人： Anthony Mark Jones
IPC分类号： H04N11/02 , H04B1/66
CPC分类号： H04N19/57 , H04N19/43 , H04N19/51 , H04N19/523 , H04N19/53 , H04N19/533 , H04N19/56
摘要： Embodiments of the invention include a system directed to generating motion vectors in digital video by using multiple phases in sequence. In a first phase, a match signature in the frequency domain is evaluated to find one or more minimum motion vector candidates for a particular macroblock in video. In a second phase, the vector candidates are further refined using smaller-sized portions of the macroblock and fractional motion vectors to determine a small list of minimum vector choices for each macroblock that maintain vector integrity within the vector field of the frame and across nearby frames.
摘要翻译：本发明的实施例包括一种系统，其用于通过使用多个相位来产生数字视频中的运动矢量。在第一阶段中，评估频域中的匹配签名以找到视频中特定宏块的一个或多个最小运动矢量候选。在第二阶段中，使用宏块和分数运动向量的较小尺寸的部分进一步细化向量候选，以确定维持帧的向量场内和跨附近帧的向量完整性的每个宏块的最小向量选择的小列表。

23. 发明授权

US07206870B2 Data interface register structure with registers for data, validity, group membership indicator, and ready to accept next member signal 有权
标题翻译：数据接口寄存器结构，具有数据寄存器，有效性，组成员指标，并准备接受下一个成员信号
公开(公告)号：US07206870B2
公开(公告)日：2007-04-17
申请号：US10871347
申请日：2004-06-18
申请人： Anthony Mark Jones
发明人： Anthony Mark Jones
IPC分类号： G06F13/14 , G06F17/50
CPC分类号： G06F17/5045
摘要： Embodiments of the invention include a system for an integrated circuit development. Elements of the development system include hardware and software objects. Boundaries of the objects may include register structures, which regulate data transfer between and within objects. Protocols, including forward and reverse protocols indicate when data is ready to be accepted, and when it is valid and ready for use. Further, specific protocol information indicates the beginning and end of a group of data. Specialized objects include fork and join objects. Fork objects have more register structures for output than they do for input, while join objects have fewer register structures for output than they do for input.
摘要翻译：本发明的实施例包括用于集成电路开发的系统。开发系统的元素包括硬件和软件对象。对象的边界可以包括寄存器结构，其调节对象内和之间的数据传输。协议，包括正向和反向协议，表明数据准备好被接受，何时有效并准备使用。此外，特定协议信息指示一组数据的开始和结束。专门的对象包括fork和join对象。叉形物体的输出结果与输入相比有更多的寄存器结构，而连接对象的输出寄存器结构比输入的结构少。

24. 发明授权

US5956741A Interface for connecting a bus to a random access memory using a swing buffer and a buffer manager 失效
标题翻译：使用摆动缓冲器和缓冲管理器将总线连接到随机存取存储器的接口
公开(公告)号：US5956741A
公开(公告)日：1999-09-21
申请号：US950892
申请日：1997-10-15
申请人： Anthony Mark Jones
发明人： Anthony Mark Jones
IPC分类号： G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F13/00 , G06F13/16 , G06F13/28 , H04N7/01 , H04N7/26 , H04N7/50
CPC分类号： G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/16 , G06F13/28 , H04N19/423 , H04N19/61 , H04N19/13 , H04N19/91
摘要： A configurable RAM interface connecting a bus to RAM is adapted to receiving large multiword variable length tokens at a high data arrival rate, using a swing buffer and a buffer manager. An address source provides complete addresses to the interface. The buffer manager has a state machine which transitions among a plurality of states, maintaining status information about the buffers, allocating the buffers for reference by a write address generator, clearing the buffers for occupation by subsequently arriving data, and maintaining status information concerning the buffers. The buffer manager also examines tokens of received data in order to update the status of the arrival buffer.
摘要翻译：将总线连接到RAM的可配置RAM接口适于使用摆动缓冲器和缓冲器管理器以高数据到达速率接收大量多字可变长度令牌。地址源为接口提供完整的地址。缓冲器管理器具有状态机，其在多个状态之间转换，维护关于缓冲器的状态信息，分配缓冲区以供写地址生成器参考，通过随后到达的数据清除用于占用的缓冲器，以及维护关于缓冲器的状态信息。缓冲区管理器还检查接收到的数据的令牌，以便更新到达缓冲区的状态。

25. 发明授权

US5910960A Signal processing apparatus and method 失效
标题翻译：信号处理装置及方法
公开(公告)号：US5910960A
公开(公告)日：1999-06-08
申请号：US480721
申请日：1995-06-07
申请人： Anthony Peter J. Claydon , Charles D. MacFarlane , Richard J. Gammack , Anthony Mark Jones , William P. Robbins , Mark Barnes
发明人： Anthony Peter J. Claydon , Charles D. MacFarlane , Richard J. Gammack , Anthony Mark Jones , William P. Robbins , Mark Barnes
IPC分类号： H03K5/24 , H03M13/15 , H04L1/00 , H04L25/03 , H04L25/06 , H04L27/02 , H04N5/44 , H03M13/00
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H04L1/0045 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04N21/4382 , H04N5/4446 , H04N5/4401
摘要： A CMOS Reed-Solomon decoding circuit calculates syndromes, executes a Berlekamp algorithm, performs a Chien Search, and corrects a delayed version of the received data according to a calculated magnitude of error. The circuit is optimized in terms of chip territory and circuit complexity. Signals are provided to indicate uncorrectable packet errors and other transmission errors.
摘要翻译： CMOS Reed-Solomon解码电路计算校正子，执行Berlekamp算法，执行Chien搜索，并根据计算的误差大小校正接收数据的延迟版本。该电路在芯片领域和电路复杂性方面进行了优化。提供信号以指示不可纠正的分组错误和其他传输错误。

26. 发明授权

US08605788B2 System for compressing and de-compressing data used in video processing 有权
标题翻译：用于压缩和解压缩视频处理中使用的数据的系统
公开(公告)号：US08605788B2
公开(公告)日：2013-12-10
申请号：US13474990
申请日：2012-05-18
申请人： Anthony Mark Jones
发明人： Anthony Mark Jones
IPC分类号： H04N11/02 , H03M7/00 , H03M7/34 , H03M5/00
CPC分类号： H04N19/51 , H03M7/4012 , H04N19/43 , H04N19/523 , H04N19/82
摘要： Disclosed are systems and methods used in motion estimation and particularly for data compression. Embodiments of the invention may store and operate on an n-bit value in less than n bits. In one embodiment, if the multi-bit value is less than a threshold, then the multi-bit value is stored in the reduced-bit storage directly, with no loss of precision. If the multi-bit value is greater than the threshold, then the Most Significant Bits (MSBs) of the multi-bit value are shifted onto the reduced-bit storage, and a compression flag set. To decompress, if the compression flag was not set, the bits stored in the reduced-bit storage are merely copied back into the multi-bit value directly. If the compression flag was set, then the bits stored in the reduced-bit storage are shifted (left) by the same amount they were shifted (right) during compression, and an error-minimizing value is added.
摘要翻译：公开了用于运动估计，特别是用于数据压缩的系统和方法。本发明的实施例可以在小于n位的n位值上存储和操作。在一个实施例中，如果多比特值小于阈值，则多比特值直接存储在缩减比特存储中，而不会损失精度。如果多比特值大于阈值，则多比特值的最高有效比特（MSB）被移位到缩减比特存储上，并且设置压缩标志。为了解压缩，如果未设置压缩标志，则存储在缩减比特存储器中的比特直接被复制回多比特值。如果设置了压缩标志，则在压缩期间，存储在减位存储器中的位移动（左）移位（右）相同的量，并且添加错误最小化值。

27. 发明授权

US07865637B2 System of hardware objects 有权
标题翻译：硬件对象系统
公开(公告)号：US07865637B2
公开(公告)日：2011-01-04
申请号：US10871329
申请日：2004-06-18
申请人： Anthony Mark Jones , Paul M. Wasson
发明人： Anthony Mark Jones , Paul M. Wasson
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F17/5045
摘要： Elements of the inventive development system include hardware and software objects. These objects can be instanced, ordered, parameterized, and connected in a software environment to implement different functions. Once in software, the description defines the topology and the properties of a set of objects and hence the overall function. These objects are hierarchically composed from a set of primitive objects. By using a piece of hardware that can model any primitive object set as pre-established encapsulated hardware objects, the topology and properties define a piece of hardware that can perform the desired, implemented, functions. Using embodiments of the invention, circuit designers can design hardware systems with little or no knowledge of hardware or hardware design, requiring only a high-level software description.
摘要翻译：本发明的开发系统的元件包括硬件和软件对象。这些对象可以在软件环境中实例化，排序，参数化和连接，以实现不同的功能。一旦在软件中，描述定义了一组对象的拓扑和属性，从而定义了整体功能。这些对象由一组原始对象分层组成。通过使用可以将任何原始对象集合建模为预先建立的封装硬件对象的硬件，拓扑和属性定义了可执行所需实现的功能的一块硬件。利用本发明的实施例，电路设计者可以很少或不知道硬件或硬件设计的硬件系统，只需要高级软件描述。

28. 发明授权

US07409533B2 Asynchronous communication among hardware object nodes in IC with receive and send ports protocol registers using temporary register bypass select for validity information 有权
标题翻译： IC中的硬件对象节点之间的异步通信与接收和发送端口协议寄存器使用临时寄存器旁路选择有效性信息
公开(公告)号：US07409533B2
公开(公告)日：2008-08-05
申请号：US11326701
申请日：2006-01-06
申请人： Anthony Mark Jones
发明人： Anthony Mark Jones
IPC分类号： G06F15/17
CPC分类号： G06F17/5045
摘要： Embodiments of the invention are directed to an integrated circuit including a communication network that interconnects individual object nodes. The nodes include a receiving port and a sending port, each structured to send messages along communication pathways, which are connected between a sending and a receiving port. Individual communication pathways may operate at different clock frequencies from one another and messages sent along them may be asynchronous from one node to another. Sending ports are structured to stall until the sending port receives notice that the receiving port is able to accept a message. Additionally, sending ports include protocol information that eliminates the necessity for message timing oversight, and instead, the delivery of each message is made on the local level independent of the operating speed of the port's attached processor or of the communication network itself. Messages may be sent across clock boundaries without data loss.
摘要翻译：本发明的实施例涉及一种集成电路，其包括互连各个对象节点的通信网络。节点包括接收端口和发送端口，每个端口被构造为沿着连接在发送端口和接收端口之间的通信路径发送消息。单个通信路径可以在彼此不同的时钟频率下操作，并且沿它们发送的消息可以从一个节点到另一个节点是异步的。发送端口被构造成停止，直到发送端口接收到接收端口能够接受消息的通知。此外，发送端口包括消除了对消息定时监控的必要性的协议信息，而是独立于端口附接的处理器或通信网络本身的操作速度而在每个消息的发送。消息可以跨时钟边界发送，而不会丢失数据。

29. 发明授权

US5984512A Method for storing video information 失效
标题翻译：存储视频信息的方法
公开(公告)号：US5984512A
公开(公告)日：1999-11-16
申请号：US488348
申请日：1995-06-07
申请人： Anthony Mark Jones , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , William P. Robbins , Nicholas Birch , David Andrew Barnes
发明人： Anthony Mark Jones , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , William P. Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52 , G06F17/00
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in select stages and are responsive to a recognized control token for reconfiguring such stages to handle an identified DATA Token. A wide variety of unique supporting subsystems circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.
摘要翻译：一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。控制令牌和数据令牌通过单个双线接口，用于携带控制和令牌格式。令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。重新配置处理电路位于选择阶段，并响应于识别的控制令牌，以重新配置这些阶段来处理所识别的数据令牌。公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等。

30. 发明授权

US5677648A Noise compensated phase locked loop circuit 失效
标题翻译：噪声补偿锁相环电路
公开(公告)号：US5677648A
公开(公告)日：1997-10-14
申请号：US396834
申请日：1995-03-01
申请人： Anthony Mark Jones
发明人： Anthony Mark Jones
IPC分类号： H03K19/003 , H03K17/687 , H03L7/08 , H03L7/089 , H03L7/093 , H03L7/085
CPC分类号： H03L7/0891 , Y10S331/02
摘要： An improved phase locked loop utilizing control logic generated by a phase detector to eliminate sensitivity to uncorrelated noise when the loop is in lock.
摘要翻译：改进的锁相环利用由相位检测器产生的控制逻辑，以消除环路锁定时对不相关噪声的敏感度。

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