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1. 发明授权

US5910960A Signal processing apparatus and method 失效
标题翻译：信号处理装置及方法
公开(公告)号：US5910960A
公开(公告)日：1999-06-08
申请号：US480721
申请日：1995-06-07
申请人： Anthony Peter J. Claydon , Charles D. MacFarlane , Richard J. Gammack , Anthony Mark Jones , William P. Robbins , Mark Barnes
发明人： Anthony Peter J. Claydon , Charles D. MacFarlane , Richard J. Gammack , Anthony Mark Jones , William P. Robbins , Mark Barnes
IPC分类号： H03K5/24 , H03M13/15 , H04L1/00 , H04L25/03 , H04L25/06 , H04L27/02 , H04N5/44 , H03M13/00
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H04L1/0045 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04N21/4382 , H04N5/4446 , H04N5/4401
摘要： A CMOS Reed-Solomon decoding circuit calculates syndromes, executes a Berlekamp algorithm, performs a Chien Search, and corrects a delayed version of the received data according to a calculated magnitude of error. The circuit is optimized in terms of chip territory and circuit complexity. Signals are provided to indicate uncorrectable packet errors and other transmission errors.
摘要翻译： CMOS Reed-Solomon解码电路计算校正子，执行Berlekamp算法，执行Chien搜索，并根据计算的误差大小校正接收数据的延迟版本。该电路在芯片领域和电路复杂性方面进行了优化。提供信号以指示不可纠正的分组错误和其他传输错误。

2. 发明授权

US5793818A Signal processing system 失效
标题翻译：信号处理系统
公开(公告)号：US5793818A
公开(公告)日：1998-08-11
申请号：US471874
申请日：1995-06-07
申请人： Anthony Peter J. Claydon , Richard J. Gammack
发明人： Anthony Peter J. Claydon , Richard J. Gammack
IPC分类号： H03M13/41 , H04L1/00 , H04L7/02 , H04L27/00 , H04L27/22 , H04L27/227 , H04L27/38 , H04N7/24 , H04L27/14
CPC分类号： H04L7/0029 , H04L1/0054 , H04L1/0057 , H04L1/0065 , H04L1/0068 , H04L27/3872 , H04N21/2383 , H04N21/4382 , H04L2027/0028 , H04L2027/0057 , H04L2027/0067 , H04L7/0334 , H04L7/0335
摘要： A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls a sinc interpolator receiving samples at the sampling rate. A loop filter is coupled to the sinc interpolator and to the numerically controlled oscillator. The arrangement is capable of handling various symbol rates. The system includes a circuit for carrier recovery, having a second on-chip numerically controlled oscillator, a digital derotation circuit responsive to the second numerically controlled oscillator, accepting an in phase component and a quadrature component of the sampled signals. An adaptive phase error estimation circuit is coupled in a feedback loop.
摘要翻译：用于采样接收机的CMOS集成信号处理系统包括定时恢复电路，其中片上数控振荡器在周期T处工作，周期T最初等于信号的标称波特率，控制在采样时接收采样的正弦内插器率。环路滤波器耦合到正弦内插器和数控振荡器。该装置能够处理各种符号率。该系统包括用于载波恢复的电路，具有第二片上数控振荡器，响应于第二数控振荡器的数字解旋转电路，接受采样信号的同相分量和正交分量。自适应相位误差估计电路耦合在反馈回路中。

3. 发明授权

US5668831A Signal processing apparatus and method 失效
标题翻译：信号处理装置及方法
公开(公告)号：US5668831A
公开(公告)日：1997-09-16
申请号：US481107
申请日：1995-06-07
申请人： Anthony Peter J. Claydon , Charles D. MacFarlane , Richard J. Gammack , Anthony Mark Jones , William P. Robbins , Mark Barnes
发明人： Anthony Peter J. Claydon , Charles D. MacFarlane , Richard J. Gammack , Anthony Mark Jones , William P. Robbins , Mark Barnes
IPC分类号： H04N7/26 , H03H17/02 , H03H21/00 , H03K5/24 , H03M3/02 , H03M13/00 , H03M13/15 , H03M13/27 , H04B3/06 , H04L1/00 , H04L7/00 , H04L7/033 , H04L7/04 , H04L25/03 , H04L25/06 , H04L27/00 , H04L27/02 , H04L27/06 , H04L27/227 , H04L27/38 , H04N5/00 , H04N5/21 , H04N5/44 , H04N5/455 , H04N5/52 , H04N7/24 , H04N7/30 , H04N21/2383 , H04N21/438 , H03H7/30
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04L7/0334
摘要： An integrated digital communication system utilizing multilevel vestigial sideband transmission is provided. The communication system receives a multi-level pulse-amplitude modulated digital signal from a limited bandwidth channel. The system includes processing stages which demodulate, sample and filter the incoming signal prior to recovery of the digital data. Other stages recover the timing and lock on to the frequency and phase of the transmitted signal, as well as provide for automatic gain control. An adaptive equalizer, error correction circuitry, and an output interface recover the digital data and provide for transfer to other devices.
摘要翻译：提供了利用多电平残留边带传输的集成数字通信系统。通信系统从有限带宽信道接收多电平脉冲幅度调制数字信号。该系统包括在恢复数字数据之前对输入信号进行解调，采样和滤波的处理阶段。其他级恢复定时并锁定到发射信号的频率和相位，并提供自动增益控制。自适应均衡器，纠错电路和输出接口恢复数字数据并提供传输到其他设备。

4. 发明授权

US5491703A Cam with additional row cells connected to match line 失效
标题翻译：带附加行单元的凸轮连接到匹配线
公开(公告)号：US5491703A
公开(公告)日：1996-02-13
申请号：US84566
申请日：1993-06-29
申请人： Catherine L. Barnaby , Richard J. Gammack , Anthony I. Stansfield
发明人： Catherine L. Barnaby , Richard J. Gammack , Anthony I. Stansfield
IPC分类号： G11C15/04 , H03M13/00
CPC分类号： G11C15/04
摘要： A method of accessing a content addressable memory having a plurality of RAM cells connected in an array of rows and columns, each row having a plurality of cells for storing a data word, at least one additional cell for storing a checking bit and a match line for providing a signal to indicate when a match occurs between an input data word and data stored in a row of cells, which method comprises storing in at least one row of cells a data word in data cells of the row and a checking bit in said at least one additonal cell of the row, the checking bit having a value dependent on the content of the data word in accordance with an error checking system, and controlling a memory accessing system to effect an associate operation by inputting to the columns of cells an input word with an input checking bit dependent on said input word in accordance with the same error checking system, comparing the input word and input checking bit with stored contents of each row of cells and in any row where a mismatch of the input data word with the stored data word occurs causing at least two cells in that row to change a signal level on a match line for that row, said memory accessing system being arranged to operate with a time delay for each associate operation which is less than that required for a single cell mismatch. The invention also provides a content addressable memory.
摘要翻译：一种访问具有以行和列的阵列连接的多个RAM单元的内容可寻址存储器的方法，每行具有用于存储数据字的多个单元，用于存储检查位的至少一个附加单元和匹配线用于提供信号以指示何时在输入数据字与存储在一行单元格中的数据之间发生匹配，该方法包括在至少一行单元中存储该行的数据单元中的数据字和所述行中的检查位所述行的至少一个附加单元，所述检查位具有依赖于错误检查系统的取决于所述数据字的内容的值，以及通过输入到所述单元格列来控制存储器访问系统来执行关联操作根据相同的错误检查系统，输入字与具有取决于所述输入字的输入检查位相比较，将输入字和输入检查位与每行单元格的存储内容进行比较，并在任何行w 这里，输入数据字与存储的数据字的不匹配发生，导致该行中的至少两个单元改变该行的匹配线上的信号电平，所述存储器访问系统被布置为以每个关联的时间延迟小于单个单元不匹配所需的操作。本发明还提供一种内容可寻址存储器。

5. 发明授权

US5724396A Signal processing system 失效
标题翻译：信号处理系统
公开(公告)号：US5724396A
公开(公告)日：1998-03-03
申请号：US480976
申请日：1995-06-07
申请人： Anthony Peter J. Claydon , Richard J. Gammack
发明人： Anthony Peter J. Claydon , Richard J. Gammack
IPC分类号： H03M13/41 , H04L1/00 , H04L7/02 , H04L27/00 , H04L27/22 , H04L27/227 , H04L27/38 , H04N7/24 , H04L7/00
CPC分类号： H04L7/0029 , H04L1/0054 , H04L1/0057 , H04L1/0065 , H04L1/0068 , H04L27/3872 , H04N21/2383 , H04N21/4382 , H04L2027/0028 , H04L2027/0057 , H04L2027/0067 , H04L7/0334 , H04L7/0335
摘要： A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls a sinc interpolator receiving samples at the sampling rate. A loop filter is coupled to the sinc interpolator and to the numerically controlled oscillator. The arrangement is capable of handling various symbol rates. The system includes a circuit for carrier recovery having a second on-chip numerically controlled oscillator, a digital derotation circuit responsive to the second numerically controlled oscillator, accepting an in phase component and a quadrature component of the sampled signals. An adaptive phase error estimation circuit is coupled in a feedback loop.
摘要翻译：用于采样接收机的CMOS集成信号处理系统包括定时恢复电路，其中片上数控振荡器在周期T处工作，周期T最初等于信号的标称波特率，控制在采样时接收采样的正弦内插器率。环路滤波器耦合到正弦内插器和数控振荡器。该装置能够处理各种符号率。该系统包括用于载波恢复的电路，具有第二片上数控振荡器，响应于第二数控振荡器的数字解旋转电路，接收采样信号的同相分量和正交分量。自适应相位误差估计电路耦合在反馈回路中。

6. 发明授权

US5761210A Signal processing apparatus and method 失效
标题翻译：信号处理装置及方法
公开(公告)号：US5761210A
公开(公告)日：1998-06-02
申请号：US486750
申请日：1995-06-07
申请人： Anthony Peter J. Claydon , Richard J. Gammack
发明人： Anthony Peter J. Claydon , Richard J. Gammack
IPC分类号： H04N7/26 , H03H17/02 , H03H21/00 , H03K5/24 , H03M3/02 , H03M13/00 , H03M13/15 , H03M13/27 , H04B3/06 , H04L1/00 , H04L7/00 , H04L7/033 , H04L7/04 , H04L25/03 , H04L25/06 , H04L27/00 , H04L27/02 , H04L27/06 , H04L27/227 , H04L27/38 , H04N5/00 , H04N5/21 , H04N5/44 , H04N5/455 , H04N5/52 , H04N7/24 , H04N7/30 , H04N21/2383 , H04N21/438 , G06F11/00
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04L7/0334
摘要： An integrated CMOS circuit is disclosed for deinterleaving transmitted data packets. The circuit operates with a RAM buffer that is no larger than a block of interleaved data. An optimized addressing scheme is provided that minimizes on-chip hardware. The circuit provides an orderly initialization of the buffer, and a suitable emptying process during a channel change or other interruption of data flow.
摘要翻译：公开了用于对所发送的数据分组进行解交织的集成CMOS电路。该电路使用不大于交错数据块的RAM缓冲器。提供了优化的寻址方案，最小化片上硬件。该电路提供缓冲器的有序初始化，以及在通道改变或数据流的其他中断过程中的适当的排空过程。

7. 发明授权

US5574875A Cache memory system including a RAM for storing data and CAM cell arrays for storing virtual and physical addresses 失效
标题翻译：高速缓冲存储器系统包括用于存储数据的RAM和用于存储虚拟和物理地址的CAM单元阵列
公开(公告)号：US5574875A
公开(公告)日：1996-11-12
申请号：US031241
申请日：1993-03-12
申请人： Anthony I. Stansfield , Catherine L. Barnaby , Richard J. Gammack , Roger M. Shepherd
发明人： Anthony I. Stansfield , Catherine L. Barnaby , Richard J. Gammack , Roger M. Shepherd
IPC分类号： G06F12/08 , G06F12/10 , G11C15/04 , G06F12/02
CPC分类号： G06F12/1063
摘要： A fully associative cache memory for virtual addressing comprises a data RAM (50), a first CAM cell array (51) for holding virtual page addresses which each require address translation to identify a physical page in a main memory, a second CAM cell array (52) holding line or word in page addresses which remain the same for virtual and physical addresses, a physical address memory (53) for holding physical page addresses for the main memory corresponding to virtual page addresses in said first array (51), said first array (51) being connected both to said physical address memory (52) to access said physical address memory in response to a hit output from said first CAM cell array and to control circuitry (57) coupled between said first and second arrays (51,52) and the data RAM (50) to access the data RAM (50) in response to hit outputs from both said first and second CAM cell arrays (51,52).
摘要翻译：用于虚拟寻址的完全关联高速缓冲存储器包括数据RAM（50），用于保持虚拟页地址的第一CAM单元阵列（51），每个都需要地址转换来标识主存储器中的物理页，第二CAM单元阵列 52）保持对于虚拟和物理地址保持相同的页面地址中的行或字，用于保存对应于所述第一阵列（51）中的虚拟页地址的主存储器的物理页地址的物理地址存储器（53），所述第一阵列（51）被连接到所述物理地址存储器（52），以响应于来自所述第一CAM单元阵列的命中输出而访问所述物理地址存储器，以及耦合在所述第一和第二阵列之间的控制电路（57） 52）和数据RAM（50），以响应于来自所述第一和第二CAM单元阵列（51,52）的命中输出来访问数据RAM（50）。

8. 发明授权

US5412368A Digital signal comparison circuitry 失效
标题翻译：数字信号比较电路
公开(公告)号：US5412368A
公开(公告)日：1995-05-02
申请号：US84418
申请日：1993-06-29
申请人： Richard J. Gammack , Catherine L. Barnaby , Anthony I. Stansfield
发明人： Richard J. Gammack , Catherine L. Barnaby , Anthony I. Stansfield
IPC分类号： G06F7/02 , G06F11/08 , H03M13/00
CPC分类号： H03M13/00 , G06F11/08 , G06F7/02
摘要： A method of comparing a first multibit digital signal with a second multibit digital signal wherein to increase speed of obtaining an output signal said method comprises inputting input signals for each of said first and second signals and forming a respective codeword for each input signal, each codeword being at least one bit longer than the respective input signal and formed by the same error correcting code for both signals to provide increased minimum Hamming distance for the respective codewords, comparing respective bit locations of the codewords to form a plurality of match indicating signals for respective bit locations thereby indicating any mismatch by a mismatch at at least two bit locations, supplying said match indicating signals in parallel to gating circuitry arranged to provide an output indicating a match or mismatch between said codewords, said output being provided with a time delay less than that required for a single bit mismatch. The invention also provides digital signal comparison circuitry.
摘要翻译：一种将第一多位数字信号与第二多位数字信号进行比较的方法，其中为了提高获得输出信号的速度，所述方法包括输入每个所述第一和第二信号的输入信号，并为每个输入信号形成相应的码字，每个码字比相应的输入信号长至少一位，并由两个信号相同的纠错码形成，以便为各个码字提供增加的最小汉明距离，比较码字的各个比特位置以形成多个匹配指示信号从而指示在至少两个位位置处的不匹配的任何失配，将并行提供所述匹配指示信号的门控电路设置成提供指示所述码字之间的匹配或不匹配的输出，所述输出提供的时间延迟小于这是单个位不匹配所需的。本发明还提供了数字信号比较电路。

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