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1. 发明授权

US08705615B1 System for generating controllable difference measurements in a video processor 失效
标题翻译：用于在视频处理器中产生可控差分测量的系统
公开(公告)号：US08705615B1
公开(公告)日：2014-04-22
申请号：US12778990
申请日：2010-05-12
申请人： Anthony Mark Jones
发明人： Anthony Mark Jones
IPC分类号： H04N7/12
CPC分类号： H04N7/50 , H04N5/145 , H04N7/26244 , H04N19/43 , H04N19/523 , H04N19/59
摘要： Disclosed are systems and methods used in motion estimation and in other systems. Embodiments of the invention include a built-in masking function that can be used in conjunction with either a difference measurement. A controllable mask bit may be set for each individual ai:bi comparison. In one embodiment, to include the particular location represented by the “i” value in the comparison, the mask bit is left unset; to ignore any location, the mask bit is set. If the mask bit is set, the comparison value is calculated as zero, i.e., there is no difference entered into the calculation, even if there is an actual difference in the two datasets.
摘要翻译：公开了用于运动估计和其他系统的系统和方法。本发明的实施例包括可以与差分测量一起使用的内置屏蔽功能。可以为每个单独的ai：bi比较设置可控制的掩码位。在一个实施例中，为了在比较中包括由“i”值表示的特定位置，屏蔽位未设置; 忽略任何位置，设置掩码位。如果设置了掩码位，则即使在两个数据集中存在实际差异，也将比较值计算为零，即计算中没有差异。

2. 发明授权

US07598918B2 Tubular endfire slot-mode antenna array with inter-element coupling and associated methods 有权
标题翻译：具有元件间耦合和相关方法的管状端火槽模式天线阵列
公开(公告)号：US07598918B2
公开(公告)日：2009-10-06
申请号：US12017183
申请日：2008-01-21
申请人： Timothy E. Durham , Griffin K. Gothard , Anthony Mark Jones , Jay Kralovec , Stephen R. Landers , Sean Ortiz , Chris Snyder , Ralph Trosa
发明人： Timothy E. Durham , Griffin K. Gothard , Anthony Mark Jones , Jay Kralovec , Stephen R. Landers , Sean Ortiz , Chris Snyder , Ralph Trosa
IPC分类号： H01Q13/10
CPC分类号： H01Q21/065 , H01Q1/38 , Y10T29/49016
摘要： The tubular slot-mode antenna includes an array of slot antenna units carried by a tubular substrate, e.g. a cylindrical substrate, and each slot antenna unit having a pair of patch antenna elements arranged in laterally spaced apart relation about at least one central feed position. Adjacent patch antenna elements of adjacent slot-mode antenna units have respective spaced apart edge portions with predetermined shapes and relative positioning to provide increased capacitive coupling therebetween. The array of slot-mode antenna units may define a plurality of ring-shaped slots coaxial with an axis of the tubular substrate, and a feed arrangement may be coupled thereto to operate the array of slot-mode antenna units in an endfire mode.
摘要翻译：管状槽模式天线包括由管状衬底承载的缝隙天线单元的阵列，例如，圆柱形基板，每个缝隙天线单元具有一对沿着至少一个中央进给位置以横向隔开的关系布置的一对贴片天线元件。相邻槽模式天线单元的相邻贴片天线元件具有预定形状和相对定位的相应间隔开的边缘部分，以在它们之间提供增加的电容耦合。槽模式天线单元的阵列可以限定与管状衬底的轴线同轴的多个环形槽，并且馈送装置可以耦合到其上以在端点模式中操作槽模式天线单元阵列。

3. 发明授权

US07577874B2 Interactive debug system for multiprocessor array 有权
标题翻译：多处理器阵列的交互式调试系统
公开(公告)号：US07577874B2
公开(公告)日：2009-08-18
申请号：US11673986
申请日：2007-02-12
申请人： Anthony Mark Jones , Paul M. Wasson , Edmund H. White
发明人： Anthony Mark Jones , Paul M. Wasson , Edmund H. White
IPC分类号： G06F11/00
CPC分类号： G06F11/362 , G06F17/5045
摘要： A debug network on a multiprocessor array includes communication channels, a master controller, and one or more individual debug units in communication with one or more of the processors. The master controller solicits information from the debug units by sending messages along the communication channels. The debug units can control some aspects of the processors, and can simply report on other aspects. By using commands to invoke processor action, then accessing the result, interactive debugging of a multiprocessor array is possible.
摘要翻译：多处理器阵列上的调试网络包括与一个或多个处理器通信的通信信道，主控制器和一个或多个单独的调试单元。主控制器通过沿着通信通道发送消息来从调试单元请求信息。调试单元可以控制处理器的某些方面，并且可以简单地报告其他方面。通过使用命令调用处理器操作，然后访问结果，可以进行多处理器阵列的交互式调试。

4. 发明申请

US20080235490A1 SYSTEM FOR CONFIGURING A PROCESSOR ARRAY 审中-公开
标题翻译：用于配置处理器阵列的系统
公开(公告)号：US20080235490A1
公开(公告)日：2008-09-25
申请号：US12018045
申请日：2008-01-22
申请人： Anthony Mark Jones , Paul M. Wasson , Michael R. Butts
发明人： Anthony Mark Jones , Paul M. Wasson , Michael R. Butts
IPC分类号： G06F15/80
CPC分类号： G06F15/16
摘要： Embodiments of the invention are directed to a system for configuring a processor array using configuration chains streamed down communication channels.
摘要翻译：本发明的实施例涉及一种使用流式传输通信信道的配置链配置处理器阵列的系统。

5. 发明授权

US07139985B2 Development system for an integrated circuit having standardized hardware objects 有权
标题翻译：具有标准化硬件对象的集成电路开发系统
公开(公告)号：US07139985B2
公开(公告)日：2006-11-21
申请号：US10871311
申请日：2004-06-18
申请人： Anthony Mark Jones
发明人： Anthony Mark Jones
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Embodiments of the invention include a system for an integrated circuit development. Elements of the development system include hardware and software objects. These objects can be instanced, ordered, parameterized, and connected in a software environment to implement different functions. Once in software, the description defines the topology and the properties of a set of objects and hence the overall function. These objects are hierarchically composed from a set of primitive objects. By using a piece of hardware that can model any primitive object set as pre-established encapsulated hardware objects, the topology and properties define a piece of hardware that can perform the desired, implemented, functions. Using embodiments of the invention, circuit designers can design hardware systems with little or no knowledge of hardware or hardware design, requiring only a high-level software description.
摘要翻译：本发明的实施例包括用于集成电路开发的系统。开发系统的元素包括硬件和软件对象。这些对象可以在软件环境中实例化，排序，参数化和连接，以实现不同的功能。一旦在软件中，描述定义了一组对象的拓扑和属性，从而定义了整体功能。这些对象由一组原始对象分层组成。通过使用可以将任何原始对象集合建模为预先建立的封装硬件对象的硬件，拓扑和属性定义了可执行所需实现的功能的一块硬件。利用本发明的实施例，电路设计者可以很少或不知道硬件或硬件设计的硬件系统，只需要高级软件描述。

6. 发明授权

US07111261B2 Method of determining library parameters using timing surface planarity 失效
标题翻译：使用定时表面平面度确定库参数的方法
公开(公告)号：US07111261B2
公开(公告)日：2006-09-19
申请号：US10715716
申请日：2003-11-18
申请人： Anthony Mark Jones
发明人： Anthony Mark Jones
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention relates to a characterizing a timing delay curve of a circuit component, said timing delay curve having a first region and a second region. The method includes determining a first delay equation representing the first region of the delay curve, determining a second delay equation representing the second region of the delay curve, and determining a corner capacitance representing a transition point from the first region to the second region.
摘要翻译：本发明涉及表征电路部件的定时延迟曲线，所述定时延迟曲线具有第一区域和第二区域。该方法包括确定表示延迟曲线的第一区域的第一延迟方程，确定表示延迟曲线的第二区域的第二延迟方程，以及确定代表从第一区域到第二区域的转变点的角电容。

7. 发明授权

US5768629A Token-based adaptive video processing arrangement 失效
标题翻译：基于令牌的自适应视频处理布置
公开(公告)号：US5768629A
公开(公告)日：1998-06-16
申请号：US479910
申请日：1995-06-07
申请人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
发明人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.
摘要翻译：一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等。

8. 发明申请

US20120230434A1 SYSTEM FOR COMPRESSING AND DE-COMPRESSING DATA USED IN VIDEO PROCESSING 有权
标题翻译：用于压缩和压缩在视频处理中使用的数据的系统
公开(公告)号：US20120230434A1
公开(公告)日：2012-09-13
申请号：US13474990
申请日：2012-05-18
申请人： Anthony Mark Jones
发明人： Anthony Mark Jones
IPC分类号： H04N7/26
CPC分类号： H04N19/51 , H03M7/4012 , H04N19/43 , H04N19/523 , H04N19/82
摘要： Disclosed are systems and methods used in motion estimation and particularly for data compression. Embodiments of the invention may store and operate on an n-bit value in less than n bits. In one embodiment, if the multi-bit value is less than a threshold, then the multi-bit value is stored in the reduced-bit storage directly, with no loss of precision. If the multi-bit value is greater than the threshold, then the Most Significant Bits (MSBs) of the multi-bit value are shifted onto the reduced-bit storage, and a compression flag set. To decompress, if the compression flag was not set, the bits stored in the reduced-bit storage are merely copied back into the multi-bit value directly. If the compression flag was set, then the bits stored in the reduced-bit storage are shifted (left) by the same amount they were shifted (right) during compression, and an error-minimizing value is added.
摘要翻译：公开了用于运动估计，特别是用于数据压缩的系统和方法。本发明的实施例可以在小于n位的n位值上存储和操作。在一个实施例中，如果多比特值小于阈值，则多比特值直接存储在缩减比特存储中，而不会损失精度。如果多比特值大于阈值，则多比特值的最高有效比特（MSB）被移位到缩减比特存储上，并且设置压缩标志。为了解压缩，如果未设置压缩标志，则存储在缩减比特存储器中的比特直接被复制回多比特值。如果设置了压缩标志，则在压缩期间，存储在减位存储器中的位移动（左）移位（右）相同的量，并且添加错误最小化值。

9. 发明授权

US08218644B1 System for compressing and de-compressing data used in video processing 有权
标题翻译：用于压缩和解压缩视频处理中使用的数据的系统
公开(公告)号：US08218644B1
公开(公告)日：2012-07-10
申请号：US12778996
申请日：2010-05-12
申请人： Anthony Mark Jones
发明人： Anthony Mark Jones
IPC分类号： H04N11/02 , H03M7/00 , H03M7/34 , H03M5/00
CPC分类号： H04N19/51 , H03M7/4012 , H04N19/43 , H04N19/523 , H04N19/82
摘要： Disclosed are systems and methods used in motion estimation and particularly for data compression. Embodiments of the invention may store and operate on an n-bit value in less than n bits. In one embodiment, if the multi-bit value is less than a threshold, then the multi-bit value is stored in the reduced-bit storage directly, with no loss of precision. If the multi-bit value is greater than the threshold, then the Most Significant Bits (MSBs) of the multi-bit value are shifted into the reduced-bit storage, and a compression flag set. To decompress, if the compression flag was not set, the bits stored in the reduced-bit storage are merely copied back into the multi-bit value directly. If the compression flag was set, then the bits stored in the reduced-bit storage are shifted (left) by the same amount they were shifted (right) during compression, and an error-minimizing value is added.
摘要翻译：公开了用于运动估计，特别是用于数据压缩的系统和方法。本发明的实施例可以在小于n位的n位值上存储和操作。在一个实施例中，如果多比特值小于阈值，则多比特值直接存储在缩减比特存储中，而不会损失精度。如果多比特值大于阈值，则多比特值的最高有效比特（MSB）被移位到缩减比特存储中，并且设置压缩标志。为了解压缩，如果未设置压缩标志，则存储在缩减比特存储器中的比特直接被复制回多比特值。如果设置了压缩标志，则在压缩期间，存储在减位存储器中的位移动（左）移位（右）相同的量，并且添加错误最小化值。

10. 发明授权

US07945803B2 Clock generation for multiple clock domains 有权
标题翻译：多个时钟域的时钟生成
公开(公告)号：US07945803B2
公开(公告)日：2011-05-17
申请号：US11460231
申请日：2006-07-26
申请人： Anthony Mark Jones , Kevin M. Koschoreck
发明人： Anthony Mark Jones , Kevin M. Koschoreck
IPC分类号： G06F1/04
CPC分类号： H04L7/02 , G06F1/04 , G06F1/10 , G06F1/12 , H04L7/0008
摘要： This disclosure relates to generating clock signals that drive data passing circuitry for various clock domains. Each individual clock domain can adjust its operating frequency from one generated by a central clock to an appropriate frequency. By using embodiments of the invention, clock crossing circuitry between domains need not run at the highest clock frequency of the entire circuit, but rather the clock crossing circuitry need only operate at the highest frequency of the two domains sharing data.
摘要翻译：本公开涉及产生驱动各种时钟域的数据传送电路的时钟信号。每个单独的时钟域可以将其工作频率从由中央时钟生成的频率调整到适当的频率。通过使用本发明的实施例，域之间的时钟交叉电路不需要在整个电路的最高时钟频率下运行，而是时钟交叉电路仅需要在共享数据的两个域的最高频率下操作。

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