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21. 发明授权

US11262018B2 Storage rack 有权
公开(公告)号：US11262018B2
公开(公告)日：2022-03-01
申请号：US15962000
申请日：2018-04-25
申请人： Anil Gupta
发明人： Anil Gupta
IPC分类号： F16M11/04 , A47B96/02 , A47B45/00 , A47F5/08 , F16M11/18 , F16M13/02 , A47B96/14 , A47B57/08 , B65G1/02
摘要： An apparatus that at least stores objects of varying sizes, said apparatus includes adjustable trays configured to support the objects at bottom surfaces thereof and stationary or mobile panels for mounting the trays in a generally vertical plane. The panels can be provided as pegboard types or as slatwall types. The adjustable trays include a pair of brackets connected with a guide. A mounting portion of each bracket is adapted to mate with the corresponding panel type.

22. 外观设计

USD895401S1 Pegboard adapter 有权
公开(公告)号：USD895401S1
公开(公告)日：2020-09-08
申请号：US29637959
申请日：2018-02-23
申请人： Anil Gupta
设计人： Anil Gupta

23. 发明授权

US08503396B2 Network apparatus enabling roaming across subnets 有权
标题翻译：允许跨子网漫游的网络设备
公开(公告)号：US08503396B2
公开(公告)日：2013-08-06
申请号：US13198084
申请日：2011-08-04
申请人： Richard H. Blanchette , Martin Bouchard , Anil Gupta , Yannick Koehler , Gilbert Moineau , Fréderic D. Mouveaux , Roger D. Sands , Pierre Trudeau
发明人： Richard H. Blanchette , Martin Bouchard , Anil Gupta , Yannick Koehler , Gilbert Moineau , Fréderic D. Mouveaux , Roger D. Sands , Pierre Trudeau
IPC分类号： H04W4/00 , H04H20/71 , H04L12/66 , H04L12/28 , H04B1/16
CPC分类号： H04W8/02 , H04L45/66 , H04W40/36 , H04W80/02 , H04W80/04
摘要： To enable a network apparatus to detect L3 roaming users and to take appropriate forwarding actions, L3 knowledge is introduced inside an L2 bridge forwarding table in the network apparatus. As a client moves from a subnet associated with a first network element to a subnet associated with the network apparatus, a determination is made regarding whether the client is roaming by evaluating a source IP address within a L3 packet header within a first frame received at the network apparatus. If, as a result of the evaluating step, it is determined that the client is roaming, the L2 bridge forwarding table is configured to include a source MAC address of the client together with information identifying a destination interface for use in directing client data traffic back towards the subnet associated with the first network element.
摘要翻译：为了使网络设备能够检测L3漫游用户并采取适当的转发动作，在网络设备的L2桥转发表中引入L3知识。当客户端从与第一网元相关联的子网移动到与网络装置相关联的子网时，通过评估在第一帧中接收到的第一帧内的L3分组报头内的源IP地址来确定客户端是否正在漫游网络设备如果作为评估步骤的结果，确定客户端正在漫游，则L2桥转发表被配置为包括客户端的源MAC地址以及标识目的地接口的信息，以用于将客户端数据业务引导回来朝向与第一网络元件相关联的子网。

24. 发明授权

US08125834B2 Device and method for controlling solid-state memory system 失效
标题翻译：用于控制固态存储器系统的装置和方法
公开(公告)号：US08125834B2
公开(公告)日：2012-02-28
申请号：US12619581
申请日：2009-11-16
申请人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
发明人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
IPC分类号： G11C16/04 , G06F13/00
CPC分类号： G11C5/04 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G06F12/0676 , G06F13/1668 , G06F13/4243 , G11C5/00 , G11C5/066 , G11C8/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A memory system includes an array of solid state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon. A reserved predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.
摘要翻译：存储器系统包括固态存储器件的阵列，其经由具有极少线的器件总线与控制器模块通信并处于控制器模块的控制之下。这形成了集成电路大容量存储系统，其被设想来替代大容量存储系统，例如计算机系统中的磁盘驱动器存储器。命令，地址和数据信息被串行化为组件字符串，并在控制器模块和存储器件阵列之间传输之前被多路复用。串行化信息伴随着一个控制信号，以帮助整理复用的组件。阵列中的每个存储器件都安装在多位安装上，并通过阵列安装分配阵列地址。通过在设备总线上广播的适当地址来选择存储器件，而不需要通常的专用选择信号。使用保留阵列特定安装多位配置来无条件地选择安装在其上的装置。通过设备总线广播的保留的预定义地址取消选择所有先前选择的存储设备。读取性能通过读取流技术得到增强，其中当当前块的数据被序列化并从存储器子系统设备移出到控制器模块时，控制器模块还设置下一个数据块开始的地址寻址内存系统。

25. 发明申请

US20110258141A1 METHOD FOR CREATING AND DELIVERING CUSTOMIZED COMPLIANCE INFORMATION 有权
公开(公告)号：US20110258141A1
公开(公告)日：2011-10-20
申请号：US13169692
申请日：2011-06-27
申请人： Jeffrey B. Levering , Alex Magary , Craig LeClair , Larry Kunz , Anil Gupta , Brigitte Tuller , Garett Wiley , Patricia Rosch
发明人： Jeffrey B. Levering , Alex Magary , Craig LeClair , Larry Kunz , Anil Gupta , Brigitte Tuller , Garett Wiley , Patricia Rosch
IPC分类号： G06Q40/00
CPC分类号： G06Q40/04 , G06Q30/00 , G06Q30/018 , G06Q40/00 , G06Q40/06 , G06Q40/12
摘要： A method and system to create personalized investor information packages, based on investor information, to be delivered to the investor to satisfy both compliance regulations and investor preferences. The method and system may deliver information in a paper or electronic format.

26. 发明授权

US07870046B2 System, apparatus and method for standardized financial reporting 有权
标题翻译：标准化财务报告制度，设备和方法
公开(公告)号：US07870046B2
公开(公告)日：2011-01-11
申请号：US10794539
申请日：2004-03-04
申请人： Anil Gupta
发明人： Anil Gupta
IPC分类号： G06Q40/00
CPC分类号： G06Q40/00 , G06Q40/10 , G06Q40/12
摘要： Standardized financial reports are automatically generated from company financial reports using a taxonomy library that maps company-specific terms to corresponding standard terms. Line items in the standardized financial reports include standardized terms derived from company-specific terms in the company financial report as well as corresponding financial information obtained from the company financial report. The financial information in the standardized financial report may be highlighted to indicate its source, and may also be cross-referenced back to its source location in the company financial report so that the information can be verified.
摘要翻译：标准化财务报告是从公司财务报告中自动生成的，该分析法库将公司特定条款映射到相应的标准条款。标准化财务报告中的订单项包括公司财务报告中公司特定条款的标准化条款以及从公司财务报告获得的相应财务信息。标准化财务报告中的财务信息可能会突出显示来源，并可能会在公司财务报告中与其来源位置进行交叉引用，以便可以验证信息。

27. 发明申请

US20100064098A1 Device and Method for Controlling Solid-State Memory System 失效
标题翻译：用于控制固态存储器系统的装置和方法
公开(公告)号：US20100064098A1
公开(公告)日：2010-03-11
申请号：US12619581
申请日：2009-11-16
申请人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
发明人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C5/04 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G06F12/0676 , G06F13/1668 , G06F13/4243 , G11C5/00 , G11C5/066 , G11C8/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A memory system includes an array of solid state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon. A reserved predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.
摘要翻译：存储器系统包括固态存储器件的阵列，其经由具有极少线的器件总线与控制器模块通信并处于控制器模块的控制之下。这形成了集成电路大容量存储系统，其被设想来替代大容量存储系统，例如计算机系统中的磁盘驱动器存储器。命令，地址和数据信息被串行化为组件字符串，并在控制器模块和存储器件阵列之间传输之前被多路复用。串行化信息伴随着一个控制信号，以帮助整理复用的组件。阵列中的每个存储器件都安装在多位安装上，并通过阵列安装分配阵列地址。通过在设备总线上广播的适当地址来选择存储器件，而不需要通常的专用选择信号。使用保留阵列特定安装多位配置来无条件地选择安装在其上的装置。通过设备总线广播的保留的预定义地址取消选择所有先前选择的存储设备。读取性能通过读取流技术得到增强，其中当当前块的数据被序列化并从存储器子系统设备移出到控制器模块时，控制器模块还设置下一个数据块开始的地址寻址内存系统。

28. 发明申请

US20070014140A1 Nonvolatile semiconductor memory apparatus 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US20070014140A1
公开(公告)日：2007-01-18
申请号：US11182374
申请日：2005-07-15
申请人： Nicola Telecco , Vijay Adusumilli , Anil Gupta , Edward Hui , Steven Schumann
发明人： Nicola Telecco , Vijay Adusumilli , Anil Gupta , Edward Hui , Steven Schumann
IPC分类号： G11C5/06
CPC分类号： G11C7/10 , H01L2224/05553 , H01L2224/48137 , H01L2224/49175
摘要： A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The memory circuit is fabricated on a second integrated circuit chip and includes a column decoder, a row decoder, a control register, and a data register. A memory-controller interface area includes a first plurality of die bond pads on the first integrated circuit chip and a second plurality of die bond pads on the second integrated circuit chip such that the first and second integrated circuit chips may be die-bonded together. A single controller circuit may interface with a plurality of memory circuits, thus further reducing overall costs as each memory circuit does not require a dedicated controller circuit.
摘要翻译：非易失性存储装置包括单独的控制器电路和存储器电路。控制器电路制造在第一集成电路芯片上。控制器电路包括多个电荷泵电路，系统接口逻辑电路，存储器控制逻辑电路和一个或多个模拟电路。存储器电路制造在第二集成电路芯片上，并且包括列解码器，行解码器，控制寄存器和数据寄存器。存储器控制器接口区域包括第一集成电路芯片上的第一多个管芯接合焊盘和第二集成电路芯片上的第二多个管芯接合焊盘，使得第一和第二集成电路芯片可以芯片结合在一起。单个控制器电路可以与多个存储器电路接口，从而进一步降低总体成本，因为每个存储器电路不需要专用控制器电路。

29. 发明授权

US06493773B1 Data validity measure for efficient implementation of first-in-first-out memories for multi-processor systems 有权
标题翻译：有效实施多处理器系统先进先出存储器的数据有效性测量
公开(公告)号：US06493773B1
公开(公告)日：2002-12-10
申请号：US09713998
申请日：2000-11-15
申请人： Thomas Daniel , Anil Gupta
发明人： Thomas Daniel , Anil Gupta
IPC分类号： G06F1314
CPC分类号： G06F15/167
摘要： To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.
摘要翻译：为了减少跨处理器系统中的系统总线的FIFO访问周期，在多处理器系统中，两个处理器通过FIFO通过系统总线进行通信，则提供两个独立的FIFO描述符。第一描述符由位于板上的处理器由FIFO维护，第二描述符由通过总线与FIFO通信的板外处理器来维护。当一个处理器执行FIFO操作时，处理器通过总线上的存储器访问来更新其他处理器的描述符。此外，一个模块向另一个模块传递信用以指示后者具有连续执行多个FIFO操作的许可。在一个实施例中，使用特殊的非有效数据值来指示空的FIFO位置。

30. 发明授权

US6112271A Multiconfiguration backplane 失效
标题翻译：多组态背板
公开(公告)号：US6112271A
公开(公告)日：2000-08-29
申请号：US79040
申请日：1998-05-14
申请人： Mark Lanus , Anil Gupta , James Langdal
发明人： Mark Lanus , Anil Gupta , James Langdal
IPC分类号： G06F11/20 , G06F13/00 , G06F13/40
CPC分类号： G06F13/409
摘要： A multiconfiguration backplane (100) can be configured in four different configurations: dual, extended, active/standby and active/active. The multiconfiguration backplane (100) has a first COMPACT PCI bus (110) with a first system processor slot (112), a first bridge slot (114), and a first set of one or more input/output slots (116). The multiconfiguration backplane has a second COMPACT PCI bus (120) with a second system processor slot (122), a second bridge slot (124), and a second set of one or more input/output slots (126). A first cross connection (130) is between the first system processor slot (112) and the second bridge slot (124), and a second cross connection (140) is provided between the second system processor slot (122) and the first bridge slot (114). Preferably, the first cross connection is a first local PCI bus and the second cross connection is a second local PCI bus.
摘要翻译：多配置背板（100）可以配置为四种不同的配置：双，扩展，主动/待机和主动/主动。多配置背板（100）具有第一COMPACT PCI总线（110），其具有第一系统处理器插槽（112），第一桥插槽（114）和第一组一个或多个输入/输出插槽（116）。多配置背板具有第二COMPACT PCI总线（120），其具有第二系统处理器插槽（122），第二桥插槽（124）和第二组一个或多个输入/输出插槽（126）。第一交叉连接（130）在第一系统处理器插槽（112）和第二桥插槽（124）之间，并且第二交叉连接（140）设置在第二系统处理器插槽（122）和第一桥插槽（114）。优选地，第一交叉连接是第一本地PCI总线，第二交叉连接是第二本地PCI总线。

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