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1. 发明申请

US20070014140A1 Nonvolatile semiconductor memory apparatus 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US20070014140A1
公开(公告)日：2007-01-18
申请号：US11182374
申请日：2005-07-15
申请人： Nicola Telecco , Vijay Adusumilli , Anil Gupta , Edward Hui , Steven Schumann
发明人： Nicola Telecco , Vijay Adusumilli , Anil Gupta , Edward Hui , Steven Schumann
IPC分类号： G11C5/06
CPC分类号： G11C7/10 , H01L2224/05553 , H01L2224/48137 , H01L2224/49175
摘要： A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The memory circuit is fabricated on a second integrated circuit chip and includes a column decoder, a row decoder, a control register, and a data register. A memory-controller interface area includes a first plurality of die bond pads on the first integrated circuit chip and a second plurality of die bond pads on the second integrated circuit chip such that the first and second integrated circuit chips may be die-bonded together. A single controller circuit may interface with a plurality of memory circuits, thus further reducing overall costs as each memory circuit does not require a dedicated controller circuit.
摘要翻译：非易失性存储装置包括单独的控制器电路和存储器电路。控制器电路制造在第一集成电路芯片上。控制器电路包括多个电荷泵电路，系统接口逻辑电路，存储器控制逻辑电路和一个或多个模拟电路。存储器电路制造在第二集成电路芯片上，并且包括列解码器，行解码器，控制寄存器和数据寄存器。存储器控制器接口区域包括第一集成电路芯片上的第一多个管芯接合焊盘和第二集成电路芯片上的第二多个管芯接合焊盘，使得第一和第二集成电路芯片可以芯片结合在一起。单个控制器电路可以与多个存储器电路接口，从而进一步降低总体成本，因为每个存储器电路不需要专用控制器电路。

2. 发明授权

US07317630B2 Nonvolatile semiconductor memory apparatus 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US07317630B2
公开(公告)日：2008-01-08
申请号：US11182374
申请日：2005-07-15
申请人： Nicola Telecco , Vijay P. Adusumilli , Anil Gupta , Edward Hui , Steven J. Schumann
发明人： Nicola Telecco , Vijay P. Adusumilli , Anil Gupta , Edward Hui , Steven J. Schumann
IPC分类号： G11C5/06
CPC分类号： G11C7/10 , H01L2224/05553 , H01L2224/48137 , H01L2224/49175
摘要： A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The memory circuit is fabricated on a second integrated circuit chip and includes a column decoder, a row decoder, a control register, and a data register. A memory-controller interface area includes a first plurality of die bond pads on the first integrated circuit chip and a second plurality of die bond pads on the second integrated circuit chip such that the first and second integrated circuit chips may be die-bonded together. A single controller circuit may interface with a plurality of memory circuits, thus further reducing overall costs as each memory circuit does not require a dedicated controller circuit.
摘要翻译：非易失性存储装置包括单独的控制器电路和存储器电路。控制器电路制造在第一集成电路芯片上。控制器电路包括多个电荷泵电路，系统接口逻辑电路，存储器控制逻辑电路和一个或多个模拟电路。存储器电路制造在第二集成电路芯片上，并且包括列解码器，行解码器，控制寄存器和数据寄存器。存储器控制器接口区域包括第一集成电路芯片上的第一多个管芯接合焊盘和第二集成电路芯片上的第二多个管芯接合焊盘，使得第一和第二集成电路芯片可以芯片结合在一起。单个控制器电路可以与多个存储器电路接口，从而进一步降低总体成本，因为每个存储器电路不需要专用控制器电路。

3. 发明申请

US20190331288A1 STORAGE RACK 审中-公开
公开(公告)号：US20190331288A1
公开(公告)日：2019-10-31
申请号：US15962000
申请日：2018-04-25
申请人： Anil Gupta
发明人： Anil Gupta
IPC分类号： F16M11/04 , F16M11/18
摘要： An apparatus that at least stores objects of varying sizes, said apparatus includes adjustable trays configured to support the objects at bottom surfaces thereof and stationary or mobile panels for mounting the trays in a generally vertical plane. The panels can be provided as pegboard types or as slatwall types. The adjustable trays include a pair of brackets connected with a guide. A mounting portion of each bracket is adapted to mate with the corresponding panel type.

4. 发明申请

US20130297987A1 Method and Apparatus for Reading NAND Flash Memory 有权
标题翻译：读取NAND闪存的方法和装置
公开(公告)号：US20130297987A1
公开(公告)日：2013-11-07
申请号：US13464535
申请日：2012-05-04
申请人： Anil Gupta , Oron Michael , Robin John Jigour
发明人： Anil Gupta , Oron Michael , Robin John Jigour
IPC分类号： G11C29/00 , G06F11/16
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： A page buffer for a NAND memory array has a data register and a cache register that are suitably organized and operated to eliminate gaps and discontinuities in the output data during a continuous page read. The cache register may be organized in two portions, and the page data in the cache may be output from the cache portions in alternation. ECC delay may be eliminated from the output by performing the ECC computation on one cache portion while the other is being output. The data register may also be organized in two portions corresponding to the cache portions, so that data may be transferred to one cache portion while the other is being output. In a variation, the continuous page read may be done without ECC.
摘要翻译：用于NAND存储器阵列的页缓冲器具有适当地组织和操作的数据寄存器和高速缓存寄存器，以在连续页读取期间消除输出数据中的间隙和不连续性。高速缓存寄存器可以以两部分组织，并且高速缓存中的页面数据可以从高速缓存部分交替地输出。可以通过在一个高速缓存部分执行ECC计算而另一个缓存部分被输出来从输出消除ECC延迟。数据寄存器也可以被组织在与高速缓存部分对应的两部分中，从而数据可以被传送到一个高速缓存部分而另一个被输出。在一个变型中，连续页面读取可以在不进行ECC的情况下完成。

5. 发明申请

US20130279391A1 TRANSMISSION IN A NETWORK WITH ACTIVE AND SLEEPING CLIENTS 有权
标题翻译：在有活动和睡眠客户的网络中传输
公开(公告)号：US20130279391A1
公开(公告)日：2013-10-24
申请号：US13453664
申请日：2012-04-23
申请人： Anil Gupta , Sung-Ju Lee
发明人： Anil Gupta , Sung-Ju Lee
IPC分类号： H04H20/71
CPC分类号： H04H20/423 , H04L12/189 , H04L47/14 , H04L47/15 , H04L65/4076 , H04N21/6405 , H04W4/06 , H04W52/0216 , H04W52/0219 , H04W72/005 , H04W76/28 , H04W76/40 , Y02D70/142
摘要： Methods, devices, and machine readable media are provided for transmission in a network with active and sleeping clients. Some examples can include transmitting a first multicast stream of data in response to an active wireless client being associated with the wireless network device at a particular time. The method can include transmitting a second multicast stream of the data after the first multicast stream in response to a sleeping wireless client being associated with the wireless network device at the particular time and in response to a delivery traffic indication message count expiring. The first and/or second multicast streams of the data can be retransmitted a number of times (e.g., at different data rates). An active/sleep status can be maintained for the wireless clients. A unicast stream can be transmitted when the number of clients does not exceed a threshold.
摘要翻译：提供方法，设备和机器可读介质用于在具有主动和睡眠客户端的网络中进行传输。一些示例可以包括响应于在特定时间与无线网络设备相关联的活动无线客户端来发送数据的第一多播流。所述方法可以包括在所述特定时间响应于与所述无线网络设备相关联的睡眠无线客户端以及响应于传送通信量指示消息计数到期而在所述第一多播流之后发送所述数据的第二多播流。可以多次重复数据的第一和/或第二多播流（例如，以不同的数据速率）。可以为无线客户端维护活动/睡眠状态。当客户端的数量不超过阈值时，可以传输单播流。

6. 发明授权

US08400866B2 Voltage boosting in MRAM current drivers 有权
标题翻译： MRAM电流驱动器的升压电压
公开(公告)号：US08400866B2
公开(公告)日：2013-03-19
申请号：US12852335
申请日：2010-08-06
申请人： Krishnakumar Mani , Anil Gupta
发明人： Krishnakumar Mani , Anil Gupta
IPC分类号： G11C8/00
CPC分类号： G11C11/16 , G11C5/145 , G11C8/08
摘要： A current driving mechanism for a magnetic memory device, comprising: a) a current driver circuit; and b) a current decoding block coupled to the current driver circuit, wherein the current decoding block comprises a transistor (M18) to control driver currents from the current driver circuit, and wherein the transistor (M18) has a smaller form factor then otherwise possible by virtue of maintaining a gate thereof at a negative voltage.
摘要翻译：一种用于磁存储器件的电流驱动机构，包括：a）电流驱动电路; 以及b）耦合到当前驱动器电路的当前解码块，其中当前解码块包括用于控制来自当前驱动器电路的驱动器电流的晶体管（M18），并且其中晶体管（M18）具有较小的形状因数，否则可能由于其栅极保持在负电压。

7. 发明授权

US07688643B2 Device and method for controlling solid-state memory system 失效
标题翻译：用于控制固态存储器系统的装置和方法
公开(公告)号：US07688643B2
公开(公告)日：2010-03-30
申请号：US10809061
申请日：2004-03-24
申请人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
发明人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
IPC分类号： G11C16/04 , G06F13/00
CPC分类号： G11C5/04 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G06F12/0676 , G06F13/1668 , G06F13/4243 , G11C5/00 , G11C5/066 , G11C8/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A memory system includes an array of solidstate memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon. A reserved predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.
摘要翻译：存储器系统包括固态存储器件的阵列，其经由具有极少行的器件总线与控制器模块通信并处于控制器模块的控制之下。这形成了集成电路大容量存储系统，其被设想来替代大容量存储系统，例如计算机系统中的磁盘驱动器存储器。命令，地址和数据信息被串行化为组件字符串，并在控制器模块和存储器件阵列之间传输之前被多路复用。串行化信息伴随着一个控制信号，以帮助整理复用的组件。阵列中的每个存储器件都安装在多位安装上，并通过阵列安装分配阵列地址。通过在设备总线上广播的适当地址来选择存储器件，而不需要通常的专用选择信号。使用保留阵列特定安装多位配置来无条件地选择安装在其上的装置。通过设备总线广播的保留的预定义地址取消选择所有先前选择的存储设备。读取性能通过读取流技术得到增强，其中当当前块的数据被序列化并从存储器子系统设备移出到控制器模块时，控制器模块还设置下一个数据块开始的地址寻址内存系统。

8. 发明申请

US20080195516A1 Method for creating and delivering customized compliance information 审中-公开
标题翻译：创建和提供定制化合规信息的方法
公开(公告)号：US20080195516A1
公开(公告)日：2008-08-14
申请号：US12011588
申请日：2008-01-28
申请人： Jeffrey B. Levering , Alex Magary , Craig LeClair , Larry Kunz , Anil Gupta , Brigitte Tuller , Garett Wiley
发明人： Jeffrey B. Levering , Alex Magary , Craig LeClair , Larry Kunz , Anil Gupta , Brigitte Tuller , Garett Wiley
IPC分类号： G06Q40/00
CPC分类号： G06Q40/04 , G06Q30/00 , G06Q30/018 , G06Q40/00 , G06Q40/06 , G06Q40/12
摘要： A method and system to create personalized investor information packages, based on investor information, to be delivered to the investor to satisfy both compliance regulations and investor preferences. The method and system may deliver information in a paper or electronic format.
摘要翻译：一种基于投资者信息创建个性化投资者信息包的方法和系统，将交付给投资者以满足合规规定和投资者偏好。该方法和系统可以以纸或电子格式传送信息。

9. 发明申请

US20050125316A1 Method for creating and delivering customized compliance information 审中-公开
标题翻译：创建和提供定制化合规信息的方法
公开(公告)号：US20050125316A1
公开(公告)日：2005-06-09
申请号：US10877904
申请日：2004-06-25
申请人： Jeffrey Levering , Alex Magary , Craig LeClair , Larry Kunz , Anil Gupta , Brigitte Tuller , Garett Wiley
发明人： Jeffrey Levering , Alex Magary , Craig LeClair , Larry Kunz , Anil Gupta , Brigitte Tuller , Garett Wiley
IPC分类号： G06F20060101 , G06Q40/00 , G06F17/60
CPC分类号： G06Q40/04 , G06Q30/00 , G06Q30/018 , G06Q40/00 , G06Q40/06 , G06Q40/12
摘要： A method and system to create personalized investor information packages, based on investor information, to be delivered to the investor to satisfy both compliance regulations and investor preferences. The method and system may deliver information in a paper or electronic format.
摘要翻译：一种基于投资者信息创建个性化投资者信息包的方法和系统，将交付给投资者以满足合规规定和投资者偏好。该方法和系统可以以纸或电子格式传送信息。

10. 发明授权

US6161197A Method and system for controlling a bus with multiple system hosts 失效
标题翻译：用多台系统主机控制总线的方法和系统
公开(公告)号：US6161197A
公开(公告)日：2000-12-12
申请号：US079130
申请日：1998-05-14
申请人： Mark Lanus , Charles Christopher Hill , Anil Gupta
发明人： Mark Lanus , Charles Christopher Hill , Anil Gupta
IPC分类号： G06F13/14 , G06F11/20 , G06F15/177 , G06F11/16
CPC分类号： G06F11/2007 , G06F11/20 , G06F11/2023
摘要： In a method for swapping a system host board (150,160,170,180), when a failure is detected on a first system processor board (150), control of a first CompactPCI bus (110) is transferred from a first system processor board system host (154) to a first bridge board system host(164). In an active/standby configuration, control of a second CompactPCI bus (120) is transferred from a second bridge board system host (184) to a second system processor board system host (174), and control of the devices on the first CompactPCI bus (110) and second CompactPCI bus (120) is transferred from the first system processor (152) to the second system processor (172) without resetting any devices on the system.
摘要翻译：在用于交换系统主机板（150,160,170,180）的方法中，当在第一系统处理器板（150）上检测到故障时，从第一系统处理器板系统主机（154）传送第一CompactPCI总线（110）的控制，到第一桥板系统主机（164）。在主动/待机配置中，第二CompactPCI总线（120）的控制从第二桥接板系统主机（184）传送到第二系统处理器板系统主机（174），并且控制第一CompactPCI总线上的设备（110）和第二CompactPCI总线（120）从第一系统处理器（152）传送到第二系统处理器（172），而不重置系统上的任何设备。

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