专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US08518795B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08518795B2
公开(公告)日：2013-08-27
申请号：US13455633
申请日：2012-04-25
申请人： Jusuke Ogura , Hikaru Kokura , Hideyuki Kojima , Toru Anezaki , Hiroyuki Ogawa , Junichi Ariyoshi
发明人： Jusuke Ogura , Hikaru Kokura , Hideyuki Kojima , Toru Anezaki , Hiroyuki Ogawa , Junichi Ariyoshi
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L27/1052 , H01L27/11521
摘要： A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.
摘要翻译：制造半导体器件的方法包括在半导体衬底中形成限定有源区的隔离区，在半导体衬底上形成第一绝缘膜，形成第二绝缘膜，该第二绝缘膜具有与第一绝缘膜相同的蚀刻性能绝缘膜，通过使用基于碳氟化合物的蚀刻气体的干蚀刻从有源区域和隔离区域上的第一区域选择性地去除第二绝缘膜，通过在第一绝缘膜上暴露于第一绝缘膜上形成的残留膜含氧的气氛，通过湿式蚀刻从第一区域选择性地除去第一绝缘膜。

22. 发明授权

US08173514B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08173514B2
公开(公告)日：2012-05-08
申请号：US12369859
申请日：2009-02-12
申请人： Jusuke Ogura , Hikaru Kokura , Hideyuki Kojima , Toru Anezaki , Hiroyuki Ogawa , Junichi Ariyoshi
发明人： Jusuke Ogura , Hikaru Kokura , Hideyuki Kojima , Toru Anezaki , Hiroyuki Ogawa , Junichi Ariyoshi
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L27/1052 , H01L27/11521
摘要： A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.
摘要翻译：制造半导体器件的方法包括在半导体衬底中形成限定有源区的隔离区，在半导体衬底上形成第一绝缘膜，形成第二绝缘膜，该第二绝缘膜具有与第一绝缘膜相同的蚀刻性能绝缘膜，通过使用基于碳氟化合物的蚀刻气体的干蚀刻从有源区域和隔离区域上的第一区域选择性地去除第二绝缘膜，通过在第一绝缘膜上暴露于第一绝缘膜上形成的残留膜含氧的气氛，通过湿式蚀刻从第一区域选择性地除去第一绝缘膜。

23. 发明申请

US20120038051A1 BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME 有权
标题翻译：带硅胶的局部连接器和其制造方法
公开(公告)号：US20120038051A1
公开(公告)日：2012-02-16
申请号：US13281491
申请日：2011-10-26
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

24. 发明授权

US07786003B1 Buried silicide local interconnect with sidewall spacers and method for making the same 有权
标题翻译：埋入硅化物与侧壁间隔物的局部互连及其制造方法
公开(公告)号：US07786003B1
公开(公告)日：2010-08-31
申请号：US11136569
申请日：2005-05-25
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
IPC分类号： H01L21/4763
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

25. 发明申请

US20090176359A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090176359A1
公开(公告)日：2009-07-09
申请号：US12318580
申请日：2008-12-31
申请人： Jusuke Ogura
发明人： Jusuke Ogura
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11543
摘要： The semiconductor device comprises a silicon substrate 14 having a step formed in the surface which makes the surface in a flash memory cell region 10 lower than the surface in a peripheral circuit region 12; a device isolation region 20a formed in a trench 18 in the flash memory cell region 10; a device isolation region 20c formed in a trench 24 deeper than the trench 18 in the peripheral circuit region 12; a flash memory cell 46 including a floating gate 32 and a control gate 40 formed on the device region defined by the device isolation region 20a; and transistors 62, 66 formed on the device regions defined by the device isolation region 20c.
摘要翻译：半导体器件包括硅衬底14，其具有在表面中形成的台阶，其使闪存单元区域10中的表面比外围电路区域12中的表面低; 形成在闪存单元区域10中的沟槽18中的器件隔离区域20a; 形成在比外围电路区域12中的沟槽18更深的沟槽24中的器件隔离区域20c; 闪存单元46包括形成在由器件隔离区域20a限定的器件区域上的浮动栅极32和控制栅极40; 以及形成在由器件隔离区域20c限定的器件区域上的晶体管62,66。

26. 发明授权

US06809033B1 Innovative method of hard mask removal 有权
标题翻译：硬膜去除创新方法
公开(公告)号：US06809033B1
公开(公告)日：2004-10-26
申请号：US10045354
申请日：2001-11-07
申请人： Angela Hui , Jusuke Ogura
发明人： Angela Hui , Jusuke Ogura
IPC分类号： H01L21311
CPC分类号： H01L21/31116 , H01L21/32139
摘要： One aspect of the invention relates to a method of removing a hard mask from a surface, especially a silicon surface. The hard mask is removed by first applying a sacrificial coating and then plasma etching. The sacrificial material fills pattern gaps formed using the hard mask and protects insulators, such as oxides, within those pattern gaps. The sacrificial material is removed together with the hard mask by the plasma etching. The invention provides a process for removing hard masks from silicon layers without significantly damaging either the silicon layer or any exposed oxides and can be applied in a variety of integrated circuit device manufacturing processes, such as patterning the floating gate layer of a flash memory device.
摘要翻译：本发明的一个方面涉及从表面特别是硅表面去除硬掩模的方法。通过首先施加牺牲涂层，然后等离子体蚀刻来去除硬掩模。牺牲材料填充使用硬掩模形成的图案间隙，并在这些图案间隙内保护绝缘体，例如氧化物。通过等离子体蚀刻与牺牲材料一起去除牺牲材料。本发明提供了一种从硅层去除硬掩模的方法，而不会明显损害硅层或任何暴露的氧化物，并且可以应用于各种集成电路器件制造工艺中，例如对闪存器件的浮动栅极图案进行构图。

27. 发明授权

US08884375B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08884375B2
公开(公告)日：2014-11-11
申请号：US12561719
申请日：2009-09-17
申请人： Satoshi Nakai , Masato Suga , Jusuke Ogura
发明人： Satoshi Nakai , Masato Suga , Jusuke Ogura
IPC分类号： H01L29/76 , H01L21/336 , H01L21/8238 , H01L21/02 , H01L29/78 , H01L29/66
CPC分类号： H01L21/02225 , H01L21/8238 , H01L21/823807 , H01L29/665 , H01L29/7843
摘要： A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.
摘要翻译：所公开的半导体集成电路器件包括半导体衬底; 以及设置在半导体衬底上的多个半导体元件。半导体元件包括n沟道MOS晶体管和p沟道MOS晶体管。 n沟道MOS晶体管由拉伸应力膜覆盖，并且p沟道MOS晶体管被压缩应力膜覆盖。在半导体衬底的表面上设置整个表面被拉伸应力膜和压缩应力膜的组合覆盖的虚拟区域。

28. 发明授权

US07892969B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07892969B2
公开(公告)日：2011-02-22
申请号：US12333716
申请日：2008-12-12
申请人： Masanori Tsutsumi , Jusuke Ogura
发明人： Masanori Tsutsumi , Jusuke Ogura
IPC分类号： H01L21/4763
CPC分类号： H01L21/76804 , H01L21/31116 , H01L21/31144
摘要： A method of manufacturing a semiconductor device has forming a first nitride layer over a substrate, forming a first oxide layer on the first nitride layer, forming a second nitride layer on the first oxide layer, forming a photoresist layer over the second nitride layer, forming a opening in the photoresist layer, etching the second nitride layer using the photoresist layer as a mask such that the opening is reached to the first oxide layer, etching the first oxide layer using the second nitride layer as a mask such that the opening is reached to the first nitride layer, etching the first oxide layer such that bottom zone of the opening is increased in diameter, and etching the first nitride layer using the first oxide layer as a mask such that the opening is reached to the substrate thereby to form contact hole reaching to the substrate.
摘要翻译：一种制造半导体器件的方法，在衬底上形成第一氮化物层，在第一氮化物层上形成第一氧化物层，在第一氧化物层上形成第二氮化物层，在第二氮化物层上形成光致抗蚀剂层，形成光致抗蚀剂层中的开口，使用光致抗蚀剂层作为掩模蚀刻第二氮化物层，使得开口到达第一氧化物层，使用第二氮化物层作为掩模蚀刻第一氧化物层，使得达到开口蚀刻第一氧化物层，使得开口的底部区域的直径增加，并且使用第一氧化物层作为掩模蚀刻第一氮化物层，使得开口到达衬底，从而形成接触孔到达基板。

29. 发明申请

US20100001350A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20100001350A1
公开(公告)日：2010-01-07
申请号：US12561719
申请日：2009-09-17
申请人： Satoshi Nakai , Masato Suga , Jusuke Ogura
发明人： Satoshi Nakai , Masato Suga , Jusuke Ogura
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/302
CPC分类号： H01L21/02225 , H01L21/8238 , H01L21/823807 , H01L29/665 , H01L29/7843
摘要： A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.
摘要翻译：所公开的半导体集成电路器件包括半导体衬底; 以及设置在半导体衬底上的多个半导体元件。半导体元件包括n沟道MOS晶体管和p沟道MOS晶体管。 n沟道MOS晶体管由拉伸应力膜覆盖，并且p沟道MOS晶体管被压缩应力膜覆盖。在半导体衬底的表面上设置整个表面被拉伸应力膜和压缩应力膜的组合覆盖的虚拟区域。

30. 发明申请

US20060220144A1 Semiconductor device and its manufacture method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060220144A1
公开(公告)日：2006-10-05
申请号：US11220628
申请日：2005-09-08
申请人： Toru Anezaki , Jusuke Ogura , Taiji Ema
发明人： Toru Anezaki , Jusuke Ogura , Taiji Ema
IPC分类号： H01L29/76
CPC分类号： H01L21/76229 , H01L21/76227 , H01L21/823878 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11546
摘要： A semiconductor device includes: a semiconductor substrate; and STIs formed in the semiconductor substrate and defining a high voltage transistor area and a low voltage transistor area, the STIs including: a first STI with a first liner including a thermal oxide film and not including a nitride film and surrounding at least a portion of the high voltage transistor area; and a second STI with a second liner of a lamination of a thermal oxide film and a nitride film and surrounding the low voltage transistor area.
摘要翻译：半导体器件包括：半导体衬底; 以及形成在所述半导体衬底中并且限定高压晶体管区域和低电压晶体管区域的STI，所述STI包括：具有包括热氧化膜并且不包括氮化物膜并且包围至少一部分高压晶体管面积; 以及第二STI，其具有热氧化膜和氮化物膜的叠层的第二衬垫，并围绕所述低电压晶体管区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式