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21. 发明授权

US07245525B1 Data restore in thryistor based memory devices 失效
标题翻译：基于晶体管的存储器件的数据恢复
公开(公告)号：US07245525B1
公开(公告)日：2007-07-17
申请号：US11194184
申请日：2005-08-01
申请人： Zachary K. Lee , Farid Nemati , Scott Robins
发明人： Zachary K. Lee , Farid Nemati , Scott Robins
IPC分类号： G11C11/00
CPC分类号： G11C11/39
摘要： In a thyristor based memory cell, one end of a reversed-biased diode is connected to the cathode of the thyristor. During standby, the second end of the diode is biased at a voltage that is higher than that at the cathode of the thyristor. During restore operation, the second end is pulled down to zero or even a negative value. If the cell is storing a “1,” the voltage at the thyristor cathode can be approximately 0.6 volt at the time of the pull down. The large forward-bias across the diode pulls down the thryistor cathode. This causes the thyristor to be restored. If the cell is storing a “0,” the voltage at the thyristor cathode can be approximately zero volt. The small or zero forward-bias across the diode is unable to disturb the “0” state. As a result, the memory cell is restored to its original state.
摘要翻译：在基于晶闸管的存储单元中，反向偏置二极管的一端连接到晶闸管的阴极。在待机期间，二极管的第二端被偏置在高于晶闸管阴极处的电压。在恢复操作期间，第二端被拉低至零或甚至负值。如果电池正在存储“1”，则在下拉时，晶闸管阴极处的电压可能约为0.6伏特。二极管两端的大正向偏置可降低晶闸管阴极。这导致晶闸管恢复。如果电池正在存储“0”，晶闸管阴极处的电压可以近似为零伏。二极管两端的小或零正向偏置不能干扰“0”状态。结果，存储单元恢复到其原始状态。

22. 发明授权

US06944051B1 Data restore in thryistor based memory devices 失效
标题翻译：基于晶体管的存储器件的数据恢复
公开(公告)号：US06944051B1
公开(公告)日：2005-09-13
申请号：US10695171
申请日：2003-10-29
申请人： Zachary K. Lee , Farid Nemati , Scott Robins
发明人： Zachary K. Lee , Farid Nemati , Scott Robins
IPC分类号： G11C11/00
CPC分类号： G11C11/39
摘要： In a thyristor based memory cell, one end of a reversed-biased diode is connected to the cathode of the thyristor. During standby, the second end of the diode is biased at a voltage that is higher than that at the cathode of the thyristor. During restore operation, the second end is pulled down to zero or even a negative value. If the cell is storing a “1,” the voltage at the thyristor cathode can be approximately 0.6 volt at the time of the pull down. The large forward-bias across the diode pulls down the thryistor cathode. This causes the thyristor to be restored. If the cell is storing a “0,” the voltage at the thyristor cathode can be approximately zero volt. The small or zero forward-bias across the diode is unable to disturb the “0” state. As a result, the memory cell is restored to its original state.
摘要翻译：在基于晶闸管的存储单元中，反向偏置二极管的一端连接到晶闸管的阴极。在待机期间，二极管的第二端被偏置在高于晶闸管阴极处的电压。在恢复操作期间，第二端被拉低至零或甚至负值。如果电池正在存储“1”，则在下拉时，晶闸管阴极处的电压可能约为0.6伏特。二极管两端的大正向偏置可降低晶闸管阴极。这导致晶闸管恢复。如果电池正在存储“0”，晶闸管阴极处的电压可以近似为零伏。二极管两端的小或零正向偏置不能干扰“0”状态。结果，存储单元恢复到其原始状态。

23. 发明授权

US06462359B1 Stability in thyristor-based memory device 失效
标题翻译：基于晶闸管的存储器件的稳定性
公开(公告)号：US06462359B1
公开(公告)日：2002-10-08
申请号：US09814980
申请日：2001-03-22
申请人： Farid Nemati , Hyun-Jin Cho , Scott Robins
发明人： Farid Nemati , Hyun-Jin Cho , Scott Robins
IPC分类号： H01L2974
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： A semiconductor device having a thyristor-based memory device exhibits improved stability under adverse operating conditions related to temperature, noise, electrical disturbances and light. In one particular example embodiment of the present invention, a semiconductor device includes a thyristor-based memory device that uses a shunt between a base and emitter region in a thyristor that effects a leakage current in the thyristor. The thyristor includes a capacitively coupled control port and anode and cathode end portions. Each of the end portions has an emitter region and an adjacent base region, and the current shunt is located between the emitter and base region of one of the end portions of the thyristor. The current shunt is configured and arranged to shunt low-level current between the emitter region and the adjacent base region, and in doing so improves the ability of the device to operate under adverse conditions that would, absent the shunt, result in inadvertent turn on, while keeping the standby current of the memory device to an acceptably low level.
摘要翻译：具有基于晶闸管的存储器件的半导体器件在与温度，噪声，电扰动和光线相关的不利操作条件下表现出改进的稳定性。在本发明的一个具体示例性实施例中，半导体器件包括基于晶闸管的存储器件，其使用晶闸管中的基极和发射极区之间的分流器，其实现晶闸管中的漏电流。晶闸管包括电容耦合的控制端口和阳极和阴极端部分。每个端部具有发射极区域和相邻的基极区域，并且电流分流器位于晶闸管的一个端部的发射极和基极区域之间。电流分流器被配置和布置成在发射极区域和相邻基极区域之间分流低电平电流，并且在这样做时改善了器件在不利条件下操作的能力，这在不存在分流的情况下导致无意中导通同时将存储器件的待机电流保持在可接受的低电平。

24. 发明授权

US07859011B2 High ion/Ioff SOI MOSFET using body voltage control 失效
标题翻译：高离子/半导体SOI MOSFET采用体电压控制
公开(公告)号：US07859011B2
公开(公告)日：2010-12-28
申请号：US12368171
申请日：2009-02-09
申请人： Zachary K. Lee , Farid Nemati , Scott Robins
发明人： Zachary K. Lee , Farid Nemati , Scott Robins
IPC分类号： H01L29/74
CPC分类号： H01L27/1203 , H01L29/7841
摘要： A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.
摘要翻译：半导体器件可以包括部分耗尽的SOI MOSFET，其具有设置在源极和漏极之间的浮体区域。可以驱动浮体区域以接收注入的载流子，以在MOSFET的操作期间调整其电位。在特定的情况下，MOSFET可以包括与MOSFET的漏极/源极区域和与体区域相对的一侧连续关系的半导体材料的另一区域。该附加区域可以形成为具有与漏极/源极相反的类型的导电性，并且可以建立每个主体，漏极/源极和附加区域的有效双极器件。其几何形状和掺杂可被设计成建立足以帮助载流子注入浮体区域的传输增益，但足够小以防止与MOSFET的互锁。

25. 发明授权

US07109532B1 High Ion/Ioff SOI MOSFET using body voltage control 失效
公开(公告)号：US07109532B1
公开(公告)日：2006-09-19
申请号：US10746758
申请日：2003-12-23
申请人： Zachary K. Lee , Farid Nemati , Scott Robins
发明人： Zachary K. Lee , Farid Nemati , Scott Robins
IPC分类号： H01L29/74 , H01L27/12
CPC分类号： H01L27/1203 , H01L29/7841
摘要： A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.

26. 发明授权

US06891205B1 Stability in thyristor-based memory device 失效
标题翻译：基于晶闸管的存储器件的稳定性
公开(公告)号：US06891205B1
公开(公告)日：2005-05-10
申请号：US10666220
申请日：2003-09-19
申请人： Hyun-Jin Cho , Farid Nemati , Scott Robins
发明人： Hyun-Jin Cho , Farid Nemati , Scott Robins
IPC分类号： G11C11/39 , H01L29/74 , H01L29/749
CPC分类号： H01L29/749 , G11C11/39 , H01L29/7436
摘要： A semiconductor device having a thyristor-based memory device exhibits improved stability under adverse operating conditions related to temperature, noise, electrical disturbances and light. In one particular example embodiment of the present invention, a semiconductor device includes a thyristor-based memory device that uses a shunt that effects a leakage current in the thyristor. The thyristor includes a capacitively-coupled control port and anode and cathode end portions. Each of the end portions has an emitter region and an adjacent base region. In one implementation, the current shunt is located between the emitter and base region of one of the end portions of the thyristor and is configured and arranged to shunt low-level current therebetween. In connection with an example embodiment, it has been discovered that shunting current in this manner improves the ability of the device to operate under adverse conditions that would, absent the shunt, result in inadvertent turn on, while keeping the standby current of the memory device to an acceptably low level.
摘要翻译：具有基于晶闸管的存储器件的半导体器件在与温度，噪声，电扰动和光线相关的不利操作条件下表现出改进的稳定性。在本发明的一个具体示例实施例中，半导体器件包括基于晶闸管的存储器件，其使用在晶闸管中产生漏电流的分流器。晶闸管包括电容耦合控制端口和阳极和阴极端部分。每个端部具有发射极区域和相邻的基极区域。在一个实施方案中，电流分流器位于晶闸管的一个端部的发射极和基极区域之间，并且被配置和布置成在它们之间分流低电平电流。结合示例性实施例，已经发现，以这种方式分流电流提高了器件在不利条件下操作的能力，这种不利条件将在不存在分流的情况下导致无意中导通，同时保持存储器件的待机电流达到可接受的低水平。

27. 发明授权

US08093107B1 Thyristor semiconductor memory and method of manufacture 失效
标题翻译：晶闸管半导体存储器及其制造方法
公开(公告)号：US08093107B1
公开(公告)日：2012-01-10
申请号：US12271758
申请日：2008-11-14
申请人： Farid Nemati , Scott Robins , Kevin J. Yang
发明人： Farid Nemati , Scott Robins , Kevin J. Yang
IPC分类号： H01L21/332 , H01L21/337 , H01L21/8238
CPC分类号： G11C11/39 , H01L27/1027 , H01L29/66393 , H01L29/7436
摘要： A thyristor based semiconductor device includes a thyristor having cathode, P-base, N-base and anode regions disposed in electrical series relationship. The N-base region for the thyristor has a cross-section that defines an inverted “T” shape, wherein a buried well in semiconductor material forms is operable as a part of the N-base. The stem to the inverted “T” shape extends from the upper surface of the semiconductor material to the buried well. The P-base region for the thyristor extends laterally outward from a side of the stem that is opposite the anode region of the thyristor, and is further bounded between the buried well and a surface of the semiconductor material. A thinned portion for the N-base is defined between the cathode region of the thyristor and the buried well, and may include supplemental dopant of concentration greater than that for some other portion of the N-base.
摘要翻译：一种基于晶闸管的半导体器件包括具有阴极，P基极，N基极和阳极区域的晶闸管，其以电串联的关系设置。用于晶闸管的N基区域具有限定反向“T”形的横截面，其中半导体材料形式的掩埋阱可操作为N基底的一部分。反向“T”形的杆从半导体材料的上表面延伸到掩埋井。用于晶闸管的P基区域从杆的与晶闸管的阳极区域相对的侧面横向向外延伸，并且进一步限定在掩埋阱和半导体材料的表面之间。在晶闸管的阴极区域和掩埋阱之间限定了用于N-碱的薄化部分，并且可以包括浓度大于N基底的其它部分浓度的补充掺杂剂。

28. 发明授权

US07858449B2 Thyristor device with carbon lifetime adjustment implant and its method of fabrication 失效
标题翻译：具有碳寿命调整植入物的晶闸管器件及其制造方法
公开(公告)号：US07858449B2
公开(公告)日：2010-12-28
申请号：US12367891
申请日：2009-02-09
申请人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
发明人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
IPC分类号： H01L29/72
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
摘要翻译：在制造半导体存储器件的方法中，晶闸管可以形成在半导体材料层中。可以在用于晶闸管的基极 - 发射极结区域中注入和退火碳以影响泄漏特性。因此可以选择碳的密度和/或轰击能量和/或退火，以建立连接的低电压，泄漏特性，基本上大于其没有碳的泄漏。在一个实施例中，注入碳的退火可以与半导体器件的其它注入区域的激活共同进行。

29. 发明授权

US07488626B1 Thyristor device with carbon lifetime adjustment implant and its method of fabrication 失效
标题翻译：具有碳寿命调整植入物的晶闸管器件及其制造方法
公开(公告)号：US07488626B1
公开(公告)日：2009-02-10
申请号：US11483859
申请日：2006-07-10
申请人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
发明人： Kevin J. Yang , Farid Nemati , Scott Robins , James D. Plummer , Hyun-Jin Cho
IPC分类号： H01L29/72
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
摘要翻译：在制造半导体存储器件的方法中，晶闸管可以形成在半导体材料层中。可以在用于晶闸管的基极 - 发射极结区域中注入和退火碳以影响泄漏特性。因此可以选择碳的密度和/或轰击能量和/或退火，以建立连接的低电压，泄漏特性，基本上大于其没有碳的泄漏。在一个实施例中，注入碳的退火可以与半导体器件的其它注入区域的激活共同进行。

30. 发明授权

US07894256B1 Thyristor based memory cell 失效
标题翻译：基于晶闸管的存储单元
公开(公告)号：US07894256B1
公开(公告)日：2011-02-22
申请号：US11881159
申请日：2007-07-25
申请人： Farid Nemati , Scott Robins , Kevin J. Yang
发明人： Farid Nemati , Scott Robins , Kevin J. Yang
IPC分类号： G11C11/39
CPC分类号： G11C11/39 , H01L27/1027 , H01L29/66393 , H01L29/7436
摘要： A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. The memory cell contains a thyristor body and a gate. The thyristor body has two end region and two base regions, and it is disposed on top of a well. The memory cell is positioned between two isolation regions, and the isolation regions are extended below the well. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.
摘要翻译：新的存储单元仅包含一个晶闸管，而不需要包括一个存取晶体管。可以在体硅晶片上制造包含这些存储单元的存储器阵列。存储单元包含晶闸管体和栅极。晶闸管体具有两个端部区域和两个基极区域，并且它设置在阱的顶部。存储单元位于两个隔离区之间，并且隔离区延伸到阱的下方。第一端区连接到字线，位线和第三线之一。第二端区连接到字线，位线和第三线中的另一端。门连接到字线，位线和第三行的剩余部分。

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