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21. 发明授权

US06757819B1 Microprocessor with instructions for shifting data responsive to a signed count value 有权
标题翻译：微处理器，具有响应于带符号计数值移位数据的指令
公开(公告)号：US06757819B1
公开(公告)日：2004-06-29
申请号：US09703141
申请日：2000-10-31
申请人： David Hoyle , Richard H. Scales , Min Wang , Joseph R. Zbiciak
发明人： David Hoyle , Richard H. Scales , Min Wang , Joseph R. Zbiciak
IPC分类号： G06F1582
CPC分类号： G06F9/30032 , G06F9/30072
摘要： A data processing system is provided with a digital signal processor which has an instruction for shifting a source operand in response to a signed shift count value and storing the shifted result in a selected destination register. A first 32-bit operand (600) is treated as a signed shift value that has a sign and a shift count value. A second operand (602) is shifted by an amount according to the shift count value and in a direction according to the sign of the shift count. One instruction is provided that performs a right shift for a positive shift count and a left shift for a negative shift count, and another instruction is provided performs a left shift for a positive shift count and a right shift for a negative shift count. If the shift count value is greater than 31, then the shift is limited to 31.
摘要翻译：数据处理系统具有数字信号处理器，该数字信号处理器具有响应于有符号移位计数值移位源操作数并将移位结果存储在所选择的目标寄存器中的指令。第一个32位操作数（600）被视为具有符号和移位计数值的有符号位移值。第二操作数（602）根据移位计数值和根据移位计数的符号的方向移位量。提供一个指令，其执行用于正移位计数的右移位和用于负移位计数的左移位，并且提供另一指令来执行用于正移位计数的左移位和负移位计数的右移位。如果移位计数值大于31，则移位限制为31。

22. 发明授权

US06735737B2 Error correction structures and methods 有权
标题翻译：纠错结构和方法
公开(公告)号：US06735737B2
公开(公告)日：2004-05-11
申请号：US09788850
申请日：2001-02-20
申请人： Jagadeesh Sankaran , David Hoyle
发明人： Jagadeesh Sankaran , David Hoyle
IPC分类号： H03M1300
CPC分类号： H03M13/1545 , H03M13/1515 , H03M13/152 , H03M13/157 , H03M13/158
摘要： A parallel Chien search by partitioning of the nonzero elements of a root field and using a parallel Galois multiplier.
摘要翻译：通过分割根域的非零元素并使用平行Galois乘法器进行并行Chien搜索。

23. 发明申请

US20100005372A1 METHOD AND APPARATUS FOR IMPROVING TRELLIS DECODING 审中-公开
标题翻译：改进色拉解码的方法和装置
公开(公告)号：US20100005372A1
公开(公告)日：2010-01-07
申请号：US12496527
申请日：2009-07-01
申请人： Peter R. Dent , Eric Biscondi , David Hoyle
发明人： Peter R. Dent , Eric Biscondi , David Hoyle
IPC分类号： H03M13/23 , G06F11/10
CPC分类号： H03M13/41 , H03M13/395
摘要： A digital signal processor for decoding Trellis based channel encoding stages based on radix-4 stages comprising means for rearranging the input and output data in Radix-4 Viterbi decoding to make inter-stage Trellis data movement suitable for use in the digital signal processor.
摘要翻译：一种用于基于基4级解码基于网格的信道编码级的数字信号处理器，包括用于在基数-4维特比解码中重新排列输入和输出数据的装置，以使适合于在数字信号处理器中使用的阶段间格间数据移动。

24. 发明授权

US07458007B2 Error correction structures and methods 有权
标题翻译：纠错结构和方法
公开(公告)号：US07458007B2
公开(公告)日：2008-11-25
申请号：US09788805
申请日：2001-02-20
申请人： Jagadeesh Sankaran , David Hoyle
发明人： Jagadeesh Sankaran , David Hoyle
IPC分类号： H03M13/29 , H03M13/51
CPC分类号： H03M13/157 , H03M13/37
摘要： A syndrome evaluation with partitioning of a received block of symbols into subsets and interleaved partial syndrome evaluations to overcome multiplier latency. Parallel syndrome evaluations with a parallel multiplier.
摘要翻译：通过将接收的符号块划分成子集和交织的部分综合征评估来克服乘数延迟的综合征评估。平行综合征评估与并行乘数。

25. 发明授权

US07336562B1 Sonic logging tool including receiver and spacer structure 有权
标题翻译：声波测井仪包括接收器和间隔器结构
公开(公告)号：US07336562B1
公开(公告)日：2008-02-26
申请号：US10416264
申请日：2000-11-16
申请人： David Hoyle , Hitoshi Tashiro , Akira Otsuka , Jahir Pabon , Hitoshi Sugiyama
发明人： David Hoyle , Hitoshi Tashiro , Akira Otsuka , Jahir Pabon , Hitoshi Sugiyama
IPC分类号： G01V1/52
CPC分类号： G01V1/523 , Y10S367/911
摘要： A formation logging tool having a substantially continuous central mandrel with regularly spaced mass blocks disposed thereon, at least some of the mass blocks carrying sensors such as receivers. By adopting this structure, the tool can be made to behave as a mass-spring structure and its flexural and extensional behaviour controlled such that its dispersion curve does not extend into the dispersion curve of the formation to be logged. The structure can be applied to the whole of the logging tool or just to the receiver section and/or any spacer section between the receiver and the transmitter section.
摘要翻译：地层测井工具具有基本上连续的中心心轴，其上布置有规则间隔的质量块，至少一些承载传感器的质量块如接收器。通过采用这种结构，该工具可以做成质量 - 弹簧结构，并且其弯曲和拉伸行为被控制，使得其分散曲线不延伸到要记录的地层的分散曲线中。该结构可以应用于整个测井工具，或仅适用于接收器部分和/或接收器和发射器部分之间的任何间隔部分。

26. 发明申请

US20080016320A1 Vector Predicates for Sub-Word Parallel Operations 审中-公开
标题翻译：子字并行操作的向量谓词
公开(公告)号：US20080016320A1
公开(公告)日：2008-01-17
申请号：US11769198
申请日：2007-06-27
申请人： Amitabh Menon , David Hoyle
发明人： Amitabh Menon , David Hoyle
IPC分类号： G06F15/00
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30072 , G06F9/3885
摘要： This invention uses vector predicate registers to control conditional execution of instructions for vector elements within a data word. A particular vector predicate registers is addressed via a register index. The state of bits of the vector predicate register controls whether a corresponding sub-word operation is executed or inhibited.
摘要翻译：本发明使用向量谓词寄存器来控制数据字内的向量元素的指令的条件执行。特定向量谓词寄存器通过寄存器索引寻址。向量谓词寄存器的位的状态控制是否执行相应的子字操作。

27. 发明授权

US07062526B1 Microprocessor with rounding multiply instructions 有权
标题翻译：具有四舍五入乘法指令的微处理器
公开(公告)号：US07062526B1
公开(公告)日：2006-06-13
申请号：US09703140
申请日：2000-10-31
申请人： David Hoyle
发明人： David Hoyle
IPC分类号： G06F7/52 , G06F7/38
CPC分类号： G06F7/5324 , G06F7/49947 , G06F9/30014 , G06F9/30036
摘要： A functional unit in a digital system is provided with a rounding Multiplication instruction, wherein a most significant product of first pair of elements is combined with a least significant product of a second pair of elements, the combined product is rounded, and the final result is stored in a destination. Rounding is performed by adding a rounding value to form an intermediate result, and then shifting the intermediate result right. A combined result is rounded to a fixed length shorter than the combined product.
摘要翻译：数字系统中的功能单元被提供有舍入乘法指令，其中第一对元素的最重要的乘积与第二对元素的最不重要的乘积组合，组合乘积被舍入，最后的结果是存储在目的地。通过添加舍入值以形成中间结果来执行舍入，然后将中间结果右移。组合的结果被舍入到比组合产品短的固定长度。

28. 发明授权

US06748521B1 Microprocessor with instruction for saturating and packing data 有权
标题翻译：具有饱和和打包数据指令的微处理器
公开(公告)号：US06748521B1
公开(公告)日：2004-06-08
申请号：US09702476
申请日：2000-10-31
申请人： David Hoyle
发明人： David Hoyle
IPC分类号： G06F9302
CPC分类号： G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30072
摘要： A data processing system is provided with a digital signal processor which has an instruction for saturating multiple fields of a selected set of source operands and storing the separate saturated results in a selected destination register. A first 32-bit operand (600) and a second 32-bit operand (602) are treated as four 16-bit fields and the sixteen bits in each field are saturated separately. Multi-field saturation circuitry is operable to treat a source operand as a number of fields, such that a multi-field saturated (610) result is produced that includes a number of saturated results each corresponding to each field. One instruction is provided which treats an operand pair as having two packed fields, and another instruction is provided that treats the operand pair has having four packed fields. Saturation circuitry is operable to selectively treat a field as either a signed value or an unsigned value. In another embodiment, an operand size different from 32-bits may be operated on, and the number of fields may be different than two or four.
摘要翻译：数据处理系统具有数字信号处理器，该数字信号处理器具有用于饱和所选择的一组源操作数的多个场的指令，并将分离的饱和结果存储在所选择的目的地寄存器中。第一32位操作数（600）和第二32位操作数（602）被视为四个16位字段，并且每个字段中的十六位分别饱和。多场饱和电路可操作以将源操作数视为多个场，使得产生多场饱和（610）结果，其包括多个对应于每个场的饱和结果。提供一个指令，其将操作数对视为具有两个打包字段，并且提供另一个处理操作数对具有四个打包字段的指令。饱和电路可操作以选择性地将字段视为有符号值或无符号值。在另一个实施例中，可以操作与32位不同的操作数大小，并且字段数可以不同于两个或四个。

29. 发明授权

US06739423B2 Acoustic logging tool 有权
标题翻译：声学测井工具
公开(公告)号：US06739423B2
公开(公告)日：2004-05-25
申请号：US10065407
申请日：2002-10-15
申请人： Hitoshi Tashiro , Jahir Pabon , Frank Morris , Hitoshi Sugiyama , David Hoyle , David Leslie , Kazumasa Kato
发明人： Hitoshi Tashiro , Jahir Pabon , Frank Morris , Hitoshi Sugiyama , David Hoyle , David Leslie , Kazumasa Kato
IPC分类号： G01V140
CPC分类号： G01V1/523 , Y10S367/911
摘要： A sleeve for an acoustic logging tool has a structure with a window section having fewer bars than a conventional sleeve separated by a slotted region with thin circumferential slots which are stress-relieved at the ends (“dumb-bell” shaped). Steel receiver mounts are provided for hydrophone pressure sensors and this, together with the axially oriented hydrophones makes the tool less susceptible to interfering vibration.
摘要翻译：用于声学测井工具的套筒具有窗口部分的结构，其具有比常规套筒更少的杆，其由具有薄的周向狭槽的开槽区域分开，该圆周狭槽在端部（“哑铃形”）处被应力释放。为水听器压力传感器提供钢接收器支架，这与轴向定向的水听器一起使得该工具不易受到干扰振动的影响。

30. 发明授权

US06539467B1 Microprocessor with non-aligned memory access 有权
标题翻译：具有非对齐内存访问的微处理器
公开(公告)号：US06539467B1
公开(公告)日：2003-03-25
申请号：US09703105
申请日：2000-10-31
申请人： Timothy D. Anderson , David Hoyle , Donald E. Steiss , Steven D. Krueger
发明人： Timothy D. Anderson , David Hoyle , Donald E. Steiss , Steven D. Krueger
IPC分类号： G06F1200
CPC分类号： G06F9/3891 , G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/30105 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30145 , G06F9/30167 , G06F9/3552 , G06F9/3555 , G06F9/3816 , G06F9/3824 , G06F9/3828 , G06F9/3853 , G06F9/3885
摘要： A data processing system (1300) is provided with a digital signal processor (DSP) (1301) that has an instruction set architecture (ISA) that is optimized for intensive numeric algorithm processing. The DSP has dual load/store units (.D1, .D2) connected to dual memory ports (T1, T2) in a level one data cache memory controller (1720a). The DSP can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The DSP can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports.
摘要翻译：数据处理系统（1300）具有数字信号处理器（DSP）（1301），该数字信号处理器（1301）具有针对密集数字算法处理而被优化的指令集架构（ISA）。 DSP具有连接到一级数据高速缓冲存储器控制器（1720a）中的双存储器端口（T1，T2）的双重加载/存储单元（.D1，.D2）。 DSP可以通过执行两个加载/存储指令来并行执行两个对齐的数据传输，每个数据传输具有一个字节，两个字节，四个字节或八个字节的长度。 DSP还可以通过执行利用两个存储器目标端口的不对齐加载/存储指令来执行具有四字节或八字节长度的单个非对齐数据传输。

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