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1. 发明授权

US10320420B2 Bit-flip coding 有权
公开(公告)号：US10320420B2
公开(公告)日：2019-06-11
申请号：US15112013
申请日：2014-01-24
申请人： Hewlett Packard Enterprise Development LP
发明人： Erik Ordentlich , Ron M. Roth
IPC分类号： H03M13/15 , H03M13/29 , H03M13/47 , H03M13/51 , G06F11/10 , G11C29/52 , H03M13/53
摘要： Bit-flip coding uses a bit-flip encoder to flip bits in a redundancy-intersecting vector of a binary array having n rows and n columns until Hamming weights of the binary array are within a predetermined range Δ of n divided by two. Information bits of an input data word to the bit-flip coding apparatus are stored in locations within the binary array that are not occupied by n redundancy bits of a redundancy vector.

2. 发明授权

US09300434B2 Zero sum signaling in a digital system environment 有权
标题翻译：数字系统环境中的零和信令
公开(公告)号：US09300434B2
公开(公告)日：2016-03-29
申请号：US14125292
申请日：2012-06-08
申请人： Erik S. Daniel , Robert W. Techentin
发明人： Erik S. Daniel , Robert W. Techentin
IPC分类号： H03M13/11 , H04L1/00 , H04L25/49 , H04L25/14 , H03M13/51 , G06F11/10 , G06F13/42
CPC分类号： H04L1/004 , G06F11/10 , G06F13/423 , H03M13/51 , H04L1/0042 , H04L25/14 , H04L25/4908
摘要： Zero sum signaling schemes utilize coding across data words to allow the use of single-ended buffers while mitigating simultaneous switching noise (SSN) in digital systems. Zero sum signaling may include balanced zero sum coding (target disparity=0) and nearly balanced zero sum coding (target disparity=±d). Zero sum signaling may reduce simultaneous switching noise as compared to single-ended signaling while allowing a reduction in the number of physical channels (e.g. circuit board traces) by nearly a factor of two as compared to differential signaling.
摘要翻译：零和信令方案利用跨数据字的编码，以允许使用单端缓冲器，同时减轻数字系统中的同时开关噪声（SSN）。零和信号可以包括平衡零和编码（目标差异= 0）和几乎平衡的零和编码（目标差异=±d）。与单端信号相比，零和信号可以减少同时的开关噪声，同时允许与差分信号相比将物理信道（例如电路板迹线）的数量减少近一倍。

3. 发明申请

US20130086457A1 DETECTING CODEWORDS IN SOLID-STATE STORAGE DEVICES 有权
标题翻译：检测固态储存装置中的编码
公开(公告)号：US20130086457A1
公开(公告)日：2013-04-04
申请号：US13622451
申请日：2012-09-19
申请人： International Business Machines Corporation
发明人： Thomas Mittelholzer , Nikolaos Papandreou , Charalampos Pozidis
IPC分类号： H03M13/51
CPC分类号： G11C11/5678 , G11C2211/563 , G11C2211/5634
摘要： A method for detecting codewords in solid-state storage devices. The method includes the steps of: obtaining respective read signals by reading memory cells that stores a group of codewords, where each of the read signals includes N signal components corresponding to respective symbols of the codeword; producing an ordered read signal by ordering the components of each of the read signals according to a signal level; producing an average read signal by averaging corresponding components of the ordered read signals; determining a reference signal level that corresponds to each of q levels of the memory cells in relation to the average read signal with predefined probabilities of each symbol value occurring at each symbol position in the codeword, where the symbols of the codeword are ordered according to the symbol value; and detecting the codeword corresponding to each of the read signal in relation to the reference signal levels.
摘要翻译：一种用于检测固态存储设备中的码字的方法。该方法包括以下步骤：通过读取存储一组码字的存储器单元来获得相应的读取信号，其中每个读取信号包括与码字的各个符号对应的N个信号分量; 通过根据信号电平对每个读取信号的分量进行排序来产生有序的读取信号; 通过对有序读取信号的相应分量进行平均来产生平均读取信号; 确定与所述平均读取信号相对应的所述存储器单元的每个q电平的参考信号电平，所述参考信号电平具有在所述码字中的每个符号位置处出现的每个符号值的预定义概率，其中所述码字的符号根据符号值并且相对于参考信号电平检测与每个读取信号相对应的码字。

4. 发明授权

US07594159B2 Signature field in a latency measurement frame 有权
标题翻译：延迟测量帧中的签名字段
公开(公告)号：US07594159B2
公开(公告)日：2009-09-22
申请号：US10974214
申请日：2004-10-26
申请人： Craig Glenn Fujikami , William Thomas Hatley , Jocelyn Tamie Kunimitsu , Jon Kanji Otaguro , Carl Masami Uyehara
发明人： Craig Glenn Fujikami , William Thomas Hatley , Jocelyn Tamie Kunimitsu , Jon Kanji Otaguro , Carl Masami Uyehara
IPC分类号： H03M13/00 , H03M13/51
CPC分类号： H04L1/0041 , H04L1/0061 , H04L1/0072 , H04L63/12 , H04L63/16
摘要： Information is added to an encapsulated payload in a data field of a frame subsequently to placing a checksum into a checksum field of a header encapsulating the payload, wherein the checksum has been determined from byte values of the header and the payload, yet having the checksum remaining detectable as valid upon interpretation of the header and the payload. A signature field that contains the information is inserted into the data field. The signature field has a checksum cheater subfield. A one's complement of a checksum determined from byte values of the information is then placed into the checksum cheater subfield. Accordingly, the checksum in the checksum field of the header remains valid.
摘要翻译：将信息添加到随后将校验和放入封装有效负载的报头的校验和字段中的帧的数据字段中的封装有效载荷，其中校验和已经从头部和有效载荷的字节值确定，但具有校验和在标题和有效载荷的解释上仍然可以检测为有效。包含信息的签名字段被插入到数据字段中。签名字段具有校验和骗子子字段。然后将从信息的字节值确定的校验和的补码放入校验和骗子子字段。因此，标题的校验和字段中的校验和仍然有效。

5. 发明授权

US6047086A Image information encoding/decoding system 失效
公开(公告)号：US6047086A
公开(公告)日：2000-04-04
申请号：US119028
申请日：1998-07-20
申请人： Shinichi Kikuchi , Tetsuya Kitamura , Hideki Mimura , Kazuhiko Taira
发明人： Shinichi Kikuchi , Tetsuya Kitamura , Hideki Mimura , Kazuhiko Taira
IPC分类号： H04N1/64 , F42B10/64 , G06T9/00 , G11B20/00 , G11B20/12 , H03M7/46 , H03M13/51 , H04N1/41 , H04N5/85 , H04N7/32 , H04N7/52 , H04N9/804 , H04N9/806 , H04N9/82 , H04N21/236 , H04N21/434 , G06K9/36
CPC分类号： H04N9/8042 , G11B20/00007 , G11B20/1217 , H03M7/46 , H04N19/93 , H04N21/236 , H04N21/434 , H04N5/85 , H04N9/8063 , H04N9/8227
摘要： A bit train of a plurality of continuous pixels is compressed according to a new run-length compression scheme. In this run-length compression scheme, the run information of one unit of compression includes run-length information indicating the continuous number of the same pixel data blocks, or the number of pixels followed, and pixel data having a two-bit configuration for discriminating three or more colors of the pixels.

6. 发明授权

US5260917A Signal reproduction apparatus 失效
标题翻译：信号再生装置
公开(公告)号：US5260917A
公开(公告)日：1993-11-09
申请号：US535896
申请日：1990-06-11
申请人： Akira Mashimo
发明人： Akira Mashimo
IPC分类号： G11B11/105 , G11B20/10 , G11B20/14 , G11B20/18 , H03M7/14 , H03M7/20 , H03M13/51 , H04L25/49 , G11B7/00 , G11B5/09
CPC分类号： G11B20/10009 , G11B11/10515 , G11B20/1426
摘要： A signal reproduction apparatus reproduces data from an information recording disc. The data is recorded for every data block and is modulated so that data in one data block has n (n is an integer) bits including arbitrary m (m is integer and less than the n) bits each having an active value. The signal reproduction apparatus includes, a reading circuit reading out the data from the information recording disc, a converter converting the data into a pulse signal for every data block, the pulse signal having an active pulse corresponding to the active value of the data and an inactive pulse corresponding to the inactive value of the data, a judgment circuit judging whether or not the pulse signal has m active pulses for every data block, and a correction circuit correcting the pulse signal so that the pulse signal has m active pulses in one data block when the judgment circuit judges that the pulse signal has a number of active pulses other than the m in the one data block.
摘要翻译：信号再现装置从信息记录盘再现数据。对于每个数据块记录数据并被调制，使得一个数据块中的数据具有n（n是整数）位，其包括任意的m（m是整数且小于n个），每个位具有有效值。信号再现装置包括：从信息记录盘读出数据的读取电路，将数据转换为每个数据块的脉冲信号的转换器，脉冲信号具有对应于数据的有效值的有效脉冲，以及对应于数据的非活动值的无效脉冲，判断电路是否判断脉冲信号是否具有每个数据块的m个有效脉冲;以及校正电路，校正脉冲信号，使脉冲信号在一个数据中具有m个有效脉冲当判断电路判断脉冲信号在一个数据块中具有除了m以外的多个有效脉冲时，阻塞。

7. 发明授权

US4176287A Versatile CMOS decoder 失效
标题翻译：多功能CMOS解码器
公开(公告)号：US4176287A
公开(公告)日：1979-11-27
申请号：US896071
申请日：1978-04-13
申请人： James J. Remedi
发明人： James J. Remedi
IPC分类号： H03M7/20 , H03M13/51 , H03K17/60 , H03K5/18 , H03K13/00
CPC分类号： H03M13/51 , H03M7/20
摘要： A CMOS decoder capable of providing a one of n, a two of n, or a three of n decoded output, where n is equal to the number of outputs of the decoder and is a function of the number of bits in a digital signal to be decoded. A first plurality of transistors are used to precharge each of the decoder's outputs to a first voltage potential. A second plurality of transistors are placed in series between the first node and each of the outputs. The second plurality of transistors are controlled by the coded digital signal that is being decoded. The number of decoded outputs can be varied by connecting some of the outputs to some of the transistors of the second plurality of transistors or by connecting others of the outputs to junctions formed by the series placed transistors. In a preferred embodiment, a pair of back-to-back inverters are connected to each of the outputs to provide a static decoder.
摘要翻译：能够提供n，n中的n个或n个解码输出中的三个的CMOS解码器，其中n等于解码器的输出数，并且是数字信号中的位数的函数被解码。使用第一多个晶体管来将每个解码器的输出预充电到第一电压电位。在第一节点和每个输出之间串联放置第二多个晶体管。第二多个晶体管由被解码的编码数字信号控制。可以通过将一些输出连接到第二多个晶体管的一些晶体管或通过将其他输出连接到由串联放置的晶体管形成的结而改变解码输出的数量。在优选实施例中，一对背对背反相器连接到每个输出以提供静态解码器。

8. 发明授权

US4090173A Vital digital communication system 失效
标题翻译：重要的数字通信系统
公开(公告)号：US4090173A
公开(公告)日：1978-05-16
申请号：US751505
申请日：1976-12-17
申请人： Henry C. Sibley
发明人： Henry C. Sibley
IPC分类号： G06F11/16 , G08C25/00 , H03M13/51 , H04L1/00 , G06F11/08
CPC分类号： G08C25/00 , G06F11/1625 , H03M13/51 , H04L1/00
摘要： An all-digital communication system is arranged to exhibit fail-safe qualities. Each message includes a pair of words, each word separated from every other word by framing information in the form of two bits, either 1/0 or 0/1. Each word in the message is arranged to exhibit a constant ratio of 1's to 0's, so that more than a single change in any bit location is needed to change from one valid message word to another. The second word in each message is the complement of the first. Two decoders are disclosed, a hard-wired embodiment and an embodiment employing a microprocessor. In the hard-wired embodiment, straightforward decoding is employed to determine the apparent message, and the apparent message is encoded to generate a locally generated message which is then compared, bit by bit, with the received message employing vital logic techniques. Assuming each of the received and locally generated bits compare, the message is validated.In the microprocessor embodiment, decoding of each word is accomplished by a table. Several checks are run to determine that the microprocessor is operating properly. The checks if successfully completed, produce a check word, which is not stored in the machine. The check word generated by decoding of the second word of a message should be complement of the first check word. External hardware determines the existence of each check word, in sequence, and allows the decoded microprocessor output to be effective.
摘要翻译：全数字通信系统被安排为具有故障安全性质。每个消息包括一对单词，每个单词通过以1/0或0/1的两位形式的成帧信息与每个其他单词分离。消息中的每个字被布置为呈现1到0的恒定比率，使得需要多于一个位置的单个改变以从一个有效的消息字改变到另一个。每条消息中的第二个字是第一个的补语。公开了两个解码器，硬接线实施例和采用微处理器的实施例。在硬接线的实施例中，采用简单的解码来确定明显的消息，并且对视在的消息进行编码以产生本地产生的消息，然后将该消息逐位地与接收到的使用重要逻辑技术的消息进行比较。假设接收到的和本地产生的比特中的每一个比较，则该消息被验证。

9. 发明授权

US3965457A Digital control processor 失效
标题翻译：数字控制处理器
公开(公告)号：US3965457A
公开(公告)日：1976-06-22
申请号：US415423
申请日：1973-11-13
申请人： Keith Harwood
发明人： Keith Harwood
IPC分类号： G05B19/05 , H03M13/51 , H04J3/12 , H04Q1/39 , H04Q1/457 , H04Q3/545 , H04Q11/04 , G06F15/46 , G05B15/02 , G05B19/02
CPC分类号： H04J3/12 , G05B19/05 , H03M13/51 , H04Q1/39 , H04Q1/4575 , H04Q11/04 , H04Q11/0407 , H04Q3/54591 , G05B2219/15055
摘要： A digital control processor for controlling a number of relay sets from digital information received from a digital PABX. The digital control processor consists essentially of a first-in first-out memory and a combinational logic unit. The memory stores information relevant to an operation to be performed by the processor and re-cycles the information until the operation has been performed. The memory determines the action of the combinational logic unit which action includes changing the state of one of the relay sets. The action of the combinational logic unit is determined by time varying data states from the memory and/or from a relay set or sets. The digital control processor acts as an interface device between the digital/electronic world of the PABX and the analogue/mechanical world of the public exchange. The device receives digital information from a processor in the PABX and also monitors the current state of all the relay sets. The device accepts a digital signal from the PABX processor in a short time, which information relates to an action to be performed by one of the relay sets and may include information indicating a digit to be transmitted to line in the form of impulses. The device then causes the relevant relay set to perform the desired action without further reference to the PABX processor. The device is capable of locating the relay set which has been in a particular state for the longest period of time upon request from the PABX processor for a relay set in that state.
摘要翻译：一种数字控制处理器，用于从数字PABX接收的数字信息中控制多个继电器组。数字控制处理器主要由先入先出存储器和组合逻辑单元组成。存储器存储与要由处理器执行的操作相关的信息，并且重新循环信息直到执行操作。存储器确定组合逻辑单元的动作，该动作包括改变一个继电器组的状态。组合逻辑单元的动作由来自存储器和/或来自中继集合的时变数据状态确定。数字控制处理器充当PABX的数字/电子世界与公共交换的模拟/机械世界之间的接口设备。该设备从PABX中的处理器接收数字信息，并监视所有继电器组的当前状态。该设备在短时间内接收来自PABX处理器的数字信号，该信息涉及由一个继电器组执行的动作，并且可以包括指示要以脉冲形式发送到行的数字的信息。然后，设备使相关的继电器组执行所需的动作，而无需进一步参考PABX处理器。该设备能够根据请求从PABX处理器定位处于特定状态的中继集合，用于在该状态下的中继集。

10. 发明授权

US3745558A Data guard circuit 失效
标题翻译：数据保护电路
公开(公告)号：US3745558A
公开(公告)日：1973-07-10
申请号：US3745558D
申请日：1972-02-28
申请人： GTE AUTOMATIC ELECTRIC LAB INC
发明人： MORSTADT R
IPC分类号： H03M13/51 , H04L27/26 , G06F3/00
CPC分类号： H04L27/26 , H03M13/51
摘要： A circuit providing parallel-coded format receivers with good retention of character duration information and a high degree of immunity to channel noise, speech, and other channel energy that the receiver might detect, but which violate the parallel-code format or timing restrictions.

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