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21. 发明授权

US07298012B2 Shallow junction semiconductor 失效
标题翻译：浅结半导体
公开(公告)号：US07298012B2
公开(公告)日：2007-11-20
申请号：US11307537
申请日：2006-02-11
申请人： Mario M. Pelella , William George En , Eric Paton , Witold P. Maszara
发明人： Mario M. Pelella , William George En , Eric Paton , Witold P. Maszara
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28518 , H01L21/823814 , H01L29/6656 , H01L29/6659
摘要： An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A silicide layer is on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide layer incorporates a substantially uniformly distributed and concentrated dopant therein. A shallow source/drain junction is beneath the salicide layer. An interlayer dielectric is above the semiconductor substrate, and contacts are in the interlayer dielectric to the salicide layer.
摘要翻译：提供了具有半导体衬底的集成电路。栅极电介质位于半导体衬底上，栅极位于栅极电介质上。硅化物层位于与栅极和栅极电介质相邻的半导体衬底上。硅化物层在其中包含基本均匀分布和浓缩的掺杂剂。浅层源极/漏极结在自对准层下面。层间电介质位于半导体衬底之上，并且触点位于硅化物层的层间电介质中。

22. 发明授权

US07265420B2 Semiconductor substrate layer configured for inducement of compressive or expansive force 有权
标题翻译：构造成用于诱导压缩或膨胀力的半导体衬底层
公开(公告)号：US07265420B2
公开(公告)日：2007-09-04
申请号：US11179282
申请日：2005-07-12
申请人： Mario M. Pelella , Simon S. Chan
发明人： Mario M. Pelella , Simon S. Chan
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/3043 , H01L29/7842
摘要： An integrated circuit (IC) utilizes a strained layer. The substrate can utilize trenches in a base layer to induce stress in a layer. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.
摘要翻译：集成电路（IC）利用应变层。衬底可以利用基层中的沟槽以在层中诱导应力。沟槽在绝缘体上半导体（SOI）晶片的体基板或基底层的背侧上限定支柱。

23. 发明授权

US07223640B2 Semiconductor component and method of manufacture 失效
标题翻译：半导体元件及制造方法
公开(公告)号：US07223640B2
公开(公告)日：2007-05-29
申请号：US11071375
申请日：2005-03-03
申请人： Mario M. Pelella , Darin A. Chan , Simon S. Chan
发明人： Mario M. Pelella , Darin A. Chan , Simon S. Chan
IPC分类号： H01L21/00 , H01L21/20 , H01L21/84 , H01L21/336 , H01L21/8234 , H01L21/425
CPC分类号： H01L21/823481 , H01L21/84 , H01L27/1203
摘要： A semiconductor component having analog and logic circuit elements manufactured from an SOI substrate and a method for manufacturing the semiconductor component. An SOI substrate has a support wafer coupled to an active wafer through an insulating material. Openings are formed in the active wafer, extend through the insulating material, and expose portions of the support wafer. Epitaxial semiconductor material is grown on the exposed portions of the support wafer. Analog circuitry is manufactured from the epitaxially grown semiconductor material and high performance logic circuitry is manufactured from the active wafer. The processing steps for manufacturing the analog circuitry are decoupled from the steps for manufacturing the high performance logic circuitry. A substrate contact is made from a portion of the epitaxially grown semiconductor material that is electrically isolated from the portion in which the analog circuitry is manufactured.
摘要翻译：具有由SOI衬底制造的模拟和逻辑电路元件的半导体元件和用于制造半导体元件的方法。 SOI衬底具有通过绝缘材料耦合到有源晶片的支撑晶片。开口形成在有源晶片中，延伸穿过绝缘材料，并暴露支撑晶片的部分。外延半导体材料在支撑晶片的暴露部分上生长。模拟电路由外延生长的半导体材料制成，高性能逻辑电路由有源晶片制造。用于制造模拟电路的处理步骤与用于制造高性能逻辑电路的步骤分离。从与制造模拟电路的部分电隔离的外延生长的半导体材料的一部分制成衬底接触。

24. 发明授权

US07075155B1 Structure for protecting a semiconductor circuit from electrostatic discharge and a method for forming the structure 有权
标题翻译：用于保护半导体电路免受静电放电的结构和形成该结构的方法
公开(公告)号：US07075155B1
公开(公告)日：2006-07-11
申请号：US10866114
申请日：2004-06-14
申请人： Mario M. Pelella
发明人： Mario M. Pelella
IPC分类号： H01L23/62
CPC分类号： H01L29/7436 , H01L27/0259 , H01L2924/0002 , H01L2924/00
摘要： A structure for protecting a semiconductor circuit from electrostatic discharge is provided. The structure comprises a semiconductor substrate of a first conductivity type having two wells of a second conductivity type spaced laterally apart. The wells each comprise a first portion having a first concentration of an impurity of the second conductivity type and a second portion comprising source and drain regions having a second concentration of an impurity of the second conductivity type. The second concentration is greater than the first concentration. The wells are implanted in the substrate of a silicon-on-insulator semiconductor device. Conductive plugs extend through the silicon and insulator layers and make electrical contact with the wells, allowing the dissipation of excess current and heat into the semiconductor substrate.
摘要翻译：提供了一种用于保护半导体电路免受静电放电的结构。该结构包括具有第二导电类型的具有间隔开间隔的两个阱的第一导电类型的半导体衬底。每个孔各自包括具有第二导电类型的杂质的第一浓度的第一部分和包含具有第二导电类型的杂质的第二浓度的源区和漏区的第二部分。第二浓度大于第一浓度。将阱注入到绝缘体上硅半导体器件的衬底中。导电插头延伸穿过硅和绝缘体层，并与阱电接触，从而将过剩的电流和热量散发到半导体衬底中。

25. 发明授权

US06700430B1 Method to reduce time to dynamic steady-state condition 失效
标题翻译：减少时间到动态稳态条件的方法
公开(公告)号：US06700430B1
公开(公告)日：2004-03-02
申请号：US10188173
申请日：2002-08-20
申请人： Mario M. Pelella , Srikanth Sundararajan
发明人： Mario M. Pelella , Srikanth Sundararajan
IPC分类号： H03K1704
CPC分类号： H01L27/1203 , H01L29/78612 , H03K3/012
摘要： A method for reducing the time for a partially depleted/silicon-on-insulator (PD/SOI) based circuit to reach a dynamic steady state pre-conditions the PD/SOI-based circuit by initially charging the circuit at a voltage greater than the normal operating voltage. The circuit is then charged at the normal operating voltage after a predetermined amount of time. By pre-conditioning the circuit in this manner, the amount of time required for the PD/SOI transistors of the circuit to reach their dynamic steady state (DSS) condition is shortened.
摘要翻译：一种减少部分耗尽/绝缘体上（基于硅）的电路达到动态稳态的时间的方法通过以大于该电压的电压对电路进行初始充电来预先调节基于PD / SOI的电路正常工作电压。然后在预定时间量之后，在正常工作电压下对电路进行充电。通过以这种方式对电路进行预调节，电路的PD / SOI晶体管达到其动态稳态（DSS）条件所需的时间被缩短。

26. 发明授权

US06642119B1 Silicide MOSFET architecture and method of manufacture 有权
标题翻译：硅化物MOSFET结构及其制造方法
公开(公告)号：US06642119B1
公开(公告)日：2003-11-04
申请号：US10215171
申请日：2002-08-08
申请人： Mario M. Pelella , Shankar Sinha , Simon S. Chan
发明人： Mario M. Pelella , Shankar Sinha , Simon S. Chan
IPC分类号： H01L21336
CPC分类号： H01L29/66507 , H01L21/84 , H01L27/1203 , H01L29/458 , H01L29/66757 , H01L29/78612 , H01L29/78621 , Y10S438/952
摘要： The present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance and reduces the floating-body-effect when employed in conjunction with SOI type device architecture.
摘要翻译：本发明涉及一种形成晶体管和晶体管结构的方法。本发明包括使用双硅化物工艺来形成晶体管，当与SOI型器件结构结合使用时，其降低电阻并降低浮体效应。

27. 发明授权

US06323522B1 Silicon on insulator thick oxide structure and process of manufacture 有权
标题翻译：硅绝缘体厚氧化物结构及制造工艺
公开(公告)号：US06323522B1
公开(公告)日：2001-11-27
申请号：US09227695
申请日：1999-01-08
申请人： Michael J. Hargrove , Mario M. Pelella , Steven H. Voldman
发明人： Michael J. Hargrove , Mario M. Pelella , Steven H. Voldman
IPC分类号： H01L2900
CPC分类号： H01L27/1203 , H01L27/0266 , H01L29/4908 , H01L29/78615 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： A SOI field effect transistor structure providing ESD protection. The structure has a source, a drain, a body, and a gate. The gate is formed from a thick oxide layer and a metal contact. The gate is formed during the BEOL process. The transistor may be a p-type transistor or an n-type transistor. The transistor may have its drain tied to either the gate, the body, or both the gate and body. When used as a protection device, the drain is tied to a signal pad and the source is tied to a potential reference.
摘要翻译：提供ESD保护的SOI场效应晶体管结构。该结构具有源，漏，体和门。栅极由厚的氧化物层和金属接触形成。门在BEOL过程中形成。晶体管可以是p型晶体管或n型晶体管。晶体管可以将其漏极连接到栅极，主体或栅极和主体两者。当用作保护装置时，漏极连接到信号焊盘，源极连接到潜在的参考电压。

28. 发明授权

US07741164B2 Method for fabricating SOI device 有权
标题翻译：制造SOI器件的方法
公开(公告)号：US07741164B2
公开(公告)日：2010-06-22
申请号：US12033060
申请日：2008-02-19
申请人： Mario M. Pelella
发明人： Mario M. Pelella
IPC分类号： H01L21/84
CPC分类号： H01L21/823481 , H01L21/28123 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/66128 , H01L29/8611
摘要： A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer. A well region is ion implanted in the monocrystalline silicon substrate. A gate electrode material is deposited overlying the monocrystalline silicon layer. The gate electrode material is photolithographically patterned and etched using a minimum lithography feature size to form a first gate electrode, a second gate electrode and a spacer having the minimum lithography feature size. The gate electrode material is then isotropically etched to reduce the width of the first gate electrode, the second gate electrode and the spacer.
摘要翻译：提供了一种用于制造绝缘体上半导体（SOI）器件的方法。在一个实施例中，该方法包括提供具有单晶硅层的单晶硅衬底，该单晶硅层覆盖单晶硅衬底，并通过电介质层与其分离。在单晶硅衬底中离子注入阱区。沉积在单晶硅层上的栅电极材料。使用最小光刻特征尺寸对光栅图案化和蚀刻栅电极材料以形成具有最小光刻特征尺寸的第一栅电极，第二栅电极和间隔物。然后各向同性蚀刻栅电极材料，以减小第一栅电极，第二栅电极和间隔物的宽度。

29. 发明申请

US20090073758A1 SRAM CELLS WITH ASYMMETRIC FLOATING-BODY PASS-GATE TRANSISTORS 审中-公开
标题翻译：具有不对称浮动体态栅极晶体管的SRAM电池
公开(公告)号：US20090073758A1
公开(公告)日：2009-03-19
申请号：US11857757
申请日：2007-09-19
申请人： Gregory G. Freeman , Qingqing Liang , Mario M. Pelella , Carl J. Radens , Huicai Zhong , Huilong Zhu
发明人： Gregory G. Freeman , Qingqing Liang , Mario M. Pelella , Carl J. Radens , Huicai Zhong , Huilong Zhu
IPC分类号： G11C11/34 , H01L21/00
CPC分类号： G11C11/412
摘要： The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate transistor, and a second pass-gate transistor. The first pass-gate transistor is connected to a first side of the SRAM cell, wherein the first pass-gate transistor comprises a first drain region and a first source region. The second pass-gate transistor is connected to a second side of the SRAM cell, wherein the second side is opposite the first side. The second pass-gate transistor comprises a second source region and a second drain region. Furthermore, the first source region and/or the second source region comprise a xenon implant. The first drain region and the second drain region each lack a xenon implant.
摘要翻译：本发明的实施例提供具有非对称浮体通过栅极晶体管的SRAM单元。更具体地，半导体器件包括SRAM单元，第一通过栅极晶体管和第二通过栅极晶体管。第一栅极晶体管连接到SRAM单元的第一侧，其中第一栅极晶体管包括第一漏极区域和第一源极区域。第二通栅晶体管连接到SRAM单元的第二侧，其中第二侧与第一侧相对。第二通栅晶体管包括第二源区和第二漏区。此外，第一源区和/或第二源区包括氙植入物。第一漏区和第二漏区各自缺少氙植入物。

30. 发明授权

US07494885B1 Disposable spacer process for field effect transistor fabrication 有权
标题翻译：场效应晶体管制造的一次性间隔工艺
公开(公告)号：US07494885B1
公开(公告)日：2009-02-24
申请号：US10818155
申请日：2004-04-05
申请人： Mario M. Pelella , Darin A. Chan , Kei-Leong Ho , Lu You
发明人： Mario M. Pelella , Darin A. Chan , Kei-Leong Ho , Lu You
IPC分类号： H01L21/00
CPC分类号： H01L29/6659 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/7833
摘要： According to one exemplary embodiment, a method for forming a field effect transistor on a substrate comprises a step of forming disposable spacers adjacent to a gate stack situated on the substrate, where the disposable spacers comprise amorphous carbon. The disposable spacers can be formed by depositing a layer of amorphous carbon on the gate stack and anisotropically etching the layer of amorphous carbon. The method further comprises forming source and drain regions in the substrate, where the source and drain regions are situated adjacent to the disposable spacers. According to this exemplary embodiment, the method further comprises removing the disposable spacers, where the removal of the disposable spacers causes substantially no gouging in the substrate. The disposable spacers can be removed by using a dry etch process. The method can further comprise forming extension regions in the substrate adjacent to the gate stack prior to forming the disposable spacers.
摘要翻译：根据一个示例性实施例，用于在衬底上形成场效应晶体管的方法包括形成邻近位于衬底上的栅极堆叠的一次性间隔物的步骤，其中一次性间隔物包括无定形碳。可以通过在栅极堆叠上沉积无定形碳层并且各向异性地蚀刻无定形碳层来形成一次性间隔物。该方法还包括在衬底中形成源极和漏极区域，其中源极区域和漏极区域邻近一次性间隔物定位。根据该示例性实施例，该方法还包括去除一次性间隔件，其中一次性间隔件的移除基本上不引起基板中的气刨。可以通过使用干法蚀刻工艺去除一次性间隔物。该方法还可以包括在形成一次性间隔件之前在邻近栅极堆叠的基板中形成延伸区域。

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