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21. 发明授权

US06512252B1 Semiconductor device 有权
公开(公告)号：US06512252B1
公开(公告)日：2003-01-28
申请号：US09712223
申请日：2000-11-15
申请人： Takeshi Takagi , Akira Inoue
发明人： Takeshi Takagi , Akira Inoue
IPC分类号： H01L31072
CPC分类号： H01L29/1054 , H01L21/84 , H01L27/1203 , H01L29/161 , H01L29/165 , H01L29/7782 , H01L29/783 , H01L29/78615 , H01L29/78648 , H01L29/78687
摘要： A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high concentration Si body region, an n− Si region, a SiGe channel region containing n-type low concentration impurities, an n-type low concentration Si cap layer, and a contact which is a conductor member for electrically connecting the gate electrode and the Si body region. The present invention extends the operation range while keeping the threshold voltage small by using, for the channel layer, a material having a smaller potential at the band edge where carriers travel than that of a material constituting the body region.

22. 发明授权

US07205586B2 Semiconductor device having SiGe channel region 有权
标题翻译：具有SiGe沟道区的半导体器件
公开(公告)号：US07205586B2
公开(公告)日：2007-04-17
申请号：US10851073
申请日：2004-05-24
申请人： Takeshi Takagi , Akira Inoue
发明人： Takeshi Takagi , Akira Inoue
IPC分类号： H01L31/072
CPC分类号： H01L29/1054 , H01L21/84 , H01L27/1203 , H01L29/161 , H01L29/165 , H01L29/7782 , H01L29/783 , H01L29/78615 , H01L29/78648 , H01L29/78687
摘要： A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high concentration Si body region, an n− Si region, a SiGe channel region containing n-type low concentration impurities, an n-type low concentration Si cap layer, and a contact which is a conductor member for electrically connecting the gate electrode and the Si body region. The present invention extends the operation range while keeping the threshold voltage small by using, for the channel layer, a material having a smaller potential at the band edge where carriers travel than that of a material constituting the body region.
摘要翻译： HDTMOS包括Si衬底，掩埋氧化物膜和半导体层。半导体层包括上硅膜，外延生长的Si缓冲层，外延生长的SiGe膜和外延生长的Si膜。此外，HDTMOS包括n型高浓度Si体区域，n + Si区域，含有n型低浓度杂质的SiGe沟道区域，n型低浓度Si覆盖层，以及作为用于电连接栅电极和Si体区的导体构件的接触。本发明通过在沟道层使用载流子行进的带边缘处的电位较小的材料，而不是构成体区的材料的情况下，使阈值电压保持较小。

23. 发明授权

US06781163B2 Heterojunction field effect transistor 有权
标题翻译：异质结场效应晶体管
公开(公告)号：US06781163B2
公开(公告)日：2004-08-24
申请号：US10311293
申请日：2002-12-17
申请人： Takeshi Takagi , Akira Inoue
发明人： Takeshi Takagi , Akira Inoue
IPC分类号： H01L310328
CPC分类号： H01L29/802 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/78687
摘要： A region of an Si layer (15) located between source and drain regions (19 and 20) is an Si body region (21) which contains an n-type impurity of high concentration. An Si layer (16) and an SiGe layer (17) are, in an as grown state, undoped layers into which no n-type impurity is doped. Regions of the Si layer 16 and the SiGe layer (17) located between the source and drain regions (19 and 20) are an Si buffer region (22) and an SiGe channel region (23), respectively, which contain the n-type impurity of low concentration. A region of an Si film (18) located directly under a gate insulating film (12) is an Si cap region (24) into which a p-type impurity (5×1017 atoms·cm−3) is doped. Accordingly, a semiconductor device in which an increase in threshold voltage is suppressed can be achieved.
摘要翻译：位于源极和漏极区域（19和20）之间的Si层（15）的区域是包含高浓度的n型杂质的Si体区域（21）。处于生长状态的Si层（16）和SiGe层（17）是未掺杂n型杂质的未掺杂层。位于源极和漏极区域（19和20）之间的Si层16和SiGe层（17）的区域分别是包含n型的Si缓冲区（22）和SiGe沟道区（23）低浓度的杂质。位于栅极绝缘膜（12）正下方的Si膜（18）的区域是掺杂有p型杂质（5×10 17原子·cm -3）的Si帽区域（24）。因此，可以实现抑制阈值电压增加的半导体装置。

24. 发明授权

US07554139B2 Semiconductor manufacturing method and semiconductor device 失效
标题翻译：半导体制造方法和半导体器件
公开(公告)号：US07554139B2
公开(公告)日：2009-06-30
申请号：US11568404
申请日：2005-04-11
申请人： Akira Inoue , Haruyuki Sorada , Yoshio Kawashima , Takeshi Takagi
发明人： Akira Inoue , Haruyuki Sorada , Yoshio Kawashima , Takeshi Takagi
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/76229 , H01L21/823412 , H01L21/823481 , H01L27/0207 , H01L27/088
摘要： A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitioning the principal face into a plurality of device active regions 50, 60; step (B) of growing an epitaxial layer containing Si and Ge on selected device active regions 50 among the plurality of device active regions 50, 60 of the principal face of the semiconductor layer; and step (C) of forming a transistor in, among the plurality of device active regions 50, 60, each of the device active regions 50 on which the epitaxial layer is formed and each of the device active regions A2 on which the epitaxial layer is not formed. Step (A) includes step (a1) of forming, in the isolation region 70, a plurality of dummy regions 80 surrounded by the device isolation structure (STI), and step (B) includes step (b1) of growing a layer of the same material as that of the epitaxial layer on selected regions among the plurality of dummy regions 80.
摘要翻译：根据本发明的半导体器件的制造方法包括：步骤（A），其提供包括具有主面的半导体层的衬底，所述衬底具有形成在隔离区域70中的器件隔离结构（STI），用于分割主面进入多个设备有源区域50,60; 在半导体层的主面的多个器件有源区50,60中的选定器件有源区50上生长含有Si和Ge的外延层的工序（B）以及在多个器件有源区域50,60之间形成晶体管的步骤（C），在其上形成有外延层的器件有源区域50中的每一个，外延层上的每个器件有源区域A2 没有形成。步骤（A）包括在隔离区域70中形成被器件隔离结构（STI）包围的多个虚拟区域80的步骤（a1），步骤（B）包括步骤（b1）与多个虚拟区域80中的选定区域上的外延层相同的材料。

25. 发明申请

US20090002084A1 Oscillator 审中-公开
标题翻译：振荡器
公开(公告)号：US20090002084A1
公开(公告)日：2009-01-01
申请号：US11658615
申请日：2005-07-13
申请人： Akira Inoue , Kouji Katayama , Takeshi Takagi
发明人： Akira Inoue , Kouji Katayama , Takeshi Takagi
IPC分类号： H03B5/12
CPC分类号： H01L27/088 , H01L27/0617 , H01L27/092 , H03B5/1203 , H03B5/1215 , H03B5/1228 , H03K3/0315 , H03K3/0322 , H03K3/354
摘要： In an oscillator of the present invention, each of field-effect transistors (12) and (13) contained as amplifier elements is a buried-channel transistor including: a body region formed on a semiconductor substrate, a source region and a drain region formed on the body region and having a different conductivity type from that of the body region, a buried channel layer formed between the source region and the drain region, and a gate electrode formed above the buried channel layer with a gate insulating film interposed therebetween, wherein body terminals (b12) and (b13) electrically connected to the body region are connected to a power supply wire to which a power supply potential (Vdd) is applied.
摘要翻译：在本发明的振荡器中，包含作为放大器元件的场效应晶体管（12）和（13）中的每一个是埋入沟道晶体管，其包括：形成在半导体衬底上的体区，形成源区和漏区在体区域具有与体区不同的导电类型，形成在源极区域和漏极区域之间的掩埋沟道层，以及在掩埋沟道层上方形成有栅极绝缘膜的栅电极，其中，电连接到主体区域的主体端子（b12）和（b13）连接到施加电源电位（Vdd）的电源线。

26. 发明申请

US20080135877A1 Semiconductor Manufacturing Method and Semiconductor Device 失效
标题翻译：半导体制造方法和半导体器件
公开(公告)号：US20080135877A1
公开(公告)日：2008-06-12
申请号：US11568404
申请日：2005-04-11
申请人： Akira Inoue , Haruyuki Sorada , Yoshio Kawashima , Takeshi Takagi
发明人： Akira Inoue , Haruyuki Sorada , Yoshio Kawashima , Takeshi Takagi
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/76229 , H01L21/823412 , H01L21/823481 , H01L27/0207 , H01L27/088
摘要： A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitioning the principal face into a plurality of device active regions 50, 60; step (B) of growing an epitaxial layer containing Si and Ge on selected device active regions 50 among the plurality of device active regions 50, 60 of the principal face of the semiconductor layer; and step (C) of forming a transistor in, among the plurality of device active regions 50, 60, each of the device active regions 50 on which the epitaxial layer is formed and each of the device active regions A2 on which the epitaxial layer is not formed. Step (A) includes step (a1) of forming, in the isolation region 70, a plurality of dummy regions 80 surrounded by the device isolation structure (STI), and step (B) includes step (b1) of growing a layer of the same material as that of the epitaxial layer on selected regions among the plurality of dummy regions 80.
摘要翻译：根据本发明的半导体器件的制造方法包括：步骤（A），其提供包括具有主面的半导体层的衬底，所述衬底具有形成在隔离区域70中的器件隔离结构（STI），用于分割主面进入多个设备有源区域50,60; 在半导体层的主面的多个器件有源区50,60中的选定器件有源区50上生长含有Si和Ge的外延层的工序（B）以及在多个器件有源区域50,60中形成晶体管的步骤（C），在其上形成有外延层的器件有源区域50中的每个器件有源区域A 2上，其上的外延层没有形成。步骤（A）包括在隔离区域70中形成被器件隔离结构（STI）包围的多个虚拟区域80的步骤（a1），步骤（B）包括步骤（b1）与多个虚拟区域80中的选定区域上的外延层相同的材料。

27. 发明授权

US07126170B2 MISFET for reducing leakage current 失效
标题翻译：用于减少漏电流的MISFET
公开(公告)号：US07126170B2
公开(公告)日：2006-10-24
申请号：US10978513
申请日：2004-11-02
申请人： Akira Inoue , Takeshi Takagi , Akira Asai , Haruyuki Sorada
发明人： Akira Inoue , Takeshi Takagi , Akira Asai , Haruyuki Sorada
IPC分类号： H01L31/0336
CPC分类号： H01L21/28123 , H01L29/1054 , H01L29/1087 , H01L29/4238 , H01L29/66651 , H01L29/783
摘要： A MISFET according to this invention includes: a substrate having a semiconductor layer; an active region formed in the semiconductor layer; a gate insulator formed on the active region; a gate formed on the gate insulator; and a source region and a drain region, wherein: the active region is formed, in plan view, to have a body portion and a projecting portion projecting from a periphery of the body portion; the gate is formed, in plan view, to intersect the body portion of the active region, cover a pair of connecting portions connecting a periphery of the projecting portion to the periphery of the body portion and allow a part of the projecting portion to project from a periphery of the gate; and the source region and the drain region are formed in regions of the body portion of the active region which are situated on opposite sides of the gate in plan view, respectively.
摘要翻译：根据本发明的MISFET包括：具有半导体层的衬底; 形成在半导体层中的有源区; 形成在有源区上的栅极绝缘体; 形成在栅极绝缘体上的栅极; 源极区域和漏极区域，其中：有源区域在平面图中形成为具有从主体部分的周边突出的主体部分和突出部分; 在平面图中，门形成为与有源区域的主体部分相交，覆盖将突出部分的周边连接到主体部分的周边的一对连接部分，并使突出部分的一部分从门的周边; 并且源极区域和漏极区域分别形成在有源区域的主体部分的位于平面图的栅极的相对侧上的区域中。

28. 发明授权

US06987065B2 Method of manufacturing self aligned electrode with field insulation 失效
标题翻译：制造具有场绝缘的自对准电极的方法
公开(公告)号：US06987065B2
公开(公告)日：2006-01-17
申请号：US10891038
申请日：2004-07-15
申请人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Akira Inoue
发明人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Akira Inoue
IPC分类号： H01L21/311
CPC分类号： H01L29/78696 , H01L21/76264 , H01L21/76281 , H01L29/1054 , H01L29/66742 , H01L29/78687 , Y10S438/933 , Y10S438/938
摘要： The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.
摘要翻译：本发明提供一种半导体器件，包括：半导体层（3）; 经由栅极绝缘膜（10）形成在所述半导体层（3）上的栅电极（11）; 以及形成在所述半导体层（3），所述栅极绝缘膜（10）和所述栅电极（11）的侧壁的一个或多个的第一绝缘膜（13）。其中所述第一绝缘膜（13）覆盖所述栅极绝缘膜（10）表面的一部分。根据半导体装置，可以抑制隔离边缘处的漏电流，从而可以提高可靠性。

29. 发明申请

US20070108514A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070108514A1
公开(公告)日：2007-05-17
申请号：US10554860
申请日：2004-04-28
申请人： Akira Inoue , Takeshi Takagi , Haruyuki Sorada
发明人： Akira Inoue , Takeshi Takagi , Haruyuki Sorada
IPC分类号： H01L29/94
CPC分类号： H01L29/7834 , H01L29/66545 , H01L29/66553 , H01L29/66621 , H01L29/66772 , H01L29/78621
摘要： A semiconductor device according to the present invention, which comprises a MISFET, has a semiconductor layer (3) having a recessed portion (101) formed in the surface thereof, the recessed portion (101) having an opening the outer circumference of which is closed, a gate insulating film (13) formed so as to cover at least the inner face of the recessed portion (3), a gate electrode (14) filling the recessed portion (101) such that the gate insulating film (13) is interposed between the gate electrode (14) and the inner face of the recessed portion (101), and a pair of source/drains (102), located on both sides of the gate electrode (14) when viewed in plan and formed to a predetermined depth from the surface of the semiconductor layer (3).
摘要翻译：根据本发明的包括MISFET的半导体器件具有在其表面形成有凹部（101）的半导体层（3），所述凹部（101）的外周封闭的开口部形成为至少覆盖所述凹部（3）的内面的栅极绝缘膜（13），填充所述凹部（101）的栅极电极（14），使得所述栅极绝缘膜（13）插入在栅极电极（14）和凹部（101）的内表面之间，以及一对源极/漏极（102），位于栅极电极（14）的两侧，当从平面观察时形成预定的从半导体层（3）的表面的深度。

30. 发明授权

US07119417B2 Semiconductor device and fabrication method thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07119417B2
公开(公告)日：2006-10-10
申请号：US10948747
申请日：2004-09-24
申请人： Haruyuki Sorada , Takeshi Takagi , Akira Inoue , Yoshio Kawashima
发明人： Haruyuki Sorada , Takeshi Takagi , Akira Inoue , Yoshio Kawashima
IPC分类号： H01L31/117
CPC分类号： H01L29/66636 , H01L21/28202 , H01L29/1054 , H01L29/518 , H01L29/665 , H01L29/7833 , H01L29/7842
摘要： A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode in a plan view; and a germanium-containing channel layer situated below the gate electrode to sandwich an gate insulator therebetween and intervening between the pair of source and drain electrodes, wherein a silicide layer forming at least a part of the source and drain electrodes has a lower germanium concentration than the channel layer.
摘要翻译：本发明的半导体器件包括：半导体衬底; 形成在所述半导体衬底上的栅电极; 在平面图中分别形成在位于栅电极的相对侧的半导体衬底的区域中的一对源极和漏极; 以及位于栅极电极下方的含锗沟道层，以夹持栅极绝缘体，并且介于所述一对源极和漏极之间，其中形成所述源极和漏极的至少一部分的硅化物层的锗浓度低于通道层。

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