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21. 发明授权

US06937001B2 Circuit for generating a reference voltage having low temperature dependency 失效
标题翻译：用于产生具有低温度依赖性的参考电压的电路
公开(公告)号：US06937001B2
公开(公告)日：2005-08-30
申请号：US10492418
申请日：2003-02-26
申请人： Yoshinori Ueda
发明人： Yoshinori Ueda
IPC分类号： G11C11/413 , G05F1/56 , G05F3/30 , H01L21/822 , H01L27/04 , H03F1/30 , G05F3/16
CPC分类号： G05F3/30 , Y10S323/907
摘要： A circuit for generating a reference voltage includes a bandgap reference circuit that exhibits low temperature dependency of the output reference voltage. Since temperature dependencies of resistances thereof are appropriately controlled so that the temperature dependency of a load current flowing through divisional resistances is eliminated, it is possible to prevent the linearity of temperature dependency of the forward direction voltages of diodes from degrading. Accordingly, the temperature dependency of output is reduced.
摘要翻译：用于产生参考电压的电路包括具有低的输出参考电压的温度依赖性的带隙基准电路。由于其电阻的温度依赖性被适当地控制，从而消除了流过分电阻的负载电流的温度依赖性，可以防止二极管的正向电压的温度依赖性的线性降低。因此，输出的温度依赖性降低。

22. 发明授权

US06917081B2 Semiconductor integrated device 有权
标题翻译：半导体集成器件
公开(公告)号：US06917081B2
公开(公告)日：2005-07-12
申请号：US10422786
申请日：2003-04-25
申请人： Naohiro Ueda , Yoshinori Ueda
发明人： Naohiro Ueda , Yoshinori Ueda
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/76
CPC分类号： H01L21/823857 , H01L21/823892 , H01L27/0922 , H01L27/0928
摘要： A semiconductor device is provided comprising several device components formed in the same substrate, such as a P-substrate having an offset Nch transistor including N-type source and drain each formed in a P-well spatially separated from one another, and the drain surrounded by a low concentration N-type diffusion layer; an offset Pch transistor including P-type source and drain each formed in an N-well spatially separated from one another, and the drain surrounded by a low concentration P-type diffusion layer; a triple well including a deep N-well, and a P-type IP well formed therein; a normal N-well for forming a Pch MOS transistor; and a normal P-well for forming an Nch MOS transistor; in which simultaneously formed are the low concentration N-type diffusion layer, N-well and normal N-well; the P-well and normal P-well; and the low concentration P-type diffusion layer and IP well.
摘要翻译：提供了一种半导体器件，其包括形成在同一衬底中的若干器件组件，例如具有偏置N沟道晶体管的P衬底，其中N型晶体管包括N型源极和漏极，其各自形成在彼此空间上分离的P阱中，并且漏极包围通过低浓度N型扩散层; 偏移Pch晶体管，包括P型源极和漏极，各自形成在空间上彼此分离的N阱中，并且由低浓度P型扩散层包围的漏极; 包括深N阱的三阱和在其中形成的P型IP阱; 用于形成Pch MOS晶体管的正常N阱; 以及用于形成Nch MOS晶体管的正常P阱; 其中同时形成低浓度N型扩散层，N阱和正常N阱; P井和正常P井; 和低浓度P型扩散层和IP井。

23. 发明申请

US20050079280A1 Electroless copper plating solution, electroless copper plating process and production process of circuit board 失效
标题翻译：化学镀铜液，化学镀铜工艺及电路板生产工艺
公开(公告)号：US20050079280A1
公开(公告)日：2005-04-14
申请号：US10898282
申请日：2004-07-26
申请人： Takeyuki Itabashi , Hiroshi Kanemoto , Haruo Akahoshi , Eiji Takai , Naoki Nishimura , Tadashi Iida , Yoshinori Ueda
发明人： Takeyuki Itabashi , Hiroshi Kanemoto , Haruo Akahoshi , Eiji Takai , Naoki Nishimura , Tadashi Iida , Yoshinori Ueda
IPC分类号： C23C18/40 , C23C28/02 , C25D7/00 , H05K3/18 , C23C16/00
CPC分类号： C23C18/1803 , C23C18/1653 , C23C18/40
摘要： An electroless copper plating solution using glyoxylic acid as a reducing agent, which is small in the reacting quantity of Cannizzaro reaction, does not largely cause precipitation of the salt accumulated in the electroless copper plating solution by the plating reaction and Cannizzaro reaction, and can be used stably over a long period of time. The electroless copper plating solution comprises copper ion, a complexing agent for copper ion, a reducing agent for copper ion and a pH adjusting agent, wherein the reducing agent for copper ion is glyoxylic acid or a salt thereof, the pH adjusting agent is potassium hydroxide and the electroless copper plating solution contains at least one member selected from metasilicic acid, metasilicic acid salt, germanium dioxide, germanic acid salt, phosphoric acid, phosphoric acid salt, vanadic acid, vanadic acid salt, stannic acid and stannic acid salt in an amount of 0.0001 mol/L or more.
摘要翻译：使用乙醛酸作为还原剂的化学镀铜溶液，其在Cannizzaro反应的反应量较小时，不会通过电镀反应和Cannizzaro反应极大地引起积存在无电镀铜溶液中的盐的沉淀，并且可以长时间稳定使用。无电镀铜液包括铜离子，铜离子络合剂，铜离子还原剂和pH调节剂，其中铜离子还原剂为乙醛酸或其盐，pH调节剂为氢氧化钾化学镀铜溶液含有选自硅酸，偏硅酸盐，二氧化锗，锗酸盐，磷酸，磷酸盐，钒酸，钒酸盐，锡酸和锡酸盐中的至少一种，为0.0001mol / L以上。

24. 发明授权

US06805915B2 Electroless copper plating solution, electroless copper plating process and production process of circuit board 失效
标题翻译：化学镀铜液，化学镀铜工艺及电路板生产工艺
公开(公告)号：US06805915B2
公开(公告)日：2004-10-19
申请号：US10076536
申请日：2002-02-19
申请人： Takeyuki Itabashi , Hiroshi Kanemoto , Haruo Akahoshi , Eiji Takai , Naoki Nishimura , Tadashi Iida , Yoshinori Ueda
发明人： Takeyuki Itabashi , Hiroshi Kanemoto , Haruo Akahoshi , Eiji Takai , Naoki Nishimura , Tadashi Iida , Yoshinori Ueda
IPC分类号： B05D118
CPC分类号： C23C18/1803 , C23C18/1653 , C23C18/40
摘要： An electroless copper plating solution using glyoxylic acid as a reducing agent, which is small in the reacting quantity of Cannizzaro reaction, does not largely cause precipitation of the salt accumulated in the electroless copper plating solution by the plating reaction and Cannizzaro reaction, and can be used stably over a long period of time. The electroless copper plating solution comprises copper ion, a complexing agent for copper ion, a reducing agent for copper ion and a pH adjusting agent, wherein the reducing agent for copper ion is glyoxylic acid or a salt thereof, the pH adjusting agent is potassium hydroxide and the electroless copper plating solution contains at least one member selected from metasilicic acid, metasilicic acid salt, germanium dioxide, germanic acid salt, phosphoric acid, phosphoric acid salt, vanadic acid, vanadic acid salt, stannic acid and stannic acid salt in an amount of 0.0001 mol/L or more.
摘要翻译：使用乙醛酸作为还原剂的化学镀铜溶液，其在Cannizzaro反应的反应量较小时，不会通过电镀反应和Cannizzaro反应极大地引起积存在无电镀铜溶液中的盐的沉淀，并且可以长时间稳定使用。无电镀铜液包括铜离子，铜离子络合剂，铜离子还原剂和pH调节剂，其中铜离子还原剂为乙醛酸或其盐，pH调节剂为氢氧化钾化学镀铜溶液含有选自硅酸，偏硅酸盐，二氧化锗，锗酸盐，磷酸，磷酸盐，钒酸，钒酸盐，锡酸和锡酸盐中的至少一种，为0.0001mol / L以上。

25. 发明授权

US10078010B2 Photoelectric conversion device, image generation device, and method of correcting output of photoelectric conversion device 有权
公开(公告)号：US10078010B2
公开(公告)日：2018-09-18
申请号：US14978172
申请日：2015-12-22
申请人： Katsuhiko Aisu , Hirofumi Watanabe , Takaaki Negoro , Yoshinori Ueda , Yasukazu Nakatani , Kazuhiro Yoneda , Katsuyuki Sakurano
发明人： Katsuhiko Aisu , Hirofumi Watanabe , Takaaki Negoro , Yoshinori Ueda , Yasukazu Nakatani , Kazuhiro Yoneda , Katsuyuki Sakurano
IPC分类号： G01J1/44 , H04N5/361 , H04N5/365 , H04N5/378
CPC分类号： G01J1/44 , G01J2001/444 , G01J2001/4473 , H04N5/361 , H04N5/3655 , H04N5/378
摘要： A photoelectric conversion device includes a pixel cell including a phototransistor, a reference cell including a reference transistor having a temperature characteristic identical to that of the phototransistor and having a fixed electrical state, an analog-to-digital converter that converts an analog output of the pixel cell into a digital output, a correction amount computation unit that computes a correction amount for the digital output of the analog-to-digital converter based on an output of the reference cell and a reference value, and a correction unit that corrects the digital output of the analog-to-digital converter based on the correction amount.

26. 发明授权

US09923019B2 Semiconductor device, manufacturing method thereof and imaging apparatus 有权
公开(公告)号：US09923019B2
公开(公告)日：2018-03-20
申请号：US14935973
申请日：2015-11-09
申请人： Takaaki Negoro , Yoshinori Ueda , Katsuyuki Sakurano , Yasukazu Nakatani , Kazuhiro Yoneda , Katsuhiko Aisu
发明人： Takaaki Negoro , Yoshinori Ueda , Katsuyuki Sakurano , Yasukazu Nakatani , Kazuhiro Yoneda , Katsuhiko Aisu
IPC分类号： H01L31/0224 , H04N5/378 , H04N5/361 , H01L31/0352 , H01L31/18 , H01L27/146
CPC分类号： H01L27/14681 , H01L27/14612
摘要： A semiconductor device for converting incident light into an electric current includes a semiconductor substrate; an electrode embedded in the semiconductor substrate; an insulation film contacting the electrode in the semiconductor substrate; a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and a third semiconductor region of the first conductivity type, formed sequentially in a depth direction from a side of a front face of the semiconductor substrate; and a fourth semiconductor region of the second conductivity type contacting the insulation film and the second semiconductor region. An impurity concentration of the fourth semiconductor region is greater than an impurity concentration of the second semiconductor region.

27. 发明授权

US07151038B2 Semiconductor device having an integral resistance element 有权
标题翻译：具有积分电阻元件的半导体器件
公开(公告)号：US07151038B2
公开(公告)日：2006-12-19
申请号：US11059818
申请日：2005-02-17
申请人： Yoshinori Ueda
发明人： Yoshinori Ueda
IPC分类号： H01L21/20
CPC分类号： H01L27/0802
摘要： A resistance element of a semiconductor device includes a first resistance pattern and a second resistance pattern formed adjacent to the first resistance pattern at a lower level, wherein the second resistance pattern is defined by the first resistance pattern in a self-aligned relationship and connected to the first resistance pattern in series.
摘要翻译：半导体器件的电阻元件包括在较低电平下与第一电阻图形相邻形成的第一电阻图案和第二电阻图案，其中第二电阻图案由第一电阻图案以自对准关系定义并连接到第一个电阻模式串联。

28. 发明申请

US20050221551A1 Method of forming semiconductor integrated device 有权
标题翻译：形成半导体集成器件的方法
公开(公告)号：US20050221551A1
公开(公告)日：2005-10-06
申请号：US11134386
申请日：2005-05-23
申请人： Naohiro Ueda , Yoshinori Ueda
发明人： Naohiro Ueda , Yoshinori Ueda
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823857 , H01L21/823892 , H01L27/0922 , H01L27/0928
摘要： A semiconductor device is provided comprising several device components formed in the same substrate, such as a P-substrate having an offset Nch transistor including N-type source and drain each formed in a P-well spatially separated from one another, and the drain surrounded by a low concentration N-type diffusion layer; an offset Pch transistor including P-type source and drain each formed in an N-well spatially separated from one another, and the drain surrounded by a low concentration P-type diffusion layer; a triple well including a deep N-well, and a P-type IP well formed therein; a normal N-well for forming a Pch MOS transistor; and a normal P-well for forming an Nch MOS transistor; in which simultaneously formed are the low concentration N-type diffusion layer, N-well and normal N-well; the P-well and normal P-well; and the low concentration P-type diffusion layer and IP well.
摘要翻译：提供了一种半导体器件，其包括形成在同一衬底中的若干器件组件，例如具有偏置N沟道晶体管的P衬底，其中N型晶体管包括N型源极和漏极，其各自形成在彼此空间上分离的P阱中，并且漏极包围通过低浓度N型扩散层; 偏移Pch晶体管，包括P型源极和漏极，各自形成在空间上彼此分离的N阱中，并且由低浓度P型扩散层包围的漏极; 包括深N阱的三阱和在其中形成的P型IP阱; 用于形成Pch MOS晶体管的正常N阱; 以及用于形成Nch MOS晶体管的正常P阱; 其中同时形成低浓度N型扩散层，N阱和正常N阱; P井和正常P井; 和低浓度P型扩散层和IP井。

29. 发明申请

US20050042366A1 Method of manufacturing a wiring substrate and an electroless copper plating solution for providing interlayer connections 失效
标题翻译：制造布线基板的方法和用于提供层间连接的化学镀铜溶液
公开(公告)号：US20050042366A1
公开(公告)日：2005-02-24
申请号：US10959073
申请日：2004-10-07
申请人： Takeyuki Itabashi , Haruo Akahoshi , Eiji Takai , Naoki Nishimura , Tadashi Iida , Yoshinori Ueda
发明人： Takeyuki Itabashi , Haruo Akahoshi , Eiji Takai , Naoki Nishimura , Tadashi Iida , Yoshinori Ueda
IPC分类号： H05K1/02 , C23C18/38 , C23C18/40 , H05K3/18 , H05K3/42 , H05K3/46 , B05D1/18
CPC分类号： C23C18/40 , H05K3/421 , H05K3/422 , H05K3/426 , H05K3/429 , H05K2201/09518
摘要： A multilayer wiring substrate which is high in connection reliability is provided through process steps of forming more than one opening, such as a via-hole in a dielectric layer laminated on a substrate, and then applying uniform copper plating to a surface portion of the dielectric layer including the opening to thereby form a wiring layer. An electroless copper plating solution with at least one of mandelonitrile and triethyltetramine mixed therein is used to perform the intended electroless copper plating. An alternative process makes use of an electroless copper plating solution with chosen additives or “admixtures” containing at least on of mandelonitrile and triethyltetramine plus eriochrome block T along with at least one of 2,2′-bipyridyl, 1,10-phenanthroline, and 2,9-dimethyl-1,10-phenanthroline
摘要翻译：通过在层叠在基板上的电介质层中形成多个开口（例如通孔），然后对电介质的表面部分施加均匀的镀铜，通过工艺步骤提供连接可靠性高的多层布线基板层，从而形成布线层。使用其中混合有扁桃腈和三乙基四胺中的至少一种的无电镀铜溶液进行预期的无电镀铜。一种替代方法利用含有至少含有扁桃腈和三乙基四胺加色团块T的选择的添加剂或“混合物”的化学镀铜溶液以及至少一种2,2'-联吡啶，1,10-菲咯啉和 2,9-二甲基-1,10-菲咯啉

30. 发明授权

US06552603B2 Voltage reference generation circuit and power source incorporating such circuit 失效
公开(公告)号：US06552603B2
公开(公告)日：2003-04-22
申请号：US09884922
申请日：2001-06-21
申请人： Yoshinori Ueda
发明人： Yoshinori Ueda
IPC分类号： G05F324
CPC分类号： G05F3/24
摘要： A voltage reference generation circuit is disclosed including a voltage reference generating stage and a voltage reference output stage, in which a depletion-mode MOS transistor and an enhancement-mode MOS transistor are connected in series, and the junction formed between these MOS transistors serves as an output terminal for outputting a voltage to be input to the voltage reference output stage. In the output stage, two enhancement-mode MOS transistors having the same channel dopant profile are connected in series between a power source and the ground, the gate of one MOS transistor is connected to the output terminal of the generating stage, the gate and drain of the other MOS transistor are interconnected, and the junction formed between these MOS transistors serves as an output terminal for a voltage reference. In addition, each of the enhancement-mode MOS transistors is provided with a floating gate having a different threshold voltage depending on, the coupling coefficient between the floating gate and a gate, the amount of charge input to the floating gate, the kind of dielectric material included in the gate, or the thickness of a gate oxide layer, which is suitably utilized to supply reference voltages with improved stability to fluctuations in operating temperatures or processing parameters.

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