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21. 发明授权

US06522590B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06522590B2
公开(公告)日：2003-02-18
申请号：US09783109
申请日：2001-02-14
申请人： Yoshinori Matsui , Hiroaki Ikeda
发明人： Yoshinori Matsui , Hiroaki Ikeda
IPC分类号： G11C700
CPC分类号： G11C29/44
摘要： A semiconductor memory device, that uses redundant memory cell clusters sharing one data transfer bus line to perform defect recovery for a plurality of defects, and provides an improved rate of recovery. The semiconductor memory device is formed from a main memory, a sub-memory functioning as cache memory, and a plurality of data transfer bus lines, which are configured so that data can be transferred bi-directionally between said main memory and said sub-memory; and performs defect recovery for defects located in said main memory based on an address signal (sub-memory column selecting signal SYm) for said sub-memory and address signals (main memory row selecting signal DXn and bank selecting signal BS) in said main memory, which correspond to said address.
摘要翻译：一种半导体存储器件，其使用共享一个数据传输总线的冗余存储器单元簇来执行多个缺陷的缺陷恢复，并提供改进的恢复速率。半导体存储器件由主存储器，作为高速缓存存储器起作用的子存储器和多个数据传输总线线路构成，数据传输总线被配置为使得数据可以在所述主存储器和所述子存储器之间双向传输 ; 并且基于用于所述副存储器的地址信号（子存储器列选择信号SYm）和所述主存储器中的地址信号（主存储器行选择信号DXn和存储体选择信号BS）对位于所述主存储器中的缺陷进行缺陷恢复，其对应于所述地址。

22. 发明授权

US06392956B2 Semiconductor memory that enables high speed operation 失效
标题翻译：可实现高速运行的半导体存储器
公开(公告)号：US06392956B2
公开(公告)日：2002-05-21
申请号：US09863322
申请日：2001-05-24
申请人： Yoshinori Matsui , Hiroyuki Yamakoshi
发明人： Yoshinori Matsui , Hiroyuki Yamakoshi
IPC分类号： G11C800
CPC分类号： G11C29/70 , G11C8/12
摘要： A semiconductor memory includes a block selection circuit, a redundancy main word decoder, a word reset circuit, and a word driver circuit. The block selection circuit outputs a block selection signal based on an address signal. The redundancy main word decoder generates a redundancy main word signal in response to the block selection signal. The word reset circuit outputs a word reset signal in response to the redundancy main word signal. The word driver circuit drives one of word lines in response to the word reset signal, a main word signal indicating selection of the word driver circuit, and a word decode signal indicating selection of the one of word lines.
摘要翻译：半导体存储器包括块选择电路，冗余主字解码器，字复位电路和字驱动器电路。块选择电路基于地址信号输出块选择信号。冗余主字解码器响应于块选择信号产生冗余主字信号。字复位电路响应于冗余主字信号输出字复位信号。字驱动器电路响应于字复位信号驱动字线之一，指示字驱动器电路的选择的主字信号和指示字线之一的选择的字解码信号。

23. 发明授权

US06335873B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06335873B1
公开(公告)日：2002-01-01
申请号：US09525226
申请日：2000-03-14
申请人： Masaki Kawaguchi , Takeo Fujii , Yoshinori Matsui , Hiroshi Furuta , Seiichi Hannai
发明人： Masaki Kawaguchi , Takeo Fujii , Yoshinori Matsui , Hiroshi Furuta , Seiichi Hannai
IPC分类号： G11C506
CPC分类号： G11C11/005 , G11C11/4125
摘要： A semiconductor integrated circuit device is configured using a DRAM and an SRAM between which data transfer is performed by way of a data transfer circuit using data transfer bus lines. Herein, the DRAM is divided into at least two DRAM arrays, each of which contains a number of columns each consisting of memory cells. In addition, the columns are arranged in mixture in connection with external I/O terminals respectively in such a way that columns respectively containing memory cells which are simultaneously subjected to read operations within a same cycle are arranged not to adjoin each other. Thus, it is possible to reduce a probability in which multiple memory cells which are simultaneously subjected to read operations within the same cycle exist within a range of an area under influence of charged particles, which are produced locally due to neutrons. Even if data of memory cells which are concentrated at a certain region are simultaneously placed under influence of the charged particles, it is possible to remarkably reduce a number of chances in that multiple bits of data being read out to the external I/O terminals go defective simultaneously.
摘要翻译：半导体集成电路器件使用DRAM和SRAM，其间通过使用数据传输总线的数据传输电路进行数据传输。这里，DRAM被划分为至少两个DRAM阵列，每个DRAM阵列包含多个列，每列由存储器单元组成。此外，这些列分别与外部I / O端子混合地排列，使得分别包含在相同周期内同时进行读取操作的存储单元的列彼此不相邻地布置。因此，可以降低在相同周期内同时进行读取操作的多个存储单元在由于中子而局部产生的带电粒子的影响范围内的可能性。即使集中在特定区域的存储单元的数据同时被放置在带电粒子的影响下，也可以显着地减少读出到外部I / O端子的多个数据位移动的次数同时发生故障。

24. 发明授权

US06307410B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06307410B1
公开(公告)日：2001-10-23
申请号：US09521474
申请日：2000-03-08
申请人： Yoshinori Matsui
发明人： Yoshinori Matsui
IPC分类号： H03L700
CPC分类号： G11C7/222 , G11C7/22
摘要： The semiconductor integrated circuit device of the present invention for accepting an external signal synchronously with an external clock signal, comprises: an internal clock signal circuit for detecting a change in the external clock signal and generating an internal clock signal having a predetermined pulse width; a latch circuit for accepting the external signal in advance and latching the external signal for the period of time corresponding to the predetermined pulse width according to the internal clock signal; and an internal signal generating circuit for generating an internal signal which reflects the logic of the external signal and has the predetermined pulse width, according to the internal clock signal.
摘要翻译：本发明的用于与外部时钟信号同步地接收外部信号的本发明的半导体集成电路装置包括：内部时钟信号电路，用于检测外部时钟信号的变化并产生具有预定脉冲宽度的内部时钟信号; 一个锁存电路，用于根据内部时钟信号提前接收外部信号并锁存对应于预定脉冲宽度的时间段; 以及内部信号发生电路，用于根据内部时钟信号产生反映外部信号的逻辑并具有预定脉冲宽度的内部信号。

25. 发明授权

US5444661A Semiconductor memory device having test circuit 失效
标题翻译：具有测试电路的半导体存储器件
公开(公告)号：US5444661A
公开(公告)日：1995-08-22
申请号：US186142
申请日：1994-01-25
申请人： Yoshinori Matsui
发明人： Yoshinori Matsui
IPC分类号： G11C29/00 , G11C29/26 , G11C29/28 , G11C29/34 , G11C29/38
CPC分类号： G11C29/38 , G11C29/26 , G11C29/28
摘要： A semiconductor memory device is disclosed which has a data output circuit including a first node, a second node, first and second transistors connected in series between the first node and a potential line, third and fourth transistors connected in series between the first node and the potential line, fifth and sixth transistors connected in series between the second node and the potential line, seventh and eighth transistors connected in series between the second node and the potential-line, one of the first and third transistors being driven in response to a data signal read from a selected memory cell and one of the fifth and seventh transistors being driven in response to an inverted data signal of the data signal in a normal mode while turning one of the second and fourth transistor and one of the sixth and eighth transistors ON, both of the first and third transistors being driven in response to the data signal and both of the fifth and seventh transistors being driven in response to the inverted data signal while all the second, fourth, sixth and eighth transistors ON. The output circuit further includes an output logic circuit driving an output terminal to one of first and second logic levels when the first and second nods have logic levels different from each other and to a high impedance when the first and second nodes have logic levels equal to each other.
摘要翻译：公开了一种半导体存储器件，其具有包括串联连接在第一节点和电位线之间的第一节点，第二节点，第一和第二晶体管的数据输出电路，串联连接在第一节点和第一节点之间的第三和第四晶体管在第二节点和电位线之间串联连接的电位线，第五和第六晶体管，第七和第八晶体管串联连接在第二节点和电位线之间，第一和第三晶体管之一响应于数据被驱动响应于在正常模式下的数据信号的反相数据信号驱动从所选存储单元读取的信号，并且第五和第七晶体管中的一个被驱动，同时使第二和第四晶体管中的一个和第六和第八晶体管中的一个导通第一晶体管和第三晶体管都响应于数据信号被驱动，第五晶体管和第七晶体管都以响应方式被驱动所有第二，第四，第六和第八晶体管ON。输出电路还包括输出逻辑电路，当第一和第二点具有彼此不同的逻辑电平时，驱动输出端到第一和第二逻辑电平中的一个，当第一和第二节点的逻辑电平等于彼此。

26. 发明授权

US5444305A Semiconductor memory circuit 失效
标题翻译：半导体存储电路
公开(公告)号：US5444305A
公开(公告)日：1995-08-22
申请号：US84017
申请日：1993-06-30
申请人： Yoshinori Matsui
发明人： Yoshinori Matsui
IPC分类号： G11C7/10 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1006 , G11C11/4096
摘要： This semiconductor circuit includes a plurality of memory cell arrays arranged mutually adjacent in one direction, a plurality of first selection/sense amplifier circuits provided in the respective regions between mutually adjacent pairs of these memory cell arrays and make access to one of alternately defined odd-numbered or even-numbered memory cell trains in the order of arrangement, two units of second selection/sense amplifier circuits arranged on the outside of the memory cell arrays on both ends of the arrangement of the plurality of memory cell arrays and make access to one of the designated odd-numbered or even-numbered memory cell trains of the memory cell arrays on both ends, a plurality of data buses corresponding to the respective bits of data transferred in bit parallel between an external circuit, and a plurality of input and output switching circuits arranged and connected in one-to-one correspondence to the respective first and second selection/sense amplifier circuits connected to the plurality of data buses so as to have an equal number of memory cell trains capable of transferring data with these data buses, and a plurality of input and output switching circuits which transfer data with the first and the second selection/sense amplifier circuits in one-to-one correspondence.
摘要翻译：该半导体电路包括在一个方向上相互相邻布置的多个存储单元阵列，多个第一选择/读出放大器电路，设置在相互相邻的这些存储单元阵列对之间的各个区域中，编号或偶数编号的存储单元列，排列在多个存储单元阵列的排列的两端上的存储单元阵列的外部的两个单元的第二选择/读出放大器电路，并且访问一个在两端的存储单元阵列的指定的奇数或偶数号存储单元列中，对应于在外部电路与多个输入和输出之间并行传送的数据的各个位的多个数据总线开关电路与各自的第一和第二选择/读出放大器电路一一对应地布置和连接连接到多个数据总线，以具有能够使用这些数据总线传送数据的相同数目的存储单元列;以及多个输入和输出切换电路，其与第一和第二选择/读出放大器电路一一对应。

27. 发明授权

US5424987A Semiconductor memory device having redundant memory cells and circuit therefor 失效
标题翻译：具有冗余存储单元的半导体存储器件及其电路
公开(公告)号：US5424987A
公开(公告)日：1995-06-13
申请号：US128237
申请日：1993-09-29
申请人： Yoshinori Matsui
发明人： Yoshinori Matsui
IPC分类号： G11C11/401 , G11C11/409 , G11C16/06 , G11C17/00 , G11C29/00 , G11C29/04 , G11C29/34 , G11C7/00
CPC分类号： G11C29/846
摘要： The semiconductor memory device includes at least one pair of redundant digit lines (RD,RDb), first input/output lines (IO,IOb) connected to a pair of digit lines (D,Db) via a respective sense amplifier (SA) and a switch (SW), second input/output lines (IO',IOb')connected to the redundant digit line pair (RD,RDb) via a sense amplifier (RSA) and switch (RSW), and selective amplifier means (IOSW, IOSW', RIOSW, RIOSW') for amplifying second input/output lines when redundant digit lines are selected.With this configuration, even when the redundant digit line pair is substituted for the digit line pair, it is possible to execute the redundancy operation by mere translation between these input/output line pairs.
摘要翻译：半导体存储器件包括至少一对冗余数字线（RD，RDb），经由相应读出放大器（SA）连接到一对数字线（D，Db）的第一输入/输出线（IO，IOb）和通过读出放大器（RSA）和开关（RSW）连接到冗余数字线对（RD，RDb）的开关（SW），第二输入/输出线（IO'，IOb'）和选择放大器装置（IOSW， IOSW'，RIOSW，RIOSW'），用于在选择冗余数字线时放大第二输入/输出线。利用这种配置，即使冗余数字线对代替数字线对，也可以通过这些输入/输出线对之间的平移进行冗余操作。

28. 发明申请

US20130148448A1 MEMORY SYSTEM AND DATA TRANSMISSION METHOD 有权
公开(公告)号：US20130148448A1
公开(公告)日：2013-06-13
申请号：US13764433
申请日：2013-02-11
申请人： Yoshinori Matsui
发明人： Yoshinori Matsui
IPC分类号： G11C7/10 , G11C8/18
CPC分类号： G11C7/1048 , G06F13/4243 , G06F13/4256 , G11C7/10 , G11C8/18 , G11C11/401 , G11C11/4093 , G11C29/028 , G11C29/50012
摘要： A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.

29. 发明授权

US08390338B2 Semiconductor device having signal transfer line 失效
标题翻译：具有信号传输线的半导体器件
公开(公告)号：US08390338B2
公开(公告)日：2013-03-05
申请号：US12909327
申请日：2010-10-21
申请人： Yoshinori Matsui
发明人： Yoshinori Matsui
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K19/0013 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , H03K19/018571
摘要： To include a switch transistor inserted between a data bus and an input end of a signal receiving circuit and turned off when a potential of the data bus reaches VPERI−NVth, and an assist transistor that drives the input end of the signal receiving circuit to have VPERI. According to the present invention, because the switch transistor and the assist transistor assist a receiving operation performed by the signal receiving circuit, amplitude of a transferred signal can be reduced without reducing a transfer rate. With this configuration, power consumed by charging or discharging of the data bus can be reduced.
摘要翻译：为了包括插入在数据总线和信号接收电路的输入端之间的开关晶体管，并且当数据总线的电位达到VPERI-NVth时截止，并且驱动信号接收电路的输入端的辅助晶体管具有 VPERI。根据本发明，由于开关晶体管和辅助晶体管辅助由信号接收电路执行的接收操作，所以可以在不降低传输速率的情况下降低传送信号的幅度。通过这种配置，可以减少数据总线的充电或放电所消耗的功率。

30. 发明申请

US20130019044A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130019044A1
公开(公告)日：2013-01-17
申请号：US13547799
申请日：2012-07-12
申请人： Nakaba KAIWA , Yoshinori MATSUI
发明人： Nakaba KAIWA , Yoshinori MATSUI
IPC分类号： G06F13/40
CPC分类号： G06F13/40 , G06F13/4059
摘要： A semiconductor memory device includes a memory cell array section including a plurality of memory cell arrays, a peripheral circuit section, and an internal bus 4 connecting the plurality of memory cell arrays and the peripheral circuit section. The peripheral circuit section includes a plurality of external input/output buffers 23, and a plurality of bus interface circuits 24. The plurality of bus interface circuits execute conversion between data inputted/outputted in parallel to/from the memory cell arrays through the internal bus and data inputted/outputted in serial through the plurality of external input/output buffers. The plurality of bus interface circuits 24 are densely arranged between the internal bus 4 and the plurality of external input/output buffers, so that a width d1 of the area of the plurality of bus interface circuits being arranged is narrower than a width d2 of the area of the plurality of external input/output buffers being arranged and a bus width maximum value d3 of the internal bus.
摘要翻译：半导体存储器件包括存储单元阵列部分，其包括多个存储单元阵列，外围电路部分和连接多个存储单元阵列和外围电路部分的内部总线4。外围电路部分包括多个外部输入/输出缓冲器23和多个总线接口电路24.多个总线接口电路通过内部总线执行与存储单元阵列并行输入/输出的数据之间的转换以及通过多个外部输入/输出缓冲器串行输入/输出的数据。多个总线接口电路24密集地布置在内部总线4和多个外部输入/输出缓冲器之间，使得布置的多个总线接口电路的区域的宽度d1比宽度d2窄布置多个外部输入/输出缓冲器的区域和内部总线的总线宽度最大值d3。

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