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1. 发明授权

US06335873B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06335873B1
公开(公告)日：2002-01-01
申请号：US09525226
申请日：2000-03-14
申请人： Masaki Kawaguchi , Takeo Fujii , Yoshinori Matsui , Hiroshi Furuta , Seiichi Hannai
发明人： Masaki Kawaguchi , Takeo Fujii , Yoshinori Matsui , Hiroshi Furuta , Seiichi Hannai
IPC分类号： G11C506
CPC分类号： G11C11/005 , G11C11/4125
摘要： A semiconductor integrated circuit device is configured using a DRAM and an SRAM between which data transfer is performed by way of a data transfer circuit using data transfer bus lines. Herein, the DRAM is divided into at least two DRAM arrays, each of which contains a number of columns each consisting of memory cells. In addition, the columns are arranged in mixture in connection with external I/O terminals respectively in such a way that columns respectively containing memory cells which are simultaneously subjected to read operations within a same cycle are arranged not to adjoin each other. Thus, it is possible to reduce a probability in which multiple memory cells which are simultaneously subjected to read operations within the same cycle exist within a range of an area under influence of charged particles, which are produced locally due to neutrons. Even if data of memory cells which are concentrated at a certain region are simultaneously placed under influence of the charged particles, it is possible to remarkably reduce a number of chances in that multiple bits of data being read out to the external I/O terminals go defective simultaneously.
摘要翻译：半导体集成电路器件使用DRAM和SRAM，其间通过使用数据传输总线的数据传输电路进行数据传输。这里，DRAM被划分为至少两个DRAM阵列，每个DRAM阵列包含多个列，每列由存储器单元组成。此外，这些列分别与外部I / O端子混合地排列，使得分别包含在相同周期内同时进行读取操作的存储单元的列彼此不相邻地布置。因此，可以降低在相同周期内同时进行读取操作的多个存储单元在由于中子而局部产生的带电粒子的影响范围内的可能性。即使集中在特定区域的存储单元的数据同时被放置在带电粒子的影响下，也可以显着地减少读出到外部I / O端子的多个数据位移动的次数同时发生故障。

2. 发明授权

US5489901A Data input/output circuit for a digital signal processing system 失效
标题翻译：数字信号处理系统的数据输入/输出电路
公开(公告)号：US5489901A
公开(公告)日：1996-02-06
申请号：US21832
申请日：1993-02-24
申请人： Mituyoshi Fukuda , Masahisa Shimizu , Hideki Ohashi , Masaki Kawaguchi
发明人： Mituyoshi Fukuda , Masahisa Shimizu , Hideki Ohashi , Masaki Kawaguchi
IPC分类号： G06F5/00 , G06F7/76 , H03M9/00 , H04L13/10 , H04L29/06 , H03M7/00
CPC分类号： G06F7/768 , H03M9/00
摘要： A data input/output circuit includes a 32-bit reversible shift register (1) which includes four 8-bit reversible shift registers (2-5). Input gate circuits (6, 7) selectively apply data being inputted in a bit-serial fashion from an external to the 8-bit reversible shift registers (3, 4), and output gate circuits (8-12) selectively output data being stored in arbitrary stages of the 32-bit reversible shift register (1) in a bit-serial fashion. Input latches (13-15) and output latches (16-18) each of which is an 8-bit latch are connected to the respective 8-bit reversible shift registers (2-4) and a data bus (19). The input latches (13-15) hold the data being stored in the 8-bit reversible shift registers (2-4) and send the same onto the data bus (19) in a bit-parallel fashion, and the output latches (16-18) hold the data being sent from the data bus (19) and preset the same into the 8-bit reversible shift registers (2-4) in a bit-parallel fashion.
摘要翻译：数据输入/输出电路包括一个32位可逆移位寄存器（1），它包括四个8位可逆移位寄存器（2-5）。输入门电路（6,7）有选择地将从数据串行方式输入的数据从外部输入到8位可逆移位寄存器（3,4），并且输出门电路（8-12）选择性地输出正被存储的数据在32位可逆移位寄存器（1）的任意阶段以位串行的方式。每个8位锁存器的输入锁存器（13-15）和输出锁存器（16-18）连接到相应的8位可逆移位寄存器（2-4）和数据总线（19）。输入锁存器（13-15）保持存储在8位可逆移位寄存器（2-4）中的数据，并以位并行方式将其发送到数据总线（19），输出锁存器（16 -18）保持从数据总线（19）发送的数据，并将它们以位并行的方式预设为8位可逆移位寄存器（2-4）。

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