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21. 发明授权

US08125870B1 Flexible optical write strategy 有权
标题翻译：灵活的光写策略
公开(公告)号：US08125870B1
公开(公告)日：2012-02-28
申请号：US13019011
申请日：2011-02-01
申请人： Pantas Sutardja , Yingxuan Li , Daniel Mumford
发明人： Pantas Sutardja , Yingxuan Li , Daniel Mumford
IPC分类号： G11B7/00
CPC分类号： G11B7/126 , G11B7/0062
摘要： A driver comprising: a pattern module configured to generate a plurality of timing parameters in response to a received bit stream; a timing module configured to determine a plurality of multi-bit parameters in response to the timing parameters; and a pulse module configured to (i) generate each of a plurality of pulses in response to a different one of the plurality of multi-bit parameters, (ii) generate each of a plurality of enable signals in response to a variable combination of the plurality of pulses, and (iii) output the plurality of enable signals to a laser driver.
摘要翻译：一种驱动器，包括：模式模块，被配置为响应于所接收的比特流生成多个定时参数; 定时模块，被配置为响应于所述定时参数确定多个多位参数; 以及脉冲模块，其被配置为（i）响应于所述多个多位参数中的不同的一个参数来产生多个脉冲中的每一个;（ii）响应于所述多位参数的可变组合而产生多个使能信号中的每一个多个脉冲，以及（iii）将多个使能信号输出到激光驱动器。

22. 发明授权

US07869312B1 Calibration based DC coupled analog front end for optical storage system 有权
标题翻译：基于校准的直流耦合模拟前端用于光存储系统
公开(公告)号：US07869312B1
公开(公告)日：2011-01-11
申请号：US11755463
申请日：2007-05-30
申请人： Yingxuan Li , Fu-Tai An , Yonghua Song
发明人： Yingxuan Li , Fu-Tai An , Yonghua Song
IPC分类号： G11B7/00
CPC分类号： G11B7/0945
摘要： A driver circuit for use with a variety of OPU circuits has both a single-ended input and a differential input. The single-ended input is coupled to a single-ended signal path having a variable gain stage and a variable level shifter. The differential input is coupled to a differential signal path having a variable gain stage and a variable level shifter. The single-ended signal path and the differential signal path may be selectively coupled to an output. The respective variable gain stages and variable level shifters can be adjusted so that an output signal at the output has a desired dynamic range.
摘要翻译：与各种OPU电路一起使用的驱动电路具有单端输入和差分输入。单端输入耦合到具有可变增益级和可变电平转换器的单端信号路径。差分输入耦合到具有可变增益级和可变电平转换器的差分信号路径。单端信号路径和差分信号路径可以选择性地耦合到输出端。可以调节各个可变增益级和可变电平移位器，使得输出端的输出信号具有期望的动态范围。

23. 发明授权

US07737731B1 High data rate envelope detector for high speed optical storage application 失效
标题翻译：用于高速光存储应用的高数据速率包络检测器
公开(公告)号：US07737731B1
公开(公告)日：2010-06-15
申请号：US11492612
申请日：2006-07-24
申请人： Qiang Luo , Yingxuan Li , Sriharsha Annadore , Pantas Sutardja
发明人： Qiang Luo , Yingxuan Li , Sriharsha Annadore , Pantas Sutardja
IPC分类号： H03K5/153
CPC分类号： G11B20/10009 , G01R19/04 , G11B20/10416 , G11B2220/2516 , G11B2220/2562
摘要： To detect the peaks level of an incoming signal, the difference between the voltage level of the incoming signal and a voltage developed across a capacitor is amplified. The amplified difference signal is applied to a transconductor adapted to vary its output current in response to changes in the amplified difference signal. The variations in the current generated by the transconductor are used to change a current flowing through a current mirror that charges the capacitor. The voltage developed across the capacitor represents the detected peak. The capacitor is discharged to a predefined voltage level during the reset periods. A second amplifier receiving the capacitor voltage is optionally used to develop a voltage across a second capacitor that is not reset and thus carries only the detected peak levels.
摘要翻译：为了检测输入信号的峰值电平，输入信号的电压电平和电容器两端产生的电压之间的差异被放大。放大的差分信号被施加到适于根据放大的差分信号的变化改变其输出电流的跨导体。由跨导体产生的电流的变化用于改变流经电容器的电流镜的电流。电容器上产生的电压表示检测到的峰值。电容器在复位期间被放电到预定的电压电平。可选地，接收电容器电压的第二放大器用于在不复位的第二电容器上产生电压，并因此仅传送检测到的峰值电平。

24. 发明授权

US07312642B1 Continuous, wide-range frequency synthesis and phase tracking methods and apparatus 有权
标题翻译：连续，大范围的频率合成和相位跟踪方法和装置
公开(公告)号：US07312642B1
公开(公告)日：2007-12-25
申请号：US11498958
申请日：2006-08-02
申请人： Yingxuan Li , Pantas Sutardja
发明人： Yingxuan Li , Pantas Sutardja
IPC分类号： H03B21/00
CPC分类号： H03L7/18 , H03L7/0891 , H03L7/091 , H03L7/0991 , H03L7/23
摘要： Circuitry and methods are provided for continuously adjustable frequency synthesis. The synthesis covers a wide range of possible frequencies and can be performed to a high degree of precision. In an embodiment of the invention, an analog phase-locked loop (“PLL”) performs relatively coarse wide-range frequency synthesis, while a digital PLL performs relatively fine narrow-range frequency synthesis and phase alignment. The analog PLL is capable of varying frequency in a stepwise linear fashion. The digital PLL communicates with the analog PLL to ensure that the output of the analog PLL is within the digital PLL's specified pull-in range.
摘要翻译：提供电路和方法用于连续可调频率合成。该合成涵盖了广泛的可能频率，并且可以以高精度执行。在本发明的一个实施例中，模拟锁相环（“PLL”）执行相对粗略的宽范围频率合成，而数字PLL执行相对精细的窄范围频率合成和相位对准。模拟PLL能够以逐步线性方式变化频率。数字PLL与模拟PLL通信，以确保模拟PLL的输出在数字PLL的指定拉入范围内。

25. 发明授权

US07002500B2 Circuit, apparatus and method for improved current distribution of output drivers enabling improved calibration efficiency and accuracy 失效
标题翻译：用于改善输出驱动电流分布的电路，装置和方法，可提高校准效率和精度
公开(公告)号：US07002500B2
公开(公告)日：2006-02-21
申请号：US11114326
申请日：2005-04-26
申请人： Yingxuan Li
发明人： Yingxuan Li
IPC分类号： H03M1/66
CPC分类号： G11C29/022 , G11C7/1057 , G11C29/02 , G11C29/028 , G11C2029/5006 , G11C2207/2254
摘要： A circuit, apparatus and method for efficiently and accurately calibrating an output driver current are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a first digital-to-analog converter (“DAC”) that generates a first current. A first transistor is coupled to the first DAC and generates a first biasing current responsive to the first current. A second DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. According to an embodiment of the present invention, the first and second DACs are binary weighted control DACs. According to an embodiment of the present invention, the binary weighted values of the second DAC are obtained in response to a calibration signal generated by a controller. According to an embodiment of the present invention, the first DAC is an M-bit DAC and the second DAC is an N-bit DAC, wherein M is less than N. According to an embodiment of the present invention, the circuit is in a memory device and a controller generates calibration signals.
摘要翻译：在本发明的实施例中提供了用于有效且精确地校准输出驱动器电流的电路，装置和方法。在本发明的实施例中，电路包括产生第一电流的第一数模转换器（“DAC”）。第一晶体管耦合到第一DAC并产生响应于第一电流的第一偏置电流。第二DAC耦合到第一晶体管，并响应于第一偏置电流产生第一控制电流。根据本发明的实施例，第一和第二DAC是二进制加权控制DAC。根据本发明的实施例，响应于由控制器产生的校准信号，获得第二DAC的二进制加权值。根据本发明的实施例，第一DAC是M位DAC，第二DAC是N位DAC，其中M小于N.根据本发明的实施例，电路处于存储器件和控制器产生校准信号。

26. 发明授权

US06909387B2 Circuit, apparatus and method for improved current distribution of output drivers enabling improved calibration efficiency and accuracy 失效
标题翻译：用于改善输出驱动电流分布的电路，装置和方法，可提高校准效率和精度
公开(公告)号：US06909387B2
公开(公告)日：2005-06-21
申请号：US10695569
申请日：2003-10-28
申请人： Yingxuan Li
发明人： Yingxuan Li
IPC分类号： G11C29/02 , H03M1/10
CPC分类号： G11C29/022 , G11C7/1057 , G11C29/02 , G11C29/028 , G11C2029/5006 , G11C2207/2254
摘要： A circuit, apparatus and method for efficiently and accurately calibrating an output driver current are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a first digital-to-analog converter (“DAC”) that generates a first current. A first transistor is coupled to the first DAC and generates a first biasing current responsive to the first current. A second DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. According to an embodiment of the present invention, the first and second DACs are binary weighted control DACs. According to an embodiment of the present invention, the binary weighted values of the second DAC are obtained in response to a calibration signal generated by a controller. According to an embodiment of the present invention, the first DAC is an M-bit DAC and the second DAC is an N-bit DAC, wherein M is less than N. According to an embodiment of the present invention, the circuit is in a memory device and a controller generates calibration signals.
摘要翻译：在本发明的实施例中提供了用于有效且精确地校准输出驱动器电流的电路，装置和方法。在本发明的实施例中，电路包括产生第一电流的第一数模转换器（“DAC”）。第一晶体管耦合到第一DAC并产生响应于第一电流的第一偏置电流。第二DAC耦合到第一晶体管，并响应于第一偏置电流产生第一控制电流。根据本发明的实施例，第一和第二DAC是二进制加权控制DAC。根据本发明的实施例，响应于由控制器产生的校准信号，获得第二DAC的二进制加权值。根据本发明的实施例，第一DAC是M位DAC，第二DAC是N位DAC，其中M小于N.根据本发明的实施例，电路处于存储器件和控制器产生校准信号。

27. 发明授权

US06850124B1 Circuit, architecture and method for tracking loop bandwidth in a frequency synthesizer having a wide frequency range 有权
标题翻译：用于跟踪具有较宽频率范围的频率合成器中的环路带宽的电路，结构和方法
公开(公告)号：US06850124B1
公开(公告)日：2005-02-01
申请号：US10464278
申请日：2003-06-17
申请人： Yingxuan Li
发明人： Yingxuan Li
IPC分类号： H03B27/00 , H03L7/00 , H03L7/093 , H03L7/099 , H03L7/183
CPC分类号： H03L7/093 , H03L7/0995 , H03L7/183
摘要： Circuits, architectures, and methods for tracking a phase locked loop (PLL) configuration such that its VCO gain is essentially a linear function of its feedback divider factor over a wide frequency range. The circuit generally includes an oscillator loop having (2n+1) stages, where n is an integer of at least 1, and at least three of the stages comprise a delay circuit and a characteristic control circuit configured to (i) receive divider information and (ii) set or change a delay characteristic of the delay circuit in response to the divider information. The architectures generally relate to PLLs that include a circuit embodying one or more of the inventive concepts disclosed herein. The method generally includes the steps of generating a periodic signal from an oscillator, dividing the periodic signal by a first number, and setting a characteristic property of at least part of the oscillator in accordance with the first number. The present invention advantageously tracks changes to a PLL and adjusts the VCO gain dynamically and in a predictable and controllable manner in response to such changes. The present invention avoids noisy and/or complicated charge pump and/or filter designs, and advantageously improves PLL stability, reliability and/or performance.
摘要翻译：用于跟踪锁相环（PLL）配置的电路，架构和方法，使得其VCO增益基本上是其在较宽频率范围内的反馈分频器因子的线性函数。电路通常包括具有（2n + 1）级的振荡器环路，其中n是至少为1的整数，并且至少三个级包括延迟电路和特性控制电路，其被配置为（i）接收分频器信息，以及（ii）响应于分频器信息设置或改变延迟电路的延迟特性。该体系结构通常涉及包括体现本文公开的一个或多个本发明构思的电路的PLL。该方法通常包括以下步骤：从振荡器产生周期性信号，将周期信号除以第一数字，并根据第一个数字设置至少部分振荡器的特性。本发明有利地跟踪对PLL的改变，并且响应于这种改变动态地并且以可预测和可控的方式调整VCO增益。本发明避免了噪声和/或复杂的电荷泵和/或滤波器设计，并且有利地提高了PLL的稳定性，可靠性和/或性能。

28. 发明授权

US06674377B1 Circuit, apparatus and method for improved current distribution of output drivers enabling improved calibration efficiency and accuracy 有权
公开(公告)号：US06674377B1
公开(公告)日：2004-01-06
申请号：US10132246
申请日：2002-04-25
申请人： Yingxuan Li
发明人： Yingxuan Li
IPC分类号： H03M110
CPC分类号： G11C29/022 , G11C7/1057 , G11C29/02 , G11C29/028 , G11C2029/5006 , G11C2207/2254
摘要： A circuit, apparatus and method for efficiently and accurately calibrating an output driver current are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a first digital-to-analog converter (“DAC”) that generates a first current. A first transistor is coupled to the first DAC and generates a first biasing current responsive to the first current. A second DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. According to an embodiment of the present invention, the first and second DACs are binary weighted control DACs. According to an embodiment of the present invention, the binary weighted values of the second DAC are obtained in response to a calibration signal generated by a controller. According to an embodiment of the present invention, the first DAC is an M-bit DAC and the second DAC is an N-bit DAC, wherein M is less than N. According to an embodiment of the present invention, the circuit is in a memory device and a controller generates calibration signals.

29. 发明授权

US06573779B2 Duty cycle integrator with tracking common mode feedback control 有权
公开(公告)号：US06573779B2
公开(公告)日：2003-06-03
申请号：US09865615
申请日：2001-05-25
申请人： Stefanos Sidiropoulos , Yingxuan Li
发明人： Stefanos Sidiropoulos , Yingxuan Li
IPC分类号： G06F764
CPC分类号： H03F3/45183 , H03F3/4565 , H03F2203/45466 , H03F2203/45631 , H03F2203/45642 , H03F2203/45644 , H03F2203/45648
摘要： Disclosed herein is a process-tracking clock duty cycle integrator. Common mode feedback is used to set a common mode output voltage that varies with the voltage threshold of MOS elements that implement the circuit. In addition, a buffer is used to control the common mode input voltage to the differential amplifier circuit, and to vary the common mode input voltage with the voltage threshold.

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