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21. 发明授权

US06610127B2 Facility for improving environmental atmosphere of interior space 有权
标题翻译：改善室内空气环境的设施
公开(公告)号：US06610127B2
公开(公告)日：2003-08-26
申请号：US09906728
申请日：2001-07-18
申请人： Wen-Pin Lu
发明人： Wen-Pin Lu
IPC分类号： B03C341
CPC分类号： F24F3/12 , F24F2003/1682
摘要： A facility for improving the environmental atmosphere of an interior space, which includes a negative ion discharger; a plurality of electric poles connected to the output wires of the negative ion discharger. The aforementioned negative ion discharger is placed in a corner of the interior space, and the plurality of electric poles are situated in the upper part of the interior space. By means of an active carbon layer beneath the floor indoors, an invisible shelter will be formed by the negative ions released from the negative ion discharger. Accordingly, the ion energy will be effectively decreased, and the particle condition of the indoor space will be harmonized. In addition, a proper proportion of active carbon and zeolite are mixed with concrete, or a predetermined amount of active carbon is buried in cavities by the building, in order to absorb the moisture and the calcium, magnesium, and sodium, to purify the interior atmosphere, to diminish the humidity of the air indoors, and to lift the health of the people living in such space.
摘要翻译：一种用于改善内部空间的环境气氛的设施，其包括负离子放电器; 连接到负离子放电器的输出线的多个电极。上述负离子放电器被放置在内部空间的角落中，并且多个电极位于内部空间的上部。通过室内地板下面的活性炭层，由负离子放电器释放的负离子将形成不可见的遮蔽物。因此，能够有效地降低离子能量，并且使室内空间的粒子状态相一致。此外，将适当比例的活性炭和沸石与混凝土混合，或者通过建筑物将预定量的活性炭掩埋在空腔中，以便吸收水分和钙，镁和钠，以净化内部气氛，以减少室内空气的湿度，并提升居住在这样的空间的人的健康。

22. 发明授权

US06496417B1 Method and integrated circuit for bit line soft programming (BLISP) 有权
标题翻译：位线软编程方法与集成电路（BLISP）
公开(公告)号：US06496417B1
公开(公告)日：2002-12-17
申请号：US09601089
申请日：2000-07-27
申请人： Tzeng-Huei Shiau , Ray-Lin Wan , Han Sung Chen , Yu-Shen Lin , Wen-Pin Lu , Tso-Ming Chang
发明人： Tzeng-Huei Shiau , Ray-Lin Wan , Han Sung Chen , Yu-Shen Lin , Wen-Pin Lu , Tso-Ming Chang
IPC分类号： G11C1604
CPC分类号： G11C16/107 , G11C16/3404 , G11C16/3409 , G11C16/3413 , G11C16/3445
摘要： A method and an integrated circuit for performing a soft program after erase provides efficient convergence of over-erased floating gate memory cells disposed in bit lines. The soft program is applied to successive subject bit lines. The BLISP method includes selection of a selected bit line and applying the soft program to a subject bit line corresponding to the selected bit line. For integrated circuits having no defective bit lines, the subject bit lines comprise the selected bit lines. The BLISP method is adapted for low current consumption compared to bulk soft programming methods. In some embodiments, the integrated circuit includes defective bit lines. For these integrated circuits, the selection of the selected bit line includes indicating a bit line type corresponding to the selected bit line. The defective bit lines are logically replaced by redundant bit lines so that the soft program is applied to conforming selected bit lines and redundant bit lines corresponding to defective bit lines. The defective bit lines in the first memory array can be disabled during the soft program and replaced by corresponding redundant bit lines disposed in the second memory array, so that the soft program is not applied to the defective bit lines. By preventing application of the soft program to the defective bit lines, the BLISP method avoids consumption of excessive current that would otherwise be consumed by very low threshold voltage memory cells disposed on the defective bit lines. The excessive current would render the soft program method much less efficient.
摘要翻译：用于在擦除之后执行软程序的方法和集成电路提供了布置在位线中的过擦除的浮动栅极存储单元的有效收敛。软程序应用于连续的主题位线。 BLISP方法包括选择所选位线并将软程序应用于对应于所选位线的对象位线。对于没有有缺陷的位线的集成电路，主题位线包括所选择的位线。与批量软编程方法相比，BLISP方法适用于低电流消耗。在一些实施例中，集成电路包括有缺陷的位线。对于这些集成电路，选择的位线的选择包括指示对应于所选位线的位线类型。有缺陷的位线在逻辑上被冗余位线替代，使得软程序被应用于对应于有缺陷位线的选定位线和冗余位线。可以在软程序期间禁用第一存储器阵列中的有缺陷的位线，并且由位于第二存储器阵列中的对应的冗余位线替换第一存储器阵列中的有缺陷的位线，使得软程序不被施加到有缺陷的位线。通过防止将软程序应用于有缺陷的位线，BLISP方法避免消耗过剩的电流，否则会由设置在有缺陷位线上的非常低的阈值电压存储单元消耗。过度的电流将使软程序方法效率低得多。

23. 发明授权

US08466508B2 Non-volatile memory structure including stress material between stacked patterns 有权
标题翻译：非易失性存储器结构，包括层叠图案之间的应力材料
公开(公告)号：US08466508B2
公开(公告)日：2013-06-18
申请号：US11866756
申请日：2007-10-03
申请人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
发明人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
IPC分类号： H01L29/792 , H01L29/788 , H01L21/762
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.
摘要翻译：提供了包括基板，堆叠图案和应力图案的非易失性存储器结构。层叠图案设置在基板上。每个堆叠图案包括电荷存储结构和从底部到顶部的栅极。这里，电荷存储结构至少包括电荷存储层。应力图案分别设置在两个相邻堆叠图案之间的基板上。

24. 发明授权

US07596028B2 Variable program and program verification methods for a virtual ground memory in easing buried drain contacts 有权
标题翻译：用于虚拟接地存储器的可变程序和程序验证方法，以缓解埋地漏接点
公开(公告)号：US07596028B2
公开(公告)日：2009-09-29
申请号：US11617007
申请日：2006-12-28
申请人： Ming Shiang Chen , Wen Pin Lu , I-Jen Huang , Chi Yuan Chin , Nian-Kai Zous
发明人： Ming Shiang Chen , Wen Pin Lu , I-Jen Huang , Chi Yuan Chin , Nian-Kai Zous
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/3454 , G11C16/3459
摘要： Methods for programming and program verification of a flash memory are described that ease the buried drain contact induced operation and increase the retention window. In a first aspect of the invention, a program operation method provides varying program biases which are applied to different groups of memory cells. The program biases can be supplied as drain bias voltages or gate bias voltages. The program biases vary depending on which group of memory cells is programmed. In one embodiment, a first drain voltage VD1 is applied to the first group of memory cells M0 and Mn. A second drain voltage VD2 is applied to the second group of memory cells M1 and Mn-1, where VD2=VD1+ΔVD. In a second aspect of the invention, a plurality of program verification voltage levels are selected to verify that the memory cells pass the program voltage levels.
摘要翻译：描述了用于快速存储器的编程和程序验证的方法，其易于埋入漏极接触引起的操作并增加保持窗口。在本发明的第一方面，一种程序操作方法提供了应用于不同组的存储单元的变化的程序偏移。程序偏置可以作为漏极偏置电压或栅极偏置电压提供。程序偏移根据编程的哪组存储单元而有所不同。在一个实施例中，将第一漏极电压VD1施加到第一组存储器单元M0和Mn。第二漏极电压VD2被施加到第二组存储器单元M1和Mn-1，其中VD2 = VD1 + DeltaVD。在本发明的第二方面中，选择多个程序验证电压电平以验证存储单元是否通过编程电压电平。

25. 发明授权

US07399674B2 Method of fabricating NAND-type flash EEPROM without field oxide isolation 有权
标题翻译：制造没有场氧化物隔离的NAND型快闪EEPROM的方法
公开(公告)号：US07399674B2
公开(公告)日：2008-07-15
申请号：US10971465
申请日：2004-10-22
申请人： Ming-Shang Chen , Wen-Pin Lu
发明人： Ming-Shang Chen , Wen-Pin Lu
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells.
摘要翻译：描述了用于制造没有场氧化物隔离的NAND型EEPROM的方法。采用P +注入来隔离相邻的记忆细胞。

26. 发明申请

US20060086968A1 Method of fabricating NAND-type flash EEPROM without field oxide isolation 有权
标题翻译：制造没有场氧化物隔离的NAND型快闪EEPROM的方法
公开(公告)号：US20060086968A1
公开(公告)日：2006-04-27
申请号：US10971465
申请日：2004-10-22
申请人： Ming-Shang Chen , Wen-Pin Lu
发明人： Ming-Shang Chen , Wen-Pin Lu
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells.
摘要翻译：描述了用于制造没有场氧化物隔离的NAND型EEPROM的方法。采用P +注入来隔离相邻的记忆细胞。

27. 发明授权

US08451641B2 Memory array no common source region and method of fabricating the same 有权
标题翻译：存储器阵列没有公共源区及其制造方法
公开(公告)号：US08451641B2
公开(公告)日：2013-05-28
申请号：US13549272
申请日：2012-07-13
申请人： Chun-Yuan Lo , Cheng-Ming Yih , Wen-Pin Lu
发明人： Chun-Yuan Lo , Cheng-Ming Yih , Wen-Pin Lu
IPC分类号： G11C7/00
CPC分类号： H01L27/11519 , G11C5/005 , G11C5/025 , G11C5/063 , G11C8/14 , H01L27/11565
摘要： A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line.
摘要翻译：提供了包括多个存储单元，多个字线，虚拟字线和插头的存储器阵列。每个字线耦合到相应的存储单元。虚拟字线与多个字线的最外侧字线直接相邻。插头位于虚拟字线和最外面的字线之间。

28. 发明授权

US08243489B2 Memory device no common source region and method of fabricating the same 有权
标题翻译：存储器件没有共同的源极区域及其制造方法
公开(公告)号：US08243489B2
公开(公告)日：2012-08-14
申请号：US13045153
申请日：2011-03-10
申请人： Chun-Yuan Lo , Cheng-Ming Yih , Wen-Pin Lu
发明人： Chun-Yuan Lo , Cheng-Ming Yih , Wen-Pin Lu
IPC分类号： G11C7/00
CPC分类号： H01L27/11519 , G11C5/005 , G11C5/025 , G11C5/063 , G11C8/14 , H01L27/11565
摘要： A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.
摘要翻译：提供包括多个存储单元，多个字线，虚拟字线，至少第一导电区域和至少第一插头的存储器阵列。每个字线耦合到相应的存储单元。虚拟字线与多个字线的最外侧字线直接相邻。第一导电区域仅设置在虚拟字线和最外侧字线之间。第一个插头位于虚拟字线和最外面的字线之间。

29. 发明申请

US20120119282A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路装置及制造半导体集成电路装置的方法
公开(公告)号：US20120119282A1
公开(公告)日：2012-05-17
申请号：US12945659
申请日：2010-11-12
申请人： Yu-Fong Huang , Tzung-Ting Han , Wen-Pin Lu
发明人： Yu-Fong Huang , Tzung-Ting Han , Wen-Pin Lu
IPC分类号： H01L27/11 , H01L21/336
CPC分类号： H01L29/7926 , H01L27/11565 , H01L27/11582
摘要： A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSix), and a self-aligned silicide (salicide) film, for example cobalt silicide (CoSi) and/or nickel silicide (NiSi), above the buried diffusion (BD) layer. The semiconductor integrated circuit can also include a memory gate structure formed over at least a portion of the contact layer.
摘要翻译：用于半导体集成电路器件的系统，方法和布局允许改进可以包括触点和其它金属互连结构的各种后端结构的缩小。所得到的结构可以包括半导体衬底，形成在半导体衬底上的掩埋扩散区，以及硅化物膜，例如硅化钨（WSix）和自对准硅化物（自对准硅）膜中的至少一种，例如钴硅化物（CoSi）和/或硅化镍（NiSi），在掩埋扩散（BD）层之上。半导体集成电路还可以包括形成在接触层的至少一部分上的存储器栅极结构。

30. 发明授权

US07924591B2 Memory device with shielding plugs adjacent to a dummy word line thereof 有权
标题翻译：具有与其虚拟字线相邻的屏蔽插头的存储器件
公开(公告)号：US07924591B2
公开(公告)日：2011-04-12
申请号：US12366910
申请日：2009-02-06
申请人： Chun-Yuan Lo , Cheng-Ming Yih , Wen-Pin Lu
发明人： Chun-Yuan Lo , Cheng-Ming Yih , Wen-Pin Lu
IPC分类号： G11C7/02
CPC分类号： H01L27/11519 , G11C5/005 , G11C5/025 , G11C5/063 , G11C8/14 , H01L27/11565
摘要： A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line.
摘要翻译：提供存储器件。存储器件包括衬底，多个字线，多个导电区域和至少屏蔽插头。衬底具有存储区域和周边区域。字线设置在基板上，并且至少设置在周边区域中并与字线相邻的虚拟字线。导电区域分别设置在基板中和字线之间。屏蔽插头位于基板上并且与虚拟字线相邻，并且在虚拟字线和字线之间，并且在伪字线周围没有自对准源极区域。

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