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21. 发明授权

US06914819B2 Non-volatile flash memory 有权
标题翻译：非易失性闪存
公开(公告)号：US06914819B2
公开(公告)日：2005-07-05
申请号：US10653892
申请日：2003-09-04
申请人： Chih-Chieh Yeh , Hung-Yueh Chen , Wen-Jer Tsai , Tao-Cheng Lu
发明人： Chih-Chieh Yeh , Hung-Yueh Chen , Wen-Jer Tsai , Tao-Cheng Lu
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/26 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/3418 , G11C16/0475 , G11C16/26
摘要： A method of operating a non-volatile memory cell, wherein the non-volatile memory cell includes a word line, a first bit line, and a second bit line, the method includes programming the memory cell that includes applying a high positive bias to the first bit line, applying a ground bias to the second bit line, and applying a high negative bias to the word line, wherein positively-charged holes tunnel through the dielectric layer into the trapping layer.
摘要翻译：一种操作非易失性存储单元的方法，其中所述非易失性存储单元包括字线，第一位线和第二位线，所述方法包括对所述存储器单元进行编程，所述存储单元包括向所述存储单元施加高正偏压第一位线，对第二位线施加接地偏置，以及向字线施加高负偏压，其中带正电荷的空穴穿过介电层进入捕获层。

22. 发明授权

US06801453B2 Method and apparatus of a read scheme for non-volatile memory 有权
标题翻译：用于非易失性存储器的读取方案的方法和装置
公开(公告)号：US06801453B2
公开(公告)日：2004-10-05
申请号：US10112871
申请日：2002-04-02
申请人： Chih-Chieh Yeh , Wen-Jer Tsai , Tao-Cheng Lu
发明人： Chih-Chieh Yeh , Wen-Jer Tsai , Tao-Cheng Lu
IPC分类号： G11C1604
CPC分类号： G11C16/3418 , G11C16/0475 , G11C16/26
摘要： A method of a read scheme for a non-volatile memory cell. The non-volatile memory cell includes a substrate, a source, a drain and a gate above a channel separated by a nonconducting charge trapping material sandwiched between first and second insulating layers. The method applies a first positive drain-to-source bias, a second positive source-to-substrate bias, and a third positive gate-to-source bias to read the source-side charges trapped in the trapping material near the source side.
摘要翻译：一种用于非易失性存储单元的读取方案的方法。非易失性存储单元包括衬底，源极，漏极以及由夹在第一绝缘层和第二绝缘层之间的非导电电荷捕获材料隔开的沟道之上的栅极。该方法应用第一正的漏极 - 源极偏置，第二正的源极 - 衬底偏置和第三正向栅极 - 源偏置来读取在源极附近的捕获材料中的源极电荷。

23. 发明授权

US06657894B2 Apparatus and method for programming virtual ground nonvolatile memory cell array without disturbing adjacent cells 有权
标题翻译：用于编程虚拟接地非易失性存储单元阵列而不干扰相邻单元的装置和方法
公开(公告)号：US06657894B2
公开(公告)日：2003-12-02
申请号：US10112923
申请日：2002-03-29
申请人： Chih-Chieh Yeh , Wen-Jer Tsai , Tao-Cheng Lu
发明人： Chih-Chieh Yeh , Wen-Jer Tsai , Tao-Cheng Lu
IPC分类号： G11C1604
CPC分类号： G11C16/0491 , G11C16/12
摘要： A virtual ground nonvolatile memory cell array is formed by a plurality of adjacent nonvolatile memory cells arranged in rows and columns so as to form an array. Each of the nonvolatile memory cells is formed by an N channel MOSFET with a trapping layer formed between two isolating layers. In the erase state, the trapping layer stores an amount of electrons. A method for programming the virtual ground nonvolatile memory cell array is also disclosed. The potentials applied to the bitlines and wordlines in the array are preset to program nonvolatile memory cells and not to disturb cells adjacent to the nonvolatile memory cell to be programmed.
摘要翻译：由布置成行和列的多个相邻的非易失性存储单元形成虚拟非易失性存储单元阵列，以形成阵列。每个非易失性存储单元由具有在两个隔离层之间形成的捕获层的N沟道MOSFET形成。在擦除状态下，捕获层存储一定量的电子。还公开了一种用于编程虚拟接地非易失性存储单元阵列的方法。应用于阵列中的位线和字线的电位被预设为非易失性存储器单元，而不是干扰与待编程的非易失性存储器单元相邻的单元。

24. 发明授权

US06563752B2 Qualification test method and circuit for a non-volatile memory 有权
标题翻译：用于非易失性存储器的资格测试方法和电路
公开(公告)号：US06563752B2
公开(公告)日：2003-05-13
申请号：US09945289
申请日：2001-08-30
申请人： Wen-Jer Tsai , Nian-Kai Zous , Ta-Hui Wang
发明人： Wen-Jer Tsai , Nian-Kai Zous , Ta-Hui Wang
IPC分类号： G11C700
CPC分类号： G11C29/50004 , G11C16/04 , G11C29/50
摘要： A qualification test method for a non-volatile memory includes determining a relation curve between the programming voltage and the lifetime of the memory cell. A programming voltage with respect to the memory array within the expected lifetime is estimated. According to the relation curve, the accelerating test voltage and the test time period corresponding to the programming voltage operated in the expected lifetime are computed out. The test is performed for the test time period under the accelerating test voltage. All the memory cells at the programmed state are tested to see if the original programmed state still remains. If the programmed state remains, the memory array is judged to have the life period. If the programmed state does not remain, the memory array is judged to have no the life period.
摘要翻译：用于非易失性存储器的资格测试方法包括确定编程电压与存储器单元的寿命之间的关系曲线。估计在预期寿命期内相对于存储器阵列的编程电压。根据该关系曲线计算加速试验电压和对应于在预期寿命中运行的编程电压的试验时间。在加速测试电压下进行测试时间。测试编程状态下的所有存储单元，以查看原始编程状态是否仍然保留。如果编程状态保持不变，则判断存储器阵列具有使用寿命。如果编程状态不存在，则判断存储器阵列没有寿命周期。

25. 发明授权

US06320786B1 Method of controlling multi-state NROM 有权
标题翻译：控制多状态NROM的方法
公开(公告)号：US06320786B1
公开(公告)日：2001-11-20
申请号：US09777229
申请日：2001-02-05
申请人： Yao Wen Chang , Wen Jer Tsai , Tao Cheng Lu
发明人： Yao Wen Chang , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C1604
CPC分类号： G11C11/5671 , G11C16/0466
摘要： A method of controlling the multi-state NROM. A program is executed to inject electric charges that are trapped inside a nitride layer of the NROM. The amount of electric charges trapped inside the nitride layer is controlled so that the memory cell can have different threshold voltages. To read from the memory cell, a first variable voltage is applied to the gate electrode. According to the range of a second variable voltage applied to the drain terminal, three different potential levels, from the smallest to the largest, including a first potential level, a second potential level and a third potential level are set. The second input voltage is adjusted to the first potential level. When a high current is sensed, a first storage state is assumed. If little current is detected, the second input voltage is adjusted to the second potential level. When a high current is sensed, a second storage state is assumed. On the other hand, if little current is detected, the second input voltage is adjusted to the third potential level. Similarly, if a high current is sensed, a third storage state is assumed. Conversely, when little current is detected, a fourth storage state is assumed.
摘要翻译：一种控制多状态NROM的方法。执行程序以注入被俘获在NROM的氮化物层内部的电荷。控制在氮化物层内捕获的电荷量，使得存储单元可以具有不同的阈值电压。为了从存储单元读取，向栅电极施加第一可变电压。根据施加到漏极端子的第二可变电压的范围，设置包括第一电位电平，第二电位电平和第三电位电平的从最小到最大的三个不同的电位电平。将第二输入电压调整到第一电位电平。当检测到高电流时，假设第一存储状态。如果检测到小的电流，则将第二输入电压调整到第二电位电平。当感测到高电流时，假设第二存储状态。另一方面，如果检测到小的电流，则将第二输入电压调整到第三电位电平。类似地，如果感测到高电流，则假设第三存储状态。相反，当检测到少量电流时，假设第四存储状态。

26. 发明授权

US08861281B2 Method of programming memory and memory apparatus utilizing the method 有权
标题翻译：利用该方法编程存储器和存储装置的方法
公开(公告)号：US08861281B2
公开(公告)日：2014-10-14
申请号：US13105276
申请日：2011-05-11
申请人： Ping-Hung Tsai , Jyun-Siang Huang , Wen-Jer Tsai
发明人： Ping-Hung Tsai , Jyun-Siang Huang , Wen-Jer Tsai
IPC分类号： G11C11/40 , G11C16/34 , G11C16/32 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/0433 , G11C16/32 , G11C16/3454
摘要： A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first voltage is applied to a control gate of the first cell, a second voltage is applied to a control gate of the second cell to slightly turn on a channel of the second cell, a third and a fourth voltage are respectively applied to the first and the third S/D regions, and the second S/D region is floating. A carrier flows from the third S/D region to the first S/D region, and is injected into a charge storage layer of the first cell by source-side injection.
摘要翻译：提供了一种编程存储器的方法。存储器具有第一单元，具有与第二单元共用的第一S / D区和第二S / D区。第二单元具有与第二S / D区相反的第三S / D区。当对第一单元进行编程时，第一电压被施加到第一单元的控制栅极，第二电压被施加到第二单元的控制栅极，以稍微导通第二单元的沟道，第三和第四电压分别施加到第一和第三S / D区域，并且第二S / D区域是浮置的。载体从第三S / D区流向第一S / D区，并通过源侧注入注入第一单元的电荷存储层。

27. 发明授权

US08791522B2 Non-volatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US08791522B2
公开(公告)日：2014-07-29
申请号：US13271517
申请日：2011-10-12
申请人： Chih-Chieh Cheng , Shih-Guei Yan , Cheng-Hsien Cheng , Wen-Jer Tsai
发明人： Chih-Chieh Cheng , Shih-Guei Yan , Cheng-Hsien Cheng , Wen-Jer Tsai
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7887 , H01L29/7923
摘要： A non-volatile memory and a manufacturing method thereof are provided. A first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the charge storage spacers. A conductive layer is formed on the second oxide layer.
摘要翻译：提供了一种非易失性存储器及其制造方法。具有突出部的第一氧化物层形成在基板上。在突起的两侧在衬底中形成一对掺杂区域。在突起的侧壁上形成一对电荷存储间隔物。在第一氧化物层和电荷存储间隔物上形成第二氧化物层。在第二氧化物层上形成导电层。

28. 发明授权

US08760909B2 Memory and manufacturing method thereof 有权
标题翻译：其记忆及其制造方法
公开(公告)号：US08760909B2
公开(公告)日：2014-06-24
申请号：US13277816
申请日：2011-10-20
申请人： Jyun-Siang Huang , Wen-Jer Tsai
发明人： Jyun-Siang Huang , Wen-Jer Tsai
IPC分类号： G11C11/00
CPC分类号： H01L29/66833 , H01L27/11578 , H01L29/792
摘要： A memory and a manufacturing method thereof are provided. A plurality of stacked structures extending along a first direction is formed on a substrate. Each of the stacked structures includes a plurality of first insulating layers and a plurality of second insulating layers. The first insulating layers are stacked on the substrate and the second insulating layers are respectively disposed between the adjacent first insulating layers. A plurality of trenches extending along the first direction is formed in each of the stacked structures. The trenches are respectively located at two opposite sides of each of the second insulating layers. A first conductive layer is filled in the trenches. A plurality of charge storage structures extending along a second direction is formed on the stacked structures and a second conductive layer is formed on each of the charge storage structures.
摘要翻译：提供了一种存储器及其制造方法。沿着第一方向延伸的多个堆叠结构形成在基板上。每个堆叠结构包括多个第一绝缘层和多个第二绝缘层。第一绝缘层层叠在基板上，第二绝缘层分别设置在相邻的第一绝缘层之间。沿着第一方向延伸的多个沟槽形成在每个堆叠结构中。沟槽分别位于每个第二绝缘层的两个相对侧。第一导电层填充在沟槽中。沿着第二方向延伸的多个电荷存储结构形成在层叠结构上，并且在每个电荷存储结构上形成第二导电层。

29. 发明授权

US08531886B2 Hot carrier programming in NAND flash 有权
标题翻译： NAND闪存中的热载波编程
公开(公告)号：US08531886B2
公开(公告)日：2013-09-10
申请号：US12797994
申请日：2010-06-10
申请人： Jyun-Siang Huang , Wen-Jer Tsai
发明人： Jyun-Siang Huang , Wen-Jer Tsai
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection using a boosted channel potential to establish the heating field. Boosted channel hot carrier injection can be based on blocking flow of carriers between a first side of a selected cell and a second side of the selected cell in the NAND string, boosting by capacitive coupling the first semiconductor body region to a boosted voltage level, biasing the second semiconductor body region to a reference voltage level, applying a program potential greater than a hot carrier injection barrier level to the selected cell and enabling flow of carriers from the second semiconductor body region to the selected cell to cause generation of hot carriers.
摘要翻译：存储器件包括串联布置在半导体本体中的多个存储单元，例如具有多个字线的NAND串。通过使用升压通道电位的热载流子注入来对选定的存储单元进行编程以建立加热场。升压通道热载流子注入可以基于阻塞NAND串中选定单元的第一侧和所选单元的第二侧之间的载流子的流动，通过将第一半导体体区域电容耦合到提升的电压电平来提升将第二半导体主体区域设置为参考电压电平，将大于热载流子注入势垒级的编程电位施加到所选择的单元，并且使载流子能够从第二半导体体区域流向所选择的单元以引起热载流子的产生。

30. 发明授权

US08369148B2 Operation methods for memory cell and array thereof immune to punchthrough leakage 有权
标题翻译：记忆单元及其阵列的操作方法免于穿透泄漏
公开(公告)号：US08369148B2
公开(公告)日：2013-02-05
申请号：US12264893
申请日：2008-11-04
申请人： Tien-Fan Ou , Wen-Jer Tsai , Jyun-Siang Huang
发明人： Tien-Fan Ou , Wen-Jer Tsai , Jyun-Siang Huang
IPC分类号： G11C11/34
CPC分类号： G11C5/04 , G11C16/0416 , G11C16/10 , H01L27/11521 , H01L27/11568
摘要： An integrated circuit includes a memory cell structure including a first cell and a second cell. The first cell includes a first storage structure and a first gate over a substrate. The first gate is over the first storage structure. The second cell includes a second storage structure and a second gate over the substrate. The second gate is over the second storage structure. The first gate is separated from the second gate. A first doped region is adjacent to the first cell and is coupled to a first source. A second doped region is configured within the substrate and adjacent to the second cell. The second doped region is coupled to a second source. At least one third doped region is between the first cell and the second cell, wherein the third doped region is floating.
摘要翻译：集成电路包括包括第一单元和第二单元的存储单元结构。第一单元包括第一存储结构和衬底上的第一栅极。第一个门是第一个存储结构。第二单元包括第二存储结构和衬底上的第二栅极。第二个门是第二个存储结构。第一个门与第二个门分开。第一掺杂区域与第一单元相邻并且耦合到第一源极。第二掺杂区域被配置在衬底内且与第二单元相邻。第二掺杂区域耦合到第二源极。至少一个第三掺杂区域在第一单元和第二单元之间，其中第三掺杂区域是浮置的。

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