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21. 发明授权

US08090912B2 Multiprocessor system, system board, and cache replacement request handling method 有权
标题翻译：多处理器系统，系统板和缓存替换请求处理方法
公开(公告)号：US08090912B2
公开(公告)日：2012-01-03
申请号：US11790265
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0833
摘要： A request issued by the CPU is output from the local arbiter by way of the CPU bus and the CPU-issued request queue. The cache replacement request loop-back circuit determines at the loop-back determination circuit whether the outputted request is a cache replacement request or not. A request other than a cache replacement request is output onto the local bus. A cache replacement request is output to the selector and sent to the request handling section when there is no valid request on the global bus.
摘要翻译：通过CPU总线和CPU发出的请求队列，从本地仲裁器输出CPU发出的请求。高速缓存替换请求环回电路在环回确定电路中确定输出的请求是否是高速缓存替换请求。除了缓存替换请求之外的请求被输出到本地总线上。当全局总线上没有有效请求时，高速缓存替换请求被输出到选择器并发送到请求处理部分。

22. 发明申请

US20110026524A1 METHOD OF UPDATING ROUTING TABLE, DATA TRANSFER APPARATUS, AND PROGRAM 失效
标题翻译：更新路由表，数据传输设备和程序的方法
公开(公告)号：US20110026524A1
公开(公告)日：2011-02-03
申请号：US12846175
申请日：2010-07-29
申请人： Susumu Akiu , Takaharu Ishizuka , Takeshi Owaki , Atsushi Morosawa
发明人： Susumu Akiu , Takaharu Ishizuka , Takeshi Owaki , Atsushi Morosawa
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , G06F21/6209 , G06F2221/2141 , H04L45/02
摘要： A method of updating a routing table includes: receiving, from an issue-source node, a write packet that includes update data for updating the routing table; attempting to recognize, based upon contents of the write packet, a partition in which the issue-source node is included; determining whether to permit updating the routing table based upon (1) whether the partition including the source node is recognized and (2) whether port information and partition information in the update data are stored in the routing table; and updating the routing table when updating is permitted.
摘要翻译：更新路由表的方法包括：从发布源节点接收包括用于更新路由表的更新数据的写包; 基于写入包的内容，尝试识别包含发行源节点的分区; 基于（1）是否识别包括源节点的分区，以及（2）更新数据中的端口信息和分区信息是否存储在路由表中，确定是否允许更新路由表; 并且在允许更新时更新路由表。

23. 发明授权

US07805576B2 Information processing system, information processing board, and method of updating cache tag and snoop tag 有权
标题翻译：信息处理系统，信息处理板，缓存标签和窥探标签更新方法
公开(公告)号：US07805576B2
公开(公告)日：2010-09-28
申请号：US11740984
申请日：2007-04-27
申请人： Yuka Hosokawa , Takaharu Ishizuka , Makoto Hataida , Toshikazu Ueki
发明人： Yuka Hosokawa , Takaharu Ishizuka , Makoto Hataida , Toshikazu Ueki
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0831
摘要： In an information processing system loaded with a CPU having cache and a system controller having a copy of a tag of the cache (snoop tag), and the CPU not issuing replacement information about the cache tag, the number of WAYs of the snoop tags in the system controller is larger than the number of WAYs of the cache tags in the CPU to reduce a cache miss rate and suppress the degradation of performance by suppressing excess replacement of the cache tags in the CPU.
摘要翻译：在装载有具有高速缓存的CPU的信息处理系统和具有高速缓存（snoop标签）的标签的副本的系统控制器以及不发出关于高速缓存标签的替换信息的CPU的情况下，系统控制器大于CPU中缓存标签的方式数量，以减少高速缓存未命中率，并通过抑制CPU中高速缓存标签的过多替换来抑制性能下降。

24. 发明授权

US07779209B2 System controller, snoop tag modification method and information processing apparatus having snoop tag modification function 有权
标题翻译：系统控制器，snoop标签修改方法和具有snoop标签修改功能的信息处理设备
公开(公告)号：US07779209B2
公开(公告)日：2010-08-17
申请号：US11790263
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0822 , G06F12/0831
摘要： In a multiprocessor system, a system controller includes snoop tags which are copy information on cache tags retained by respective CPUs. If the same address is registered in S (Shared state) in the cache tag of each of the CPUs connected to the same CPU bus, the address is registered in S (Shared state) in only any one of the snoop tags corresponding to the CPUs in which the same address is registered.
摘要翻译：在多处理器系统中，系统控制器包括窥探标签，这些标签是由各个CPU保留的缓存标签上的复制信息。如果在连接到同一CPU总线的每个CPU的缓存标签中的S（共享状态）中登记相同的地址，则只在与CPU对应的任何一个snoop标签中的S（共享状态）中注册该地址其中注册了相同的地址。

25. 发明授权

US07467261B2 Dual storage apparatus and control method for the dual storage apparatus 有权
标题翻译：双存储设备的双存储设备和控制方法
公开(公告)号：US07467261B2
公开(公告)日：2008-12-16
申请号：US11237934
申请日：2005-09-29
申请人： Toshikazu Ueki , Takaharu Ishizuka , Takao Matsui , Makoto Hataida , Yuka Hosokawa
发明人： Toshikazu Ueki , Takaharu Ishizuka , Takao Matsui , Makoto Hataida , Yuka Hosokawa
IPC分类号： G06F12/00
CPC分类号： G06F11/1008 , G06F11/1666 , G06F11/20 , G11C5/005
摘要： A dual storage apparatus is provided that comprises a first and a second memories for respectively retaining a set of identical data and a selector for selecting either of the two (2) sets of the data respectively read from the first and the second memory based on a read control signal inputted into the selector, having a request management unit for, when the read control signal has been inputted, attaching an identifier for identifying the read control signal to the inputted read control signal and outputting the signal and the identifier; and a plurality of memory control units for each of the first and the second memories. The dual storage apparatus detects a synchronization error by verifying coincidence of the identifier attached by the request management unit and controls the selector such that the data from a system from which no synchronization error has been detected.
摘要翻译：提供了一种双存储装置，其包括用于分别保存一组相同数据的第一和第二存储器，以及用于选择从第一和第二存储器分别读取的两（2）组数据中的任何一个基于读取控制信号输入到选择器中，具有请求管理单元，当输入了读取控制信号时，将用于识别读取控制信号的标识符附加到所输入的读取控制信号并输出该信号和标识符; 以及用于第一和第二存储器中的每一个的多个存储器控制单元。双存储装置通过验证由请求管理单元附加的标识符的一致性来检测同步错误，并且控制选择器使得来自未检测到同步错误的系统的数据。

26. 发明申请

US20080046792A1 Node device, control device, control method and control program 有权
标题翻译：节点装置，控制装置，控制方法和控制程序
公开(公告)号：US20080046792A1
公开(公告)日：2008-02-21
申请号：US11785759
申请日：2007-04-19
申请人： Takashi Yamamoto , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takashi Yamamoto , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： H04L1/00
CPC分类号： H04L1/004 , H04L1/0082 , H04L2001/0097
摘要： A control device managing a plurality of nodes transmitting and receiving data containing an error correcting code, comprises means accepting, when any one of the nodes detects an uncorrectable error from the data containing the error correcting code, a signal transmitted by the node detecting the error, means judging from a record of the detection of a first node, when accepting the signal from a second node receiving data transmitted by the first node, whether or not the first node has detected the uncorrectable error from the data transmitted to the second node, and means stopping, when the first node has detected the uncorrectable error from the data transmitted to the second node, a process attributed to the acceptance of the signal from the second node.
摘要翻译：管理发送和接收包含纠错码的数据的多个节点的控制装置包括当任何一个节点从包含纠错码的数据中检测到不可校正的错误时，接收由检测到错误的节点发送的信号从第一节点接收到的数据接收来自第二节点的信号，从第一节点的检测记录中判断第一节点是否从发送到第二节点的数据检测到不可校正的错误，并且意味着当第一节点从发送到第二节点的数据中检测到不可校正的错误时，停止归因于来自第二节点的信号的接受的处理。

27. 发明申请

US20080046664A1 Control device for snoop tag 失效
标题翻译：窥探标签控制装置
公开(公告)号：US20080046664A1
公开(公告)日：2008-02-21
申请号：US11790272
申请日：2007-04-24
申请人： Makoto Hataida , Toshikazu Ueki , Takaharu Ishizuka , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Makoto Hataida , Toshikazu Ueki , Takaharu Ishizuka , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/123
摘要： To prevent a decrease in performance of controlling a snoop tag. A queue is stored with REPLACE target WAY information and an index as an entry associated with a REPLACE request received from a processor, the index stored in the queue is compared with an index of a subsequent READ request, and, as a result of the comparison, a process based on the index-coincident READ request is executed with respect to the snoop tag corresponding to a content of a cache memory of the processor. Further, the REPLACE target WAY information of the READ request is replaced with the WAY information in the index-coincident entry within the queue.
摘要翻译：以防止控制snoop标签的性能下降。存储REPLACE目标WAY信息和索引作为与从处理器接收到的REPLACE请求相关联的条目的队列，将存储在队列中的索引与后续READ请求的索引进行比较，并且作为比较的结果相对于与处理器的高速缓冲存储器的内容相对应的窥探标签，执行基于索引一致的READ请求的处理。此外，READ请求的REPLACE目标WAY信息被队列中符合条件的条目中的WAY信息所替代。

28. 发明申请

US20050125634A1 Processor and instruction control method 审中-公开
标题翻译：处理器和指令控制方法
公开(公告)号：US20050125634A1
公开(公告)日：2005-06-09
申请号：US11028338
申请日：2005-01-04
申请人： Takaharu Ishizuka
发明人： Takaharu Ishizuka
IPC分类号： G06F9/38 , G06F15/00
CPC分类号： G06F9/3861 , G06F9/30072 , G06F9/3842
摘要： The processor issues instructions including a branch instruction under a first identifier (ID=0) and speculatively executes the instructions by branch prediction. In the event of the detection of a branch error, the processor issues instructions in the correct direction under a second identifier (ID=1) subsequently to the erroneously issued instructions. After the completion of all the instructions prior to the branch error, the processor cancels the instructions erroneously issued by branch prediction to resume the issuance of instructions in the correct direction. The processor updates the identifiers (IDs) attached to the instructions after the occurrence of a branch error. This allows the processor to issue instructions in the correct direction without waiting for the completion of all the instructions prior to the branch instruction that caused the branch error, thus ensuring enhanced processing performance. Moreover, the processor needs only at least two identifiers to be attached to the instructions. This allows reduction in hardware volume.
摘要翻译：处理器发出包括在第一标识符（ID = 0）下的分支指令的指令，并通过分支预测推测地执行指令。在检测到分支错误的情况下，处理器在错误发出的指令之后的第二标识符（ID = 1）下以正确的方向发出指令。在分支错误之前完成所有指令之后，处理器取消由分支预测错误地发出的指令，以恢复正确方向的指令的发布。在发生分支错误之后，处理器更新附加到指令的标识符（ID）。这允许处理器以正确的方向发出指令，而不等待导致分支错误的分支指令之前的所有指令的完成，从而确保增强的处理性能。此外，处理器仅需要至少两个附加到指令的标识符。这允许减少硬件体积。

29. 发明授权

US08607103B2 Transmission/reception device, transmission device, reception device, and data transmission/reception method 失效
标题翻译：发送/接收设备，发送设备，接收设备和数据发送/接收方法
公开(公告)号：US08607103B2
公开(公告)日：2013-12-10
申请号：US13224995
申请日：2011-09-02
申请人： Takeshi Owaki , Takaharu Ishizuka , Susumu Akiu , Atsushi Morosawa
发明人： Takeshi Owaki , Takaharu Ishizuka , Susumu Akiu , Atsushi Morosawa
IPC分类号： G01R31/28
CPC分类号： G06F11/277
摘要： A transmission/reception device includes a transmission device that divides a plurality of connection lines into a plurality of groups, determines corresponding connection lines in the plurality of groups, determines a correspondence between test pattern and the connection line, and outputs the test pattern to the plurality of connection lines based on the correspondence between the test pattern and the connection line, and a reception device that receives the test pattern from the transmission device, compares bits in a same position of the test pattern received through a corresponding connection line in the plurality of groups based on the correspondence between the test pattern and the connection line, and generates erroneous connection line information indicating an erroneous connection line as a connection line in which an error has occurred in the plurality of connection lines based on a result of the comparison.
摘要翻译：发送/接收装置包括：将多条连接线划分为多个组的发送装置，确定多个组中的对应连接线，确定测试模式与连接线的对应关系，并将测试模式输出到基于测试图案和连接线之间的对应关系的多个连接线以及从发送装置接收测试图案的接收装置比较通过多个对应连接线接收的测试图案的相同位置中的比特基于测试图案和连接线之间的对应关系，并且基于比较结果，生成指示错误连接线的错误连接线信息作为连接线，其中已经在多条连接线中发生错误。

30. 发明授权

US08391184B2 Method of updating routing table, data transfer apparatus, and program 失效
标题翻译：更新路由表，数据传输装置和程序的方法
公开(公告)号：US08391184B2
公开(公告)日：2013-03-05
申请号：US12846175
申请日：2010-07-29
申请人： Susumu Akiu , Takaharu Ishizuka , Takeshi Owaki , Atsushi Morosawa
发明人： Susumu Akiu , Takaharu Ishizuka , Takeshi Owaki , Atsushi Morosawa
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , G06F21/6209 , G06F2221/2141 , H04L45/02
摘要： A method of updating a routing table includes: receiving, from an issue-source node, a write packet that includes update data for updating the routing table; attempting to recognize, based upon contents of the write packet, a partition in which the issue-source node is included; determining whether to permit updating the routing table based upon (1) whether the partition including the source node is recognized and (2) whether port information and partition information in the update data are stored in the routing table; and updating the routing table when updating is permitted.
摘要翻译：更新路由表的方法包括：从发布源节点接收包括用于更新路由表的更新数据的写包; 基于写入包的内容，尝试识别包含发行源节点的分区; 基于（1）是否识别包括源节点的分区，以及（2）更新数据中的端口信息和分区信息是否存储在路由表中，确定是否允许更新路由表; 并且在允许更新时更新路由表。

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