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21. 发明申请

US20190215078A1 Method And System For Waveguide Delay Based Equalization With Current And Optical Summing In Optical Communication 审中-公开
公开(公告)号：US20190215078A1
公开(公告)日：2019-07-11
申请号：US16355357
申请日：2019-03-15
申请人： Simon Pang , Joseph Balardeta
发明人： Simon Pang , Joseph Balardeta
IPC分类号： H04B10/66 , G02F1/225 , H04B10/25 , G02B6/34 , H04B10/67 , G02B6/42 , H04B10/69
CPC分类号： H04B10/66 , G02B6/34 , G02B6/4246 , G02B6/4295 , G02F1/225 , G02F2001/212 , H04B10/2504 , H04B10/67 , H04B10/6971
摘要： Methods and systems for waveguide delay based equalization with current and optical summing in optical communication are disclosed and may include an optoelectronic receiver including a directional coupler, two or more photodetectors, and one or more current mirrors. The optoelectronic receiver may be operable to: receive an input optical signal; split the input optical signal into first and second optical signals using the directional coupler; generate a first electrical from the first optical signal using a first photodetector; generate a second electrical signal from the second optical signal using a second photodetector; mirror the second electrical signal using the current mirror; and sum the first electrical signal with the amplified second electrical signal. The optoelectronic receiver may be operable to delay the first optical signal before generating the first electrical signal, using a waveguide delay.

22. 发明授权

US08478805B1 Frequency synthesis with low resolution rational division decomposition 有权
标题翻译：频率合成与低分辨率有理分解分解
公开(公告)号：US08478805B1
公开(公告)日：2013-07-02
申请号：US12985293
申请日：2011-01-05
申请人： Viet Do , Simon Pang
发明人： Viet Do , Simon Pang
IPC分类号： G06F1/02
CPC分类号： G06F1/022 , H03L7/193 , H03L7/1976
摘要： A method is provided for synthesizing signal frequencies using low resolution rational division decomposition in a frequency synthesis device. An integer numerator (n) and an integer denominator (d) ratio is reduced; n/d=IO(NO/DO)=IO+NO/DO=(IO+1)−(DO−NO)/DO, and where NO/DO
摘要翻译：提供一种用于在频率合成装置中使用低分辨率有理分解分解合成信号频率的方法。减小整数分子（n）和整数分母（d）比率; n / d = IO（NO / DO）= IO + NO / DO =（IO + 1） - （DO-NO）/ DO，NO / DO <1，NO和DO为整数。 NO减少; （Nn / Dn）= In + Nn / Dn =（In + 1） - （Dn-Nn）/ Dn，其中In，Nn和Dn为整数，Nn / Dn <1。 In，Nn和Dn用于创建最终的分子除数。 DO减少; Nd = Dd（Nd / Dd）= Id + Nd / Dd =（Id + 1） - （Dd-Nd）/ Dd，其中Id，Nd和Dd为整数，Nd / Dd <1。 Id，Nd和Dd用于创建最终分母除数。最后，IO，最终的分子除数和最终的分母除数用于创建最终的除数。

23. 发明授权

US08346840B2 Flexible accumulator for rational division 有权
标题翻译：灵活的蓄能器进行合理划分
公开(公告)号：US08346840B2
公开(公告)日：2013-01-01
申请号：US11954325
申请日：2007-12-12
申请人： Viet Linh Do , Simon Pang
发明人： Viet Linh Do , Simon Pang
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F2207/5353
摘要： A system and method are provided for rational division. The method accepts accepting a binary numerator and a binary denominator. A binary first sum is created of the numerator and a binary first count from a previous cycle. A binary first difference is created between the first sum and the denominator. In response to comparing the first sum with the denominator, and first carry bit is generated and added to a first binary sequence. The first binary sequence is used to generate a k-bit quotient. Typically, the denominator value is larger than the numerator value. In one aspect, the numerator and denominator form a rational number. Alternately, the numerator may be an n-bit bit value formed as either a repeating or non-repeating sequence, and the denominator is an (n+1)-bit number with a decimal value of 2(n+1).
摘要翻译：提供了一种合理划分的系统和方法。该方法接受接受二进制分子和二进制分母。由分子创建二进制第一和，并从上一个循环创建二进制第一个计数。在第一个总和和分母之间创建二进制的第一个差异。响应于将第一和与分母进行比较，并且生成第一进位位并将其相加到第一二进制序列。第一个二进制序列用于生成k比特商。通常，分母值大于分子值。一方面，分子和分母形成一个有理数。或者，分子可以是形成为重复序列或非重复序列的n位比特值，分母是小数值为2（n + 1）的（n + 1）位数字。

24. 发明授权

US08138801B1 Frequency crossing detection using opposing pattern detectors 有权
标题翻译：使用相反的图案检测器进行频率检测
公开(公告)号：US08138801B1
公开(公告)日：2012-03-20
申请号：US12892723
申请日：2010-09-28
申请人： Viet Do , Simon Pang
发明人： Viet Do , Simon Pang
IPC分类号： H03D13/00
CPC分类号： H03D13/003
摘要： A system and method are provided for matching a signal (compClk) to a particular frequency band in a multiband communications device. The method accepts a compClk signal, a frequency source is selected from sources collectively covering a range of frequency bands, and a reference clock is supplied from the selected source. If the frequency of the compClk is greater than the reference clock frequency, a high frequency window sampler supplies a first frequency pattern detector output signal (fpdOut—1). Simultaneously, a low frequency window sampler compares the compClk signal with the reference clock. If the frequency of the compClk is less than the reference clock frequency, the low frequency window sampler supplies a second frequency pattern detector output signal (fpdOut—2). The selected frequency source is compared to fpdOut—1 and fpdOut—2 signals, and a determination is made as to whether the selected frequency source coarsely matches the compClk frequency.
摘要翻译：提供了一种用于将信号（compClk）与多频带通信设备中的特定频带进行匹配的系统和方法。该方法接收compClk信号，从共同覆盖频带范围的源选择频率源，并且从所选择的源提供参考时钟。如果compClk的频率大于参考时钟频率，则高频窗口采样器提供第一频率模式检测器输出信号（fpdOut-1）。同时，低频窗口采样器将compClk信号与参考时钟进行比较。如果compClk的频率小于参考时钟频率，则低频窗口采样器提供第二频率模式检测器输出信号（fpdOut-2）。将所选频率源与fpdOut-1和fpdOut-2信号进行比较，并确定所选择的频率源是否与compClk频率粗略匹配。

25. 发明授权

US08106808B1 Successive time-to-digital converter for a digital phase-locked loop 有权
标题翻译：用于数字锁相环的连续时间 - 数字转换器
公开(公告)号：US08106808B1
公开(公告)日：2012-01-31
申请号：US12841131
申请日：2010-07-21
申请人： Hanan Cohen , Simon Pang
发明人： Hanan Cohen , Simon Pang
IPC分类号： H03M1/50
CPC分类号： G04F10/005 , H03L7/085 , H03L2207/50
摘要： A successive time-to-digital converter (STDC) method is provided for supplying a digital word representing the ratio between a phase-locked loop PLL frequency synthesizer signal and a reference clock. The number of frequency synthesizer clock cycles per reference clock cycle is counted. A first difference is measured between a reference clock period and a corresponding frequency synthesizer clock period. In response to the first measurement, a second difference is measured between a delayed reference clock period and the corresponding frequency synthesizer clock period, where the second difference is less than the first difference. A third difference is measured as a time duration between the delayed reference clock period and the corresponding delayed frequency synthesizer clock period. The first and third difference measurements and the count of the number of frequency synthesizer clock cycles per reference clock cycle are used to calculate a digital error signal supplied to the frequency synthesizer.
摘要翻译：提供了连续的时间 - 数字转换器（STDC）方法，用于提供表示锁相环PLL频率合成器信号和参考时钟之间的比率的数字字。每个参考时钟周期的频率合成器时钟周期数被计数。在参考时钟周期和对应的频率合成器时钟周期之间测量第一个差异。响应于第一测量，在延迟的参考时钟周期与相应的频率合成器时钟周期之间测量第二个差异，其中第二个差值小于第一个差值。第三个差值被测量为延迟的参考时钟周期与相应的延迟频率合成器时钟周期之间的持续时间。使用第一和第三差分测量以及每个参考时钟周期的频率合成器时钟周期数的计数来计算提供给频率合成器的数字误差信号。

26. 发明授权

US08094754B2 Frequency hold mechanism in a clock and data recovery device 有权
标题翻译：时钟和数据恢复设备中的频率保持机制
公开(公告)号：US08094754B2
公开(公告)日：2012-01-10
申请号：US12327776
申请日：2008-12-03
申请人： Mehmet Mustafa Eker , Simon Pang , Viet Linh Do , Hongming An , Philip Michael Clovis
发明人： Mehmet Mustafa Eker , Simon Pang , Viet Linh Do , Hongming An , Philip Michael Clovis
IPC分类号： H03D3/24
CPC分类号： H04L7/033 , H03L7/087 , H03L7/10 , H03L7/1976 , H03L7/22
摘要： A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency. Using a rotational frequency detector (RFD), the second communication signal, and the second synthesized signal, a second synthesized signal is generated having an output frequency equal to second frequency.
摘要翻译：提供了一种用于在时钟和数据恢复（CDR）设备频率合成器中保持非同步通信信号的频率的系统和方法。该方法最初获取具有第一频率的非同步第一通信信号的相位，并且将第一合成信号除以所选频率比值，产生频率等于参考信号频率的频率检测信号。响应于丢失第一通信信号并随后接收具有非预定第二频率的第二通信信号，基于第二频率相同或接近第一频率的假设，从存储器检索频率比值。使用相位频率检测器（PFD），参考信号和频率比值，产生具有等于第一频率的输出频率的第二合成信号。使用旋转频率检测器（RFD），第二通信信号和第二合成信号，生成具有等于第二频率的输出频率的第二合成信号。

27. 发明申请

US20090147901A1 Auto Frequency Acquisition Maintenance in a Clock and Data Recovery Device 有权
标题翻译：时钟和数据恢复设备中的自动采集维护
公开(公告)号：US20090147901A1
公开(公告)日：2009-06-11
申请号：US12372946
申请日：2009-02-18
申请人： Viet Linh Do , Philip Michael Clovis , Michael Hellmer , Mehmet Mustafa Eker , Hongming An , Simon Pang
发明人： Viet Linh Do , Philip Michael Clovis , Michael Hellmer , Mehmet Mustafa Eker , Hongming An , Simon Pang
IPC分类号： H04L7/00
CPC分类号： H04L7/0331 , H03L7/0891 , H03L7/095 , H03L7/113 , H03L7/1976 , H04L7/0004
摘要： A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired.
摘要翻译：提供了一种用于时钟和数据恢复（CDR）设备中的自动频率采集维护的系统和方法。在自动频率采集（AFA）模式中，该方法使用相位检测器（PHD）来获取具有初始第一频率的非同步输入通信信号的相位。在信号失去锁定/丢失（LOL / LOS）信号被断言的情况下，从存储器检索频率比值。使用相位频率检测器（PFD），参考信号和频率比值，产生合成信号。响应于使用PFD产生合成信号并且LOL / LOS信号被无效，旋转频率检测器（RFD）用于产生具有等于输入通信信号频率的频率的合成信号。随着LOL / LOS信号的持续消除，PHD被使能，并且获取输入信号的相位。

28. 发明申请

US20090092213A1 Frequency Hold Mechanism in a Clock and Data Recovery Device 有权
标题翻译：时钟和数据恢复设备中的频率保持机制
公开(公告)号：US20090092213A1
公开(公告)日：2009-04-09
申请号：US12327776
申请日：2008-12-03
申请人： Mehmet Mustafa Eker , Simon Pang , Viet Linh Do , Hongming An , Philip Michael Clovis
发明人： Mehmet Mustafa Eker , Simon Pang , Viet Linh Do , Hongming An , Philip Michael Clovis
IPC分类号： H04L7/04
CPC分类号： H04L7/033 , H03L7/087 , H03L7/10 , H03L7/1976 , H03L7/22
摘要： A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency. Using a rotational frequency detector (RFD), the second communication signal, and the second synthesized signal, a second synthesized signal is generated having an output frequency equal to second frequency.
摘要翻译：提供了一种用于在时钟和数据恢复（CDR）设备频率合成器中保持非同步通信信号的频率的系统和方法。该方法最初获取具有第一频率的非同步第一通信信号的相位，并且将第一合成信号除以所选频率比值，产生频率等于参考信号频率的频率检测信号。响应于丢失第一通信信号并随后接收具有非预定第二频率的第二通信信号，基于第二频率相同或接近第一频率的假设，从存储器检索频率比值。使用相位频率检测器（PFD），参考信号和频率比值，产生具有等于第一频率的输出频率的第二合成信号。使用旋转频率检测器（RFD），第二通信信号和第二合成信号，生成具有等于第二频率的输出频率的第二合成信号。

29. 发明授权

US08762436B1 Frequency synthesis with low resolution rational division 有权
标题翻译：低分辨率合理分频的频率合成
公开(公告)号：US08762436B1
公开(公告)日：2014-06-24
申请号：US12972255
申请日：2010-12-17
申请人： Viet Do , Simon Pang
发明人： Viet Do , Simon Pang
IPC分类号： G06F7/52 , G06F1/02
CPC分类号： H03L7/1976 , G06F7/68 , H03K21/40 , H03K23/486 , H03L7/18
摘要： A method is provided for synthesizing signal frequencies using low resolution rational division. A reference frequency value and synthesized frequency value are accepted. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (n) and an integer value denominator (d) are determined, with n/d=I(N/D)=I+N/D=(I+1)−(D−N)/D), and where N/D
摘要翻译：提供了一种使用低分辨率合理除法合成信号频率的方法。参考频率值和合成频率值被接受。响应于将合成频率值除以参考频率值，确定整数值分子（n）和整数分母（d），其中n / d = I（N / D）= I + N / D = （I + 1） - （D-N）/ D），其中N / D <1。累加器产生（D-N）和来自前一个循环的计数的和，并产生和和分母之间的差异。将总和与分母进行比较，并产生第一进位位。第一进位位的补码被加到第一个二进制序列中，第一个二进制序列用于产生一个k位的商。从（I + 1）中减去k位商以产生除数。

30. 发明授权

US08666011B1 Jitter-attenuated clock using a gapped clock reference 有权
标题翻译：使用有间隙时钟参考的抖动衰减时钟
公开(公告)号：US08666011B1
公开(公告)日：2014-03-04
申请号：US13091052
申请日：2011-04-20
申请人： Viet Do , Simon Pang
发明人： Viet Do , Simon Pang
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H04J3/076
摘要： A system and method are provided for generating a jitter-attenuated clock using an asynchronous gapped clock source. The method accepts a first reference clock having a first frequency. Using the first reference clock, an asynchronous gapped clock is generated having an average second frequency less than the first frequency. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock. Then, DN and DD are averaged. In response to the averaging, an averaged numerator (AN) and an averaged denominator (AD) are generated. Finally, the first frequency (first reference clock) is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency.
摘要翻译：提供了一种使用异步间隔时钟源来产生抖动衰减时钟的系统和方法。该方法接受具有第一频率的第一参考时钟。使用第一参考时钟，产生具有小于第一频率的平均第二频率的异步间隔时钟。对于有间隙的时钟，迭代地计算动态分子（DN）和动态分母（DD）。然后，DN和DD被平均。响应于平均，生成平均分子（AN）和平均分母（AD）。最后，将第一频率（第一参考时钟）乘以AN / AD的比率以产生具有第二频率的抖动衰减的第二时钟。

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