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21. 发明申请

US20090285275A1 SIGNAL ADJUSTMENT RECEIVER CIRCUITRY 失效
标题翻译：信号调整接收机电路
公开(公告)号：US20090285275A1
公开(公告)日：2009-11-19
申请号：US12511022
申请日：2009-07-28
申请人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev , Tin H. Lai
发明人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev , Tin H. Lai
IPC分类号： H04L27/01
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.
摘要翻译：公开了一种用于调整从通信路径接收的信号的系统和方法。接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。对于低频调整，控制块控制信号归一化块中的归一化信号幅度。以这种方式，在信号归一化块中执行低频内容的受控调整。

22. 发明授权

US07590207B1 Modular serial interface in programmable logic device 有权
标题翻译：可编程逻辑器件中的模块化串行接口
公开(公告)号：US07590207B1
公开(公告)日：2009-09-15
申请号：US11256346
申请日：2005-10-20
申请人： Sergey Y Shumarayev , Rakesh H Patel , Wilson Wong , Tim Tri Hoang , William Bereza
发明人： Sergey Y Shumarayev , Rakesh H Patel , Wilson Wong , Tim Tri Hoang , William Bereza
IPC分类号： H04L7/00
CPC分类号： H03L7/087 , H04J3/0688 , H04L7/033
摘要： A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accomplished by disabling the data loop of clock-data recovery circuitry in the channel, and reconfiguring the reference loop to operate as a loop circuit. In addition, instead of providing a high-speed quad interface having four channels and one or more clock management units (CMUs), a more flexible interface having five or more channels can be provided, and when it is desired to use the interface as a high-speed quad interface, one or more channels can be configured as loop circuits to function as CMUs.
摘要翻译：用于可编程逻辑器件的串行接口可以用作传统的高速四边形接口，但是也允许单独的通道（如果不另外使用）被可编程地配置为环路电路（例如，锁相环）。这是通过禁用通道中的时钟数据恢复电路的数据循环来实现的，并且重新配置参考环路以用作循环电路。此外，不是提供具有四个通道的高速四边形接口和一个或多个时钟管理单元（CMU），而是可以提供具有五个或更多个通道的更灵活的接口，并且当希望将接口用作高速四通道接口，一个或多个通道可以配置为循环电路，用作CMU。

23. 发明授权

US07538578B2 Multiple data rates in programmable logic device serial interface 失效
标题翻译：可编程逻辑器件串行接口中的多个数据速率
公开(公告)号：US07538578B2
公开(公告)日：2009-05-26
申请号：US11177034
申请日：2005-07-08
申请人： Ramanand Venkata , Chong H Lee , Rakesh H Patel
发明人： Ramanand Venkata , Chong H Lee , Rakesh H Patel
IPC分类号： H03K19/177 , G06F13/42
CPC分类号： H03K19/17744
摘要： A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.
摘要翻译：用于可编程逻辑器件的串行接口可以根据各种通信协议进行操作，并且包括接收器部分和发射器部分。接收器部分至少包括字或字节对准级，去偏移级，速率补偿或匹配级，填充协议解码器级（例如，8B / 10B解码器电路或64B / 66B解码器电路），字节解串器阶段，字节重排阶段和相位补偿阶段。发射机部分至少包括相位补偿级，字节解串器级和填充协议编码器级（例如，8B / 10B编码器电路或64B / 66B编码器电路）。每个阶段可能有多次出现相关的电路。选择电路，例如多路复用器，为所使用的协议选择适当的阶段和每个阶段内的电路。

24. 发明申请

US20080298476A1 APPARATUS FOR ALL-DIGITAL SERIALIZER-DE-SERIALIZER AND ASSOCIATED METHODS 有权
标题翻译：全数字序列化器和相关方法的设备
公开(公告)号：US20080298476A1
公开(公告)日：2008-12-04
申请号：US12119406
申请日：2008-05-12
申请人： William W. Bereza , Tad Kwasniewski , Rakesh H. Patel
发明人： William W. Bereza , Tad Kwasniewski , Rakesh H. Patel
IPC分类号： H04B3/00 , H04L7/00
CPC分类号： H03M9/00 , H03K5/133 , H03K5/15026 , H03K2005/00032 , H03L7/07 , H03L7/0814 , H03L7/091 , H03L7/0991 , H04J3/062 , H04J3/0685
摘要： An all-digital serializer-de-serializer includes an all-digital clock multiplier unit (CMU) circuit, an all-digital clock and data recovery (CDR) circuit, a multiplexer (MUX), and a demultiplexer (DeMUX). The all-digital clock and data recovery (CDR) circuit couples to the all-digital clock multiplier unit (CMU) circuit. The multiplexer (MUX), couples to all-digital clock multiplier unit (CMU) circuit, and serializes data. The demultiplexer (DeMUX), couples to the all-digital clock and data recovery (CDR) circuit, and de-serializes data.
摘要翻译：全数字串行器 - 解串器包括全数字时钟倍增器单元（CMU）电路，全数字时钟和数据恢复（CDR）电路，多路复用器（MUX）和解复用器（DeMUX）。全数字时钟和数据恢复（CDR）电路耦合到全数字时钟乘法器单元（CMU）电路。多路复用器（MUX）耦合到全数字时钟乘法器单元（CMU）电路，并串行化数据。解复用器（DeMUX）耦合到全数字时钟和数据恢复（CDR）电路，并且对数据进行反序列化。

25. 发明授权

US07304498B2 Clock circuitry for programmable logic devices 有权
标题翻译：可编程逻辑器件的时钟电路
公开(公告)号：US07304498B2
公开(公告)日：2007-12-04
申请号：US11432419
申请日：2006-05-10
申请人： William W Bereza , Shoujun Wang , Rakesh H Patel
发明人： William W Bereza , Shoujun Wang , Rakesh H Patel
IPC分类号： H01L25/00
CPC分类号： H03L7/07 , H03K19/1774 , H03K19/17744 , H03M9/00
摘要： Data transmitter circuitry on a programmable logic device (“PLD”) includes a plurality of channels of serializer circuitry, and a plurality of clock multiplier units (“CMUs”), each of which is associated with a respective subplurality of the serializer channels. Each CMU includes multiple reference clock signal sources, multiple phase-locked loop (“PLL”) circuits, and circuitry for allowing any PLL to get its reference input from any of the reference sources. Raw and centrally processed clock signals produced by each CMU are distributed to the serializer channels associated with that CMU and, at least in the case of the centrally processed signals, to the serializer channels associated with another CMU. The signal that controls release of parallel data to each serializer channel can be an output signal of that channel, or it can be an output signal of any CMU from which that channel can get a clock signal.
摘要翻译：可编程逻辑器件（“PLD”）上的数据发射器电路包括多个串行器电路的通道，以及多个时钟倍增器单元（“CMU”），每个时钟倍增器单元与串行器通道的相应子模式相关联。每个CMU包括多个参考时钟信号源，多个锁相环（“PLL”）电路和用于允许任何PLL从任何参考源获得其参考输入的电路。由每个CMU产生的原始和中央处理的时钟信号被分配到与该CMU相关联的串行器通道，并且至少在集中处理的信号的情况下分配给与另一个CMU相关联的串行器通道。控制并行数据释放到每个串行器通道的信号可以是该通道的输出信号，或者它可以是任何CMU的输出信号，该信道可以从该通道获得时钟信号。

26. 发明授权

US07151397B2 Voltage controlled oscillator programmable delay cells 有权
公开(公告)号：US07151397B2
公开(公告)日：2006-12-19
申请号：US10873578
申请日：2004-06-22
申请人： Stjepan W Andrasic , Rakesh H Patel , Chong H Lee
发明人： Stjepan W Andrasic , Rakesh H Patel , Chong H Lee
IPC分类号： H03H11/26 , H03B5/24
CPC分类号： H03K5/133 , H03K3/0322 , H03K3/354 , H03L7/0995 , H03L7/10
摘要： A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator (“VCO”) includes a plurality of such delay cells connected in a closed loop series. Phase locked loop (“PLL”) circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.

27. 发明授权

US06515507B1 Control pin for specifying integrated circuit voltage levels 有权
标题翻译：用于指定集成电路电压电平的控制引脚
公开(公告)号：US06515507B1
公开(公告)日：2003-02-04
申请号：US09607569
申请日：2000-06-29
申请人： Rakesh H. Patel , Thomas H. White
发明人： Rakesh H. Patel , Thomas H. White
IPC分类号： G06F738
CPC分类号： G11C16/30 , G11C5/147 , G11C16/20 , H03K3/011 , H03K3/0315
摘要： An integrated circuit has one or more external control pins to control and indicate which of two or more different VCC or other voltage levels will be used. The control pin receives a logic signal, high or low, and draws zero static power. A user can use the integrated circuit with two or more VCC voltage levels by indicating which voltage level at the control pins. In a specific embodiment, the integrated circuit has nonvolatile memory cells such as EEPROM or Flash cells that a configurable and reconfigurable using on-chip programming circuitry. The programming circuitry may generate and use superhigh or high voltages, higher than the VCC voltage.
摘要翻译：集成电路具有一个或多个外部控制引脚，用于控制并指示将使用两个或多个不同VCC或其他电压电平中的哪一个。控制引脚接收高或低的逻辑信号，并绘制零静态功率。用户可以通过指示控制引脚上的哪个电压电平，使用具有两个或多个VCC电压电平的集成电路。在具体实施例中，集成电路具有非易失性存储单元，例如EEPROM或闪存单元，其是使用片上编程电路的可配置和可重新配置的。编程电路可以产生和使用高于VCC电压的超高电压或高电压。

28. 发明授权

US06317367B1 FPGA with on-chip multiport memory 有权
标题翻译： FPGA具有片内多端口存储器
公开(公告)号：US06317367B1
公开(公告)日：2001-11-13
申请号：US09748088
申请日：2000-12-21
申请人： Stephen P. Sample , Michael R. Butts , Kevin A. Norman , Rakesh H. Patel , Chao Chiang Chen
发明人： Stephen P. Sample , Michael R. Butts , Kevin A. Norman , Rakesh H. Patel , Chao Chiang Chen
IPC分类号： G11C700
CPC分类号： H03K19/17772 , G11C7/1006 , G11C7/1075 , G11C7/22 , G11C8/16 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (“FPGA”), as described herein has multiple blocks of multiported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multiported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.
摘要翻译：如本文所述的用于实现可重配置逻辑的集成电路，例如现场可编程门阵列（“FPGA”）具有多个多端口存储器块。存储器具有多个读取端口和多个写入端口。多端口存储器的每个端口可以配置为与其他端口的宽度和深度独立且独立的宽度和深度。该存储器还包括用于对存储器的内容进行同步快照或将存储器加载到初始状态的端口。存储器共享由低级逻辑元件使用的路由线，从而减轻了为了满足存储器需求而向互连网络添加路由线路的需要。

29. 发明授权

US5870410A Diagnostic interface system for programmable logic system development 失效
标题翻译：用于可编程逻辑系统开发的诊断接口系统
公开(公告)号：US5870410A
公开(公告)日：1999-02-09
申请号：US840357
申请日：1997-04-28
申请人： Kevin A. Norman , Rakesh H. Patel , Stephen P. Sample , Michael R. Butts
发明人： Kevin A. Norman , Rakesh H. Patel , Stephen P. Sample , Michael R. Butts
IPC分类号： G01R31/28
CPC分类号： G01R31/318516
摘要： An diagnostic interface system for a programmable logic system is disclosed. The diagnostic interface system provides an efficient and flexible mechanism for accessing internal nodes of programmable logic devices (PLDs) to facilitate debugging and troubleshooting of the programmable logic system. The interface system includes a diagnostic data bus connecting external I/O pins to various diagnostic data and address registers that connect to the internal circuitry of a PLD. A diagnostics controller controls the various diagnostic resources in response to user supplied control data.
摘要翻译：公开了一种用于可编程逻辑系统的诊断接口系统。诊断接口系统为访问可编程逻辑器件（PLD）的内部节点提供了一种有效且灵活的机制，以便于可编程逻辑系统的调试和故障排除。接口系统包括将外部I / O引脚连接到各种诊断数据的诊断数据总线和连接到PLD内部电路的地址寄存器。诊断控制器根据用户提供的控制数据控制各种诊断资源。

30. 发明授权

US5869980A Programming programmable transistor devices using state machines 失效
标题翻译：使用状态机编程可编程晶体管器件
公开(公告)号：US5869980A
公开(公告)日：1999-02-09
申请号：US896146
申请日：1997-07-17
申请人： Michael Hsiao-Ming Chu , Rakesh H. Patel
发明人： Michael Hsiao-Ming Chu , Rakesh H. Patel
IPC分类号： G01R31/3185 , G06F17/50 , G11C29/32 , G11C29/44 , G11C29/48 , G11C29/52 , H03K19/177
CPC分类号： G11C29/48 , G01R31/318561 , G06F17/5054 , G11C29/44 , G11C29/52 , G11C29/32
摘要： An integrated circuit with programmable transistors is programmed via a state machine on the integrated circuit. For example, the integrated circuit may be a programmable logic device, and the state machine may be a JTAG state machine. Each integrated circuit may have on it a register containing data indicating how long a particular programming operation should continue in order to be successful for that circuit. External programming control apparatus first reads that data and then at least partly bases the timing of programming instructions applied to the integrated circuit on that data. The integrated circuit may have an on-board programming voltage generating circuit which is turned on only by appropriate instructions from the external programming control apparatus. The external programming control apparatus controls the sequence and timing of all programming operations via the state machine port of the integrated circuit.
摘要翻译：具有可编程晶体管的集成电路通过集成电路上的状态机进行编程。例如，集成电路可以是可编程逻辑器件，并且状态机可以是JTAG状态机。每个集成电路可以在其上具有包含指示特定编程操作应该持续多久才能使该电路成功的数据的寄存器。外部编程控制装置首先读取数据，然后至少部分地基于应用于该数据的集成电路的编程指令的定时。集成电路可以具有仅通过来自外部编程控制装置的适当指令而导通的板上编程电压产生电路。外部编程控制装置经由集成电路的状态机端口控制所有编程操作的顺序和定时。

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