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1. 发明授权

US09083365B1 Thermometer-code-to-binary encoders 有权
标题翻译：温度计代码到二进制编码器
公开(公告)号：US09083365B1
公开(公告)日：2015-07-14
申请号：US12696027
申请日：2010-01-28
申请人： Ping Xiao , William W. Bereza , Weiying Ding , Mohsen Moussavi
发明人： Ping Xiao , William W. Bereza , Weiying Ding , Mohsen Moussavi
IPC分类号： H03M1/06 , H03M7/16 , H03M1/08
CPC分类号： H03M1/0809 , H03M7/165
摘要： An encoder is provided for converting thermometer code data with bubbles to binary format. An integrated circuit may have circuitry such as digital phase-locked loop circuitry. A thermometer code data word may be used as a control signal for the circuitry. It may be desirable to monitor the thermometer code data word for testing or for downstream processing by control logic on the integrated circuit. The encoder performs thermometer code to binary encoding without requiring that the thermometer code be error corrected to remove bubbles. A bubble detection circuit may be used to detect when the thermometer code data contains bubbles. The encoder may use carry look-ahead adders and pipeline stages.
摘要翻译：提供了一种用于将温度计代码数据与气泡转换为二进制格式的编码器。集成电路可以具有诸如数字锁相环电路的电路。温度计代码数据字可以用作电路的控制信号。可能希望通过集成电路上的控制逻辑来监测温度计代码数据字进行测试或下游处理。编码器将温度计代码执行二进制编码，而不需要对温度计代码进行纠错以消除气泡。可以使用气泡检测电路来检测温度计代码数据何时包含气泡。编码器可以使用前置加法器和流水线级。

2. 发明授权

US08654898B2 Digital equalizer for high-speed serial communications 有权
标题翻译：数字均衡器，用于高速串行通信
公开(公告)号：US08654898B2
公开(公告)日：2014-02-18
申请号：US12117515
申请日：2008-05-08
申请人： William W. Bereza , Albert Vareljian , Rakesh H. Patel
发明人： William W. Bereza , Albert Vareljian , Rakesh H. Patel
IPC分类号： H04L27/01
CPC分类号： H04L25/0272
摘要： Incoming data at a high-speed serial receiver is digitized and then digital signal processing (DSP) techniques may be used to perform digital equalization. Such digital techniques may be used to correct various data anomalies. In particular, in a multi-channel system, where crosstalk may be of concern, knowledge of the characteristics of the other channels, or even the data on those channels, may allow crosstalk to be subtracted out. Knowledge of data channel geometries, particularly in the context of backplane transmissions, may allow echoes and reflections caused by connectors to be subtracted out. As data rates increase, fractional rate processing can be employed. For example, the analog-to-digital conversion can be performed at half-rate and then two DSPs can be used in parallel to maintain throughput at the higher initial clock rate. At even higher rates, quadrature techniques can allow analog-to-digital conversion at quarter-rate, with four DSPs used in parallel.
摘要翻译：数字化高速串行接收机的传入数据，然后可以使用数字信号处理（DSP）技术来执行数字均衡。这样的数字技术可以用于校正各种数据异常。特别地，在可能涉及串扰的多通道系统中，其他通道的特性或甚至这些通道上的数据的知识可能允许减去串扰。对数据通道几何的了解，特别是在背板传输的上下文中，可能允许减去连接器引起的回波和反射。随着数据速率的提高，可以采用分数速率处理。例如，可以以半速率执行模数转换，然后可以并行使用两个DSP，以在较高的初始时钟速率下维持吞吐量。在更高的速率下，正交技术可以允许以四分之一速率进行模数转换，并行使用四个DSP。

3. 发明申请

US20100073054A1 Techniques For Digital Loop Filters 有权
标题翻译：数字环路滤波器技术
公开(公告)号：US20100073054A1
公开(公告)日：2010-03-25
申请号：US12272266
申请日：2008-11-17
申请人： William W. Bereza , Mohsen Moussavi , Charles E. Berndt
发明人： William W. Bereza , Mohsen Moussavi , Charles E. Berndt
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , H03L7/099 , H03L7/107
摘要： A digital loop filter includes a fine control circuit and a coarse control circuit. The fine control circuit adjusts a phase of a feedback clock signal by a first phase adjustment in response to a first phase error signal that indicates a sign of a phase error between a reference clock signal and the feedback clock signal. The coarse control circuit adjusts the phase of the feedback clock signal by a second phase adjustment in response to a second phase error signal. The second phase adjustment is larger than the first phase adjustment. The second phase error signal indicates a magnitude of a phase error between the reference clock signal and the feedback clock signal.
摘要翻译：数字环路滤波器包括精细控制电路和粗略控制电路。精细控制电路响应于指示参考时钟信号和反馈时钟信号之间的相位误差的符号的第一相位误差信号，通过第一相位调整来调整反馈时钟信号的相位。粗调控制电路响应于第二相位误差信号，通过第二相位调整来调节反馈时钟信号的相位。第二相位调整大于第一相位调整。第二相位误差信号表示参考时钟信号和反馈时钟信号之间的相位误差的大小。

4. 发明申请

US20090309240A1 RETURN LOSS TECHNIQUES IN WIREBOND PACKAGES FOR HIGH-SPEED DATA COMMUNICATIONS 有权
标题翻译：用于高速数据通信的WIREBOND包中的返回丢失技术
公开(公告)号：US20090309240A1
公开(公告)日：2009-12-17
申请号：US12139388
申请日：2008-06-13
申请人： William W. Bereza , Hong Shi
发明人： William W. Bereza , Hong Shi
IPC分类号： H01L23/52
CPC分类号： H01L24/49 , H01L23/66 , H01L24/02 , H01L24/48 , H01L2223/6611 , H01L2224/05554 , H01L2224/45015 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/484 , H01L2224/49113 , H01L2224/49171 , H01L2224/4943 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/19051 , H01L2924/19107 , H01L2924/20752 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A wirebond package configured to reduce wirebond return loss is presented. An integrated circuit of interest with rows of bonding pads is bonded to a surface of the wirebond package. The surface of wirebond package has columns of bonding pads, which are configured to transmit or receive signals, power, and ground to and/or from the wirebond package to the integrated circuit. Corresponding die pads on the integrated circuit and bonding pads of the wirebond package are coupled using conductive lines. The conductive lines carrying the active signal has coplanar adjacent ground lines on opposing sides of active signal line and the distance between active signal line and the coplanar adjacent ground lines is tapered.
摘要翻译：提出了一种配置为减少引线键返回损耗的引线键合封装。感兴趣的一排结合焊盘的集成电路被结合到引线键合封装的表面。引线键合封装的表面具有接合焊盘的列，其被配置为向引线封装向集成电路发送或接收信号，电源和接地。集成电路上的对应的芯片焊盘和引线键合封装的焊盘使用导线连接。承载有源信号的导线在有源信号线的相对侧具有共面相邻的接地线，并且有源信号线与共面相邻接地线之间的距离是渐缩的。

5. 发明授权

US08212610B2 Techniques for digital loop filters 有权
标题翻译：数字环路滤波器技术
公开(公告)号：US08212610B2
公开(公告)日：2012-07-03
申请号：US12272266
申请日：2008-11-17
申请人： William W. Bereza , Mohsen Moussavi , Charles E. Berndt
发明人： William W. Bereza , Mohsen Moussavi , Charles E. Berndt
IPC分类号： H03B1/00
CPC分类号： H03L7/093 , H03L7/099 , H03L7/107
摘要： A digital loop filter includes a fine control circuit and a coarse control circuit. The fine control circuit adjusts a phase of a feedback clock signal by a first phase adjustment in response to a first phase error signal that indicates a sign of a phase error between a reference clock signal and the feedback clock signal. The coarse control circuit adjusts the phase of the feedback clock signal by a second phase adjustment in response to a second phase error signal. The second phase adjustment is larger than the first phase adjustment. The second phase error signal indicates a magnitude of a phase error between the reference clock signal and the feedback clock signal.
摘要翻译：数字环路滤波器包括精细控制电路和粗略控制电路。精细控制电路响应于指示参考时钟信号和反馈时钟信号之间的相位误差的符号的第一相位误差信号，通过第一相位调整来调整反馈时钟信号的相位。粗调控制电路响应于第二相位误差信号，通过第二相位调整来调节反馈时钟信号的相位。第二相位调整大于第一相位调整。第二相位误差信号表示参考时钟信号和反馈时钟信号之间的相位误差的大小。

6. 发明申请

US20110309886A1 DIGITALLY CONTROLLED OSCILLATORS 审中-公开
标题翻译：数字控制振荡器
公开(公告)号：US20110309886A1
公开(公告)日：2011-12-22
申请号：US13224086
申请日：2011-09-01
申请人： Mohsen Moussavi , William W. Bereza
发明人： Mohsen Moussavi , William W. Bereza
IPC分类号： H03K3/03
CPC分类号： H03K3/0322 , H03K2005/00071 , H03L7/0995
摘要： Oscillator circuitry is provided that is based on a ring of inverters. The ring of inverters may be single-ended or differential inverters. Digitally controlled adjustable load capacitors may be provided at inverter outputs to tune the oscillator circuitry. Each digitally controlled adjustable load capacitor may be formed from multiple varactors connected in parallel. Each varactor may have a control input that receives a digital control signal. The digitally controlled adjustable load capacitors in a given oscillator may be adjusted in unison to produce the same capacitance value for each capacitor or may be adjusted individually so that they produce different capacitance values. The inverters may include common-mode-gain reduction features such as series-connected current sources, series-connected resistors, and cross-coupled negative feedback transistors.
摘要翻译：提供了基于逆变器环的振荡器电路。逆变器的环可以是单端或差分逆变器。数字控制的可调负载电容器可以在变频器输出端提供，以调谐振荡器电路。每个数字控制的可调负载电容器可以由并联连接的多个变容二极管形成。每个变容二极管可以具有接收数字控制信号的控制输入。给定振荡器中的数字控制可调负载电容器可以一致调整，以为每个电容器产生相同的电容值，或者可以单独调整，以便它们产生不同的电容值。逆变器可以包括共模增益降低特征，例如串联电流源，串联电阻器和交叉耦合负反馈晶体管。

7. 发明授权

US07825527B2 Return loss techniques in wirebond packages for high-speed data communications 有权
标题翻译：用于高速数据通信的引线封装中的回波损耗技术
公开(公告)号：US07825527B2
公开(公告)日：2010-11-02
申请号：US12139388
申请日：2008-06-13
申请人： William W. Bereza , Hong Shi
发明人： William W. Bereza , Hong Shi
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/49 , H01L23/66 , H01L24/02 , H01L24/48 , H01L2223/6611 , H01L2224/05554 , H01L2224/45015 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/484 , H01L2224/49113 , H01L2224/49171 , H01L2224/4943 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/19051 , H01L2924/19107 , H01L2924/20752 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A wirebond package configured to reduce wirebond return loss is presented. An integrated circuit of interest with rows of bonding pads is bonded to a surface of the wirebond package. The surface of wirebond package has columns of bonding pads, which are configured to transmit or receive signals, power, and ground to and/or from the wirebond package to the integrated circuit. Corresponding die pads on the integrated circuit and bonding pads of the wirebond package are coupled using conductive lines. The conductive lines carrying the active signal has coplanar adjacent ground lines on opposing sides of active signal line and the distance between active signal line and the coplanar adjacent ground lines is tapered.
摘要翻译：提出了一种配置为减少引线键返回损耗的引线键合封装。感兴趣的一排结合焊盘的集成电路被结合到引线键合封装的表面。引线键合封装的表面具有接合焊盘的列，其被配置为向引线封装向集成电路发送或接收信号，电源和接地。集成电路上的对应的芯片焊盘和引线键合封装的焊盘使用导线连接。承载有源信号的导线在有源信号线的相对侧具有共面相邻的接地线，并且有源信号线与共面相邻接地线之间的距离是渐缩的。

8. 发明申请

US20090315627A1 PHASE-LOCKED LOOP CIRCUITRY WITH MULTIPLE VOLTAGE-CONTROLLED OSCILLATORS 有权
标题翻译：带多个电压控制振荡器的锁相环路电路
公开(公告)号：US20090315627A1
公开(公告)日：2009-12-24
申请号：US12142746
申请日：2008-06-19
申请人： William W. Bereza , Rakesh H. Patel
发明人： William W. Bereza , Rakesh H. Patel
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03L7/18
摘要： Configurable phase-locked loop circuitry is provided. The phase-locked loop circuitry may include a buffer having a buffer output and a multiplexer having inputs and an output. The phase-locked loop circuitry may include multiple voltage-controlled oscillators. The phase-locked loop circuitry may be configured to switch a desired one of the voltage-controlled oscillators into use. Each voltage-controlled oscillator may be controlled by control signals applied to a control input for that voltage-controlled oscillator. The control input of each voltage-controlled oscillator may be connected to the buffer output. The output of each voltage-controlled oscillator may be connected to a respective one of the multiplexer inputs. Power-down transistors may be used to disable unused voltage-controlled oscillators to conserve power. The power-down transistors and the multiplexer may be controlled by signals from programmable elements. One or more of the voltage-controlled oscillators may be implemented using a separate integrated circuit connected using through-silicon vias.
摘要翻译：提供可配置的锁相环电路。锁相环电路可以包括具有缓冲器输出的缓冲器和具有输入和输出的多路复用器。锁相环电路可以包括多个压控振荡器。锁相环电路可以被配置为将期望的一个压控振荡器切换成使用。每个压控振荡器可以由施加到该压控振荡器的控制输入的控制信号来控制。每个压控振荡器的控制输入可以连接到缓冲器输出端。每个压控振荡器的输出可以连接到多路复用器输入中的相应一个。掉电晶体管可用于禁用未使用的电压控制振荡器以节省功率。掉电晶体管和多路复用器可以由来自可编程元件的信号控制。可以使用通过硅通孔连接的单独的集成电路来实现一个或多个压控振荡器。

9. 发明授权

US08130044B2 Phase-locked loop circuitry with multiple voltage-controlled oscillators 有权
标题翻译：具有多个压控振荡器的锁相环电路
公开(公告)号：US08130044B2
公开(公告)日：2012-03-06
申请号：US12142746
申请日：2008-06-19
申请人： William W. Bereza , Rakesh H. Patel
发明人： William W. Bereza , Rakesh H. Patel
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03L7/18
摘要： Configurable phase-locked loop circuitry is provided. The phase-locked loop circuitry may include a buffer having a buffer output and a multiplexer having inputs and an output. The phase-locked loop circuitry may include multiple voltage-controlled oscillators. The phase-locked loop circuitry may be configured to switch a desired one of the voltage-controlled oscillators into use. Each voltage-controlled oscillator may be controlled by control signals applied to a control input for that voltage-controlled oscillator. The control input of each voltage-controlled oscillator may be connected to the buffer output. The output of each voltage-controlled oscillator may be connected to a respective one of the multiplexer inputs. Power-down transistors may be used to disable unused voltage-controlled oscillators to conserve power. The power-down transistors and the multiplexer may be controlled by signals from programmable elements. One or more of the voltage-controlled oscillators may be implemented using a separate integrated circuit connected using through-silicon vias.
摘要翻译：提供可配置的锁相环电路。锁相环电路可以包括具有缓冲器输出的缓冲器和具有输入和输出的多路复用器。锁相环电路可以包括多个压控振荡器。锁相环电路可以被配置为将期望的一个压控振荡器切换成使用。每个压控振荡器可以由施加到该压控振荡器的控制输入的控制信号来控制。每个压控振荡器的控制输入可以连接到缓冲器输出端。每个压控振荡器的输出可以连接到多路复用器输入中的相应一个。掉电晶体管可用于禁用未使用的电压控制振荡器以节省功率。掉电晶体管和多路复用器可以由来自可编程元件的信号控制。可以使用通过硅通孔连接的单独的集成电路来实现一个或多个压控振荡器。

10. 发明授权

US08125362B1 Apparatus and associated methods for generating reference signals 有权
标题翻译：用于产生参考信号的装置和相关方法
公开(公告)号：US08125362B1
公开(公告)日：2012-02-28
申请号：US12334219
申请日：2008-12-12
申请人： William W. Bereza
发明人： William W. Bereza
IPC分类号： H03M3/00
CPC分类号： H03M3/322 , H02M3/157 , H03M3/502
摘要： An integrated circuit (IC) includes a reference circuit. The reference circuit includes at least one controlled current source. The reference circuit further includes a sigma-delta modulator coupled to the at least one controlled current source.
摘要翻译：集成电路（IC）包括参考电路。参考电路包括至少一个受控电流源。参考电路还包括耦合到至少一个受控电流源的Σ-Δ调制器。

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