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21. 发明授权

US06710394B2 Method of making floating gate non-volatile memory cell with low erasing voltage having double layer gate dielectric 有权
标题翻译：制造具有双层栅电介质的低擦除电压的浮栅非易失性存储单元的方法
公开(公告)号：US06710394B2
公开(公告)日：2004-03-23
申请号：US10158706
申请日：2002-05-30
申请人： Paolo Cappelletti
发明人： Paolo Cappelletti
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/2822 , H01L29/42332 , H01L29/42336 , H01L29/49 , H01L29/495 , H01L29/513 , H01L29/518
摘要： A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.
摘要翻译：包括至少一个浮栅晶体管并且在半导体衬底上实现的类型的非易失性存储单元包括源极区和漏极区，该沟道区由覆盖有栅极氧化物的薄层。栅极氧化物从衬底隔离浮栅区域。浮栅区域耦合到控制栅极端子。存储单元的浮置栅极区域在半导体衬底和栅极氧化物层之间形成第一势垒，并且在浮置栅极区域和栅极氧化物之间形成第二个不同的势垒。

22. 发明授权

US06399444B1 Method of making floating gate non-volatile memory cell with low erasing voltage 有权
标题翻译：制造具有低擦除电压的浮栅非易失性存储单元的方法
公开(公告)号：US06399444B1
公开(公告)日：2002-06-04
申请号：US09521876
申请日：2000-03-08
申请人： Paolo Cappelletti
发明人： Paolo Cappelletti
IPC分类号： H01L218247
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/2822 , H01L29/42332 , H01L29/42336 , H01L29/49 , H01L29/495 , H01L29/513 , H01L29/518
摘要： A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.
摘要翻译：包括至少一个浮栅晶体管并且在半导体衬底上实现的类型的非易失性存储单元包括源极区和漏极区，该沟道区由覆盖有栅极氧化物的薄层。栅极氧化物从衬底隔离浮栅区域。浮栅区域耦合到控制栅极端子。存储单元的浮置栅极区域在半导体衬底和栅极氧化物层之间形成第一势垒，并且在浮置栅极区域和栅极氧化物之间形成第二个不同的势垒。

23. 发明授权

US06284585B1 Electronic memory device having bit lines with block selector switches 有权
标题翻译：具有位线的电子存储器件具有块选择器开关
公开(公告)号：US06284585B1
公开(公告)日：2001-09-04
申请号：US09387103
申请日：1999-08-31
申请人： Emilio Camerlenghi , Paolo Cappelletti , Luca Pividori
发明人： Emilio Camerlenghi , Paolo Cappelletti , Luca Pividori
IPC分类号： H01L218242
CPC分类号： H01L27/11521 , G11C7/18 , G11C8/12 , G11C16/0491 , H01L27/115
摘要： An electronic memory device organized into sections which are in turn divided into blocks formed of cells and their associated decoding and addressing circuits, the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions which are interconnected by parallel continuous conduction lines referred to as the bit lines. In the present invention, at least one interruption is provided in each bit line near a contact region by inserting a controlled switch which functions as a block selector. Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches of the cascade connected blocks. Also provided is a method of implementing the memory block, as organized into a matrix-like configuration, individually selectable from a plurality of blocks embedded in a memory device, wherein each memory cell is identified by a continuous bit line enabled by at least one block selector, by a broken bit line or ‘segment’ connected to the continuous one through an address device, and by a word line orthogonal to the direction of the bit lines, and formed on a substrate having a first type of conductivity.
摘要翻译：一种电子存储器件，其组织成分为多个单元的单元及其相关联的解码和寻址电路组成的单元，该单元以预定的电路结构连接，每个单元包含在两个相互接触的区域之间，导线称为位线。在本发明中，通过插入用作块选择器的受控开关，在接触区域附近的每个位线中提供至少一个中断。有利地，所提出的解决方案允许通过启用或禁用级联连接的块的开关来单独地隔离每个块。还提供了一种实现存储块的方法，其被组织成矩阵状配置，可从嵌入在存储器设备中的多个块单独选择，其中每个存储器单元由至少一个块使能的连续位线标识选择器，通过地址装置连接到连续的位线的断开的位线或通过与位线的方向正交的字线，并形成在具有第一类型导电性的基板上。

24. 发明授权

US6074916A FLASH-EPROM with embedded EEPROM 有权
标题翻译：带嵌入式EEPROM的FLASH-EPROM
公开(公告)号：US6074916A
公开(公告)日：2000-06-13
申请号：US164761
申请日：1998-10-01
申请人： Paolo Cappelletti
发明人： Paolo Cappelletti
IPC分类号： G11C17/00 , G11C11/00 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517 , G11C11/005 , G11C16/0408 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Cost-efficient integration of a fully-featured EEPROM memory block in a FLASH-EPROM memory device, fabricated according to a low supply voltage and low power consumption FLASH-EPROM process, is made possible by a special structure of the EEPROM cells whereby the capacitive coupling between the floating gate and the control gate of the cell is realized over the field oxide adjacent to the active area of the cell. The process of the invention permits an optimized modulation of the thicknesses of the different tunnel and gate oxides of the FLASH-EPROM and EEPROM cells, as well as of the transistors of the peripheral circuitry of the two memory blocks destined to work with a relatively low supply voltage or with a boosted voltage.
摘要翻译：根据低电源电压和低功耗FLASH-EPROM工艺制造的FLASH-EPROM存储器件中的功能齐全的EEPROM存储器块的经济高效的集成是通过EEPROM单元的特殊结构实现的，由此电容在与单元的有源区相邻的场氧化物上实现了浮栅和单元的控制栅之间的耦合。本发明的方法允许对FLASH-EPROM和EEPROM单元的不同隧道和栅极氧化物的厚度以及两个存储器块的外围电路的晶体管进行优化调制，这两个存储器块的目的地工作在相对较低的电源电压或升压电压。

25. 发明授权

US6054731A Floating gate non-volatile memory cell with low erasing voltage and manufacturing method 失效
标题翻译：具有低擦除电压和制造方法的浮栅非易失性存储单元
公开(公告)号：US6054731A
公开(公告)日：2000-04-25
申请号：US940856
申请日：1997-09-29
申请人： Paolo Cappelletti
发明人： Paolo Cappelletti
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/2822 , H01L29/42332 , H01L29/42336 , H01L29/49 , H01L29/495 , H01L29/513 , H01L29/518
摘要： A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.
摘要翻译：包括至少一个浮栅晶体管并且在半导体衬底上实现的类型的非易失性存储单元包括源极区和漏极区，该沟道区由覆盖有栅极氧化物的薄层。栅极氧化物从衬底隔离浮栅区域。浮栅区域耦合到控制栅极端子。存储单元的浮置栅极区域在半导体衬底和栅极氧化物层之间形成第一势垒，并且在浮置栅极区域和栅极氧化物之间形成第二个不同的势垒。

26. 发明授权

US5969977A Electronic memory device having bit lines with block selector switches 失效
标题翻译：具有位线的电子存储器件具有块选择器开关
公开(公告)号：US5969977A
公开(公告)日：1999-10-19
申请号：US998854
申请日：1997-12-29
申请人： Emilio Camerlenghi , Paolo Cappelletti , Luca Pividori
发明人： Emilio Camerlenghi , Paolo Cappelletti , Luca Pividori
IPC分类号： G11C7/18 , G11C8/12 , G11C16/04 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/00
CPC分类号： H01L27/11521 , G11C16/0491 , G11C7/18 , G11C8/12 , H01L27/115
摘要： An electronic memory device organized into sections which are in turn divided into blocks formed of cells and their associated decoding and addressing circuits, the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions which are interconnected by parallel continuous conduction lines referred to as the bit lines. In the present invention, at least one interruption is provided in each bit line near a contact region by inserting a controlled switch which functions as a block selector. Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches of the cascade connected blocks. Also provided is a method of implementing the memory block, as organized into a matrix-like configuration, individually selectable from a plurality of blocks embedded in a memory device, wherein each memory cell is identified by a continuous bit line enabled by at least one block selector, by a broken bit line or `segment` connected to the continuous one through an address device, and by a word line orthogonal to the direction of the bit lines, and formed on a substrate having a first type of conductivity.
摘要翻译：一种电子存储器件，其组织成分为多个单元的单元及其相关联的解码和寻址电路组成的单元，该单元以预定的电路结构连接，每个单元包含在两个相互接触的区域之间，导线称为位线。在本发明中，通过插入用作块选择器的受控开关，在接触区域附近的每个位线中提供至少一个中断。有利地，所提出的解决方案允许通过启用或禁用级联连接的块的开关来单独地隔离每个块。还提供了一种实现存储块的方法，其被组织成矩阵状配置，可从嵌入在存储器设备中的多个块单独选择，其中每个存储器单元由至少一个块使能的连续位线标识选择器，通过地址装置连接到连续的位线的断开的位线或“段”，以及与位线的方向正交的字线，并形成在具有第一类型导电性的基板上。

27. 发明授权

US5328863A Process for manufacturing a ROM cell with low drain capacitance 失效
标题翻译：具有低漏电容的ROM单元的制造工艺
公开(公告)号：US5328863A
公开(公告)日：1994-07-12
申请号：US668873
申请日：1991-03-13
申请人： Paolo Cappelletti , Silvia Lucherini , Bruno Vajana
发明人： Paolo Cappelletti , Silvia Lucherini , Bruno Vajana
IPC分类号： H01L21/8247 , H01L21/8246 , H01L27/112 , H01L27/115 , H01L21/70 , H01L27/00
CPC分类号： H01L27/11253 , H01L27/112 , H01L27/1126 , H01L27/11266
摘要： A process which provides for the creation of regions of source and drain having different doping, wherein the doping, and thus the capacitance, of the drain regions is lower than that of the source regions.
摘要翻译：提供了产生具有不同掺杂的源极和漏极的区域的工艺，其中漏极区域的掺杂以及因此的电容低于源极区域的掺杂。

28. 发明申请

US20120080738A1 SHALLOW TRENCH ISOLATION FOR A MEMORY 有权
标题翻译：用于记忆的浅层分离
公开(公告)号：US20120080738A1
公开(公告)日：2012-04-05
申请号：US13315337
申请日：2011-12-09
申请人： Alessandro Grossi , Marcello Mariani , Paolo Cappelletti
发明人： Alessandro Grossi , Marcello Mariani , Paolo Cappelletti
IPC分类号： H01L29/788
CPC分类号： H01L29/788 , H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.
摘要翻译：在一些实施例中，具有在其侧面上的间隔物的栅极结构可以用作掩模以在诸如闪存的微电子存储器中形成自对准沟槽。在一些实施例中，门结构的第一部分可以与侧壁间隔件一起用于形成掩模。然后，在形成浅沟槽隔离物之后，可以添加栅极结构的第二部分以形成蘑菇形门结构。

29. 发明申请

US20060189136A1 Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit 失效
标题翻译：为了优化集成在半导体衬底和相应电路上的电子电路中的有源电结构的定义，非有源电结构的制造方法
公开(公告)号：US20060189136A1
公开(公告)日：2006-08-24
申请号：US11334988
申请日：2006-01-19
申请人： Paolo Cappelletti , Alfonso Maurelli , Paola Zabberoni
发明人： Paolo Cappelletti , Alfonso Maurelli , Paola Zabberoni
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531 , H01L27/11546
摘要： A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.
摘要翻译：提供了一种用于制造集成在半导体衬底上的电子电路的非活性结构的方法，其中电子电路包括第一和第二电活性结构。该方法包括将电非电活性结构插入电子电路中以在半导体衬底上方形成均匀的表面。所述插入包括在电非活性结构之中识别与第一和第二电活性结构相邻的第一组电非活性结构，并且在电非活性结构中识别第二组电非活性结构，活性结构不与第一和第二电活性结构相邻。该方法还包括通过不同的光刻步骤在半导体衬底上限定第一和第二组电非活性结构。

30. 发明授权

US07012832B1 Magnetic memory cell with plural read transistors 有权
标题翻译：具有多个读取晶体管的磁存储单元
公开(公告)号：US07012832B1
公开(公告)日：2006-03-14
申请号：US10698747
申请日：2003-10-31
申请人： Kyusik Sin , Matthew R. Gibbons , William D. Jensen , Hugh Craig Hiner , Xizeng Stone Shi , Roberto Bez , Giulio Casagrande , Paolo Cappelletti
发明人： Kyusik Sin , Matthew R. Gibbons , William D. Jensen , Hugh Craig Hiner , Xizeng Stone Shi , Roberto Bez , Giulio Casagrande , Paolo Cappelletti
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A magnetic random access memory (MRAM) device has increased ΔR/R for sensing a state of a pin-dependent tunneling (SDT) device. The MRAM device includes plural transistors connected to a read line for sensing the state of the SDT device. Plural transistors lower an underlying resistance during reading, increasing ΔR/R. The plural transistors can share a source region.
摘要翻译：磁性随机存取存储器（MRAM）器件增加了用于感测引脚依赖隧道（SDT）器件的状态的DeltaR / R。 MRAM器件包括连接到读取线的多个晶体管，用于感测SDT器件的状态。多个晶体管在读取期间降低潜在电阻，增加DeltaR / R。多个晶体管可以共享源极区域。

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