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1. 发明申请

US20060189136A1 Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit 失效
标题翻译：为了优化集成在半导体衬底和相应电路上的电子电路中的有源电结构的定义，非有源电结构的制造方法
公开(公告)号：US20060189136A1
公开(公告)日：2006-08-24
申请号：US11334988
申请日：2006-01-19
申请人： Paolo Cappelletti , Alfonso Maurelli , Paola Zabberoni
发明人： Paolo Cappelletti , Alfonso Maurelli , Paola Zabberoni
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531 , H01L27/11546
摘要： A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.
摘要翻译：提供了一种用于制造集成在半导体衬底上的电子电路的非活性结构的方法，其中电子电路包括第一和第二电活性结构。该方法包括将电非电活性结构插入电子电路中以在半导体衬底上方形成均匀的表面。所述插入包括在电非活性结构之中识别与第一和第二电活性结构相邻的第一组电非活性结构，并且在电非活性结构中识别第二组电非活性结构，活性结构不与第一和第二电活性结构相邻。该方法还包括通过不同的光刻步骤在半导体衬底上限定第一和第二组电非活性结构。

2. 发明授权

US06876033B2 Electrically erasable and programmable non-volatile memory cell 有权
标题翻译：电可擦除和可编程的非易失性存储单元
公开(公告)号：US06876033B2
公开(公告)日：2005-04-05
申请号：US10606164
申请日：2003-06-25
申请人： Paolo Cappelletti , Paolo Ghezzi , Alfonso Maurelli , Loris Vendrame , Paola Zabberoni
发明人： Paolo Cappelletti , Paolo Ghezzi , Alfonso Maurelli , Loris Vendrame , Paola Zabberoni
IPC分类号： H01L21/8247 , H01L27/105 , H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11534 , H01L29/7885
摘要： An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.
摘要翻译：提供电可擦除和可编程的存储单元。存储单元包括浮置栅极MOS晶体管和用于将电荷注入浮置栅极的双极晶体管。浮置栅极晶体管具有形成在第一阱中的源极区和漏极区，沟道限定在漏极和源极区之间，控制栅极区以及在沟道和控制栅极区上延伸的浮动栅极。双极晶体管具有形成在第一阱中的发射极区域，由第一阱构成的基极区域和由沟道组成的集电极区域。存储单元包括与第一阱绝缘的第二阱，并且控制栅区形成在第二阱中。本发明的另外的实施例提供了包括至少一个这样的存储单元的存储器，包括这种存储器的电子设备，以及集成存储器单元和擦除存储器单元的方法。

3. 发明申请

US20050032278A1 Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit 失效
标题翻译：为了优化集成在半导体衬底和相应电路上的电子电路中的有源电结构的定义，非有源电结构的制造方法
公开(公告)号：US20050032278A1
公开(公告)日：2005-02-10
申请号：US10911220
申请日：2004-08-03
申请人： Paolo Cappelletti , Alfonso Maurelli , Paola Zabberoni
发明人： Paolo Cappelletti , Alfonso Maurelli , Paola Zabberoni
IPC分类号： H01L21/82 , H01L21/8247 , H01L27/02 , H01L27/105 , H01L27/115 , H01L29/00
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531 , H01L27/11546
摘要： A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.
摘要翻译：提供了一种用于制造集成在半导体衬底上的电子电路的非活性结构的方法，其中电子电路包括第一和第二电活性结构。该方法包括将电非电活性结构插入电子电路中以在半导体衬底上方形成均匀的表面。所述插入包括在电非活性结构之中识别与第一和第二电活性结构相邻的第一组电非活性结构，并且在电非活性结构之中识别第二组电非活性结构，活性结构不与第一和第二电活性结构相邻。该方法还包括通过不同的光刻步骤在半导体衬底上限定第一和第二组电非活性结构。

4. 发明申请

US20070287290A1 MANUFACTURING METHOD FOR NON-ACTIVE ELECTRICALLY STRUCTURES OF AN INTEGRATED ELECTRONIC CIRCUIT FORMED ON A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING ELECTRONIC CIRCUIT 审中-公开
标题翻译：在半导体基板和相应电子电路上形成的集成电子电路的非主动电气结构的制造方法
公开(公告)号：US20070287290A1
公开(公告)日：2007-12-13
申请号：US11754494
申请日：2007-05-29
申请人： Alfonso Maurelli , Daniela Peschiaroli , Fausto Piazza , Carlo Vigiani , Paola Zabberoni
发明人： Alfonso Maurelli , Daniela Peschiaroli , Fausto Piazza , Carlo Vigiani , Paola Zabberoni
IPC分类号： H01L21/302 , H01L21/31
CPC分类号： H01L27/11526 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/11519 , H01L27/11534
摘要： Electrically non-active structures are formed for an electronic circuit to make uniform a surface above a semiconductor substrate. The electronic circuit includes first electrically active structures comprising conductive elements of a first height projecting from the semiconductor substrate, and second electrically active structures comprising conductive elements of a second height projecting from the semiconductor substrate. The first height is different from the second height. The electrically non-active structures are formed by identifying, among the electrically non-active structures, a first group of electrically non-active structures formed within areas that substantially extend for a radius around each electrical component belonging to the second electrically active structures. The method further includes identifying, among the electrically non-active structures, a second group of electrically non-active structures not belonging to the first group of electrically non-active structures. The electrically non-active structures belonging to the first group of electrically non-active structures are formed with elements projecting from the semiconductor substrate having a height equal to the second height. The electrically non-active structures belonging to the second group of electrically non-active structures are formed with elements projecting from the semiconductor substrate having a height equal to the first height.
摘要翻译：形成用于电子电路的电非结构以在半导体衬底上方形成均匀的表面。电子电路包括第一电活动结构，其包括从半导体衬底突出的第一高度的导电元件，以及包括从半导体衬底突出的第二高度的导电元件的第二电活动结构。第一高度与第二高度不同。电非活性结构通过在电非活性结构之中识别形成在基本上延伸用于围绕属于第二电活动结构的每个电气部件的半径的区域内的第一组电非活性结构而形成。该方法还包括在电非活性结构中识别不属于第一组电非活性结构的第二组电非活性结构。属于第一组电非活性结构的电非活性结构由具有等于第二高度的高度从半导体衬底突出的元件形成。属于第二组电非活性结构的电非活性结构由具有等于第一高度的高度的半导体衬底突出的元件形成。

5. 发明授权

US07001800B2 Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit 失效
公开(公告)号：US07001800B2
公开(公告)日：2006-02-21
申请号：US10911220
申请日：2004-08-03
申请人： Paolo Giuseppe Cappelletti , Alfonso Maurelli , Paola Zabberoni
发明人： Paolo Giuseppe Cappelletti , Alfonso Maurelli , Paola Zabberoni
IPC分类号： H01L21/82
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531 , H01L27/11546
摘要： A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.

6. 发明授权

US07320904B2 Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit 失效
标题翻译：为了优化集成在半导体衬底和相应电路上的电子电路中的有源电结构的定义，非有源电结构的制造方法
公开(公告)号：US07320904B2
公开(公告)日：2008-01-22
申请号：US11334988
申请日：2006-01-19
申请人： Paolo Giuseppe Cappelletti , Alfonso Maurelli , Paola Zabberoni
发明人： Paolo Giuseppe Cappelletti , Alfonso Maurelli , Paola Zabberoni
IPC分类号： H01L21/82 , H01L29/76
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531 , H01L27/11546
摘要： A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.
摘要翻译：提供了一种用于制造集成在半导体衬底上的电子电路的非活性结构的方法，其中电子电路包括第一和第二电活性结构。该方法包括将电非电活性结构插入电子电路中以在半导体衬底上方形成均匀的表面。所述插入包括在所述电非活性结构之中识别与所述第一和第二电活性结构相邻的第一组电非活性结构，以及在所述电非活性结构中识别第二组电非活性结构，活性结构不与第一和第二电活性结构相邻。该方法还包括通过不同的光刻步骤在半导体衬底上限定第一和第二组电非活性结构。

7. 发明申请

US20070026610A1 SEALING METHOD FOR ELECTRONIC DEVICES FORMED ON A COMMON SEMICONDUCTOR SUBSTRATE AND CORRESPONDING CIRCUIT STRUCTURE 审中-公开
标题翻译：在通用半导体基板上形成的电子器件的密封方法和相应的电路结构
公开(公告)号：US20070026610A1
公开(公告)日：2007-02-01
申请号：US11457948
申请日：2006-07-17
申请人： Emilio Camerlenghi , Alfonso Maurelli , Daniela Peschiaroli , Paola Zabberoni
发明人： Emilio Camerlenghi , Alfonso Maurelli , Daniela Peschiaroli , Paola Zabberoni
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823468 , H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： An integrated circuit includes a semiconductor substrate including first and second portions, with first electronic devices adjacent the first portion. Each first electronic device includes a first region comprising at least one first conductive layer projecting from the semiconductor substrate. First protective spacers are adjacent sidewalls of the first regions of the first electronic devices. The first protective spacers are defined by first and second sealing layers adjacent one another. Second electronic devices are adjacent the second portion of the semiconductor substrate. Each second electronic device includes a second region comprising a second conductive layer projecting from the semiconductor substrate. Second protective spacers are adjacent sidewalls of the second regions of the second electronic devices. The second protective spacers are defined by other portions of the second sealing layer. The second sealing layer has a thickness less than a thickness of the first sealing layer.
摘要翻译：集成电路包括包括第一和第二部分的半导体衬底，第一电子器件与第一部分相邻。每个第一电子器件包括包含从半导体衬底突出的至少一个第一导电层的第一区域。第一保护间隔物是第一电子器件的第一区域的相邻侧壁。第一保护隔离物由彼此相邻的第一和第二密封层限定。第二电子器件与半导体衬底的第二部分相邻。每个第二电子器件包括第二区域，其包括从半导体衬底突出的第二导电层。第二保护间隔物是第二电子器件的第二区域的相邻侧壁。第二保护隔离物由第二密封层的其它部分限定。第二密封层的厚度小于第一密封层的厚度。

8. 发明授权

US07078294B2 Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure 有权
标题翻译：形成在公共半导体衬底上的电子器件的密封方法和相应的电路结构
公开(公告)号：US07078294B2
公开(公告)日：2006-07-18
申请号：US10971774
申请日：2004-10-22
申请人： Emilio Camerlenghi , Alfonso Maurelli , Daniela Peschiaroli , Paola Zabberoni
发明人： Emilio Camerlenghi , Alfonso Maurelli , Daniela Peschiaroli , Paola Zabberoni
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L23/3192 , H01L27/105 , H01L27/11536 , H01L2924/0002 , H01L2924/00
摘要： A method for sealing electronic devices formed on a semiconductor substrate includes forming at least one first conductive layer on a first portion of the semiconductor substrate for defining electronic devices, and forming a second conductive layer on a second portion of semiconductor substrate for also defining electronic devices. First regions are formed in the at least one first conductive layer for defining electronic devices, and a first sealing layer is formed on the whole semiconductor substrate to seal the first regions. Second regions are formed in the second conductive layer for defining electronic devices, and a second sealing layer is formed on the whole semiconductor substrate to seal the second regions.
摘要翻译：用于密封形成在半导体衬底上的电子器件的方法包括在半导体衬底的用于限定电子器件的第一部分上形成至少一个第一导电层，以及在半导体衬底的第二部分上形成第二导电层，用于还限定电子器件。第一区域形成在用于限定电子器件的至少一个第一导电层中，并且在整个半导体衬底上形成第一密封层以密封第一区域。第二区域形成在用于限定电子器件的第二导电层中，并且在整个半导体衬底上形成第二密封层以密封第二区域。

9. 发明申请

US20050112905A1 Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure 有权
标题翻译：形成在公共半导体衬底上的电子器件的密封方法和相应的电路结构
公开(公告)号：US20050112905A1
公开(公告)日：2005-05-26
申请号：US10971774
申请日：2004-10-22
申请人： Emilio Camerlenghi , Alfonso Maurelli , Daniela Peschiaroli , Paola Zabberoni
发明人： Emilio Camerlenghi , Alfonso Maurelli , Daniela Peschiaroli , Paola Zabberoni
IPC分类号： H01L21/8234 , H01L21/8247 , H01L23/31 , H01L27/105 , H01L21/44 , B32B7/12 , B32B15/04 , H01L21/31 , H01L21/469 , H01L21/48 , H01L21/50
CPC分类号： H01L27/11526 , H01L21/823468 , H01L23/3192 , H01L27/105 , H01L27/11536 , H01L2924/0002 , H01L2924/00
摘要： A method for sealing electronic devices formed on a semiconductor substrate includes forming at least one first conductive layer on a first portion of the semiconductor substrate for defining electronic devices, and forming a second conductive layer on a second portion of semiconductor substrate for also defining electronic devices. First regions are formed in the at least one first conductive layer for defining electronic devices, and a first sealing layer is formed on the whole semiconductor substrate to seal the first regions. Second regions are formed in the second conductive layer for defining electronic devices, and a second sealing layer is formed on the whole semiconductor substrate to seal the second regions.
摘要翻译：用于密封形成在半导体衬底上的电子器件的方法包括在半导体衬底的用于限定电子器件的第一部分上形成至少一个第一导电层，以及在半导体衬底的第二部分上形成第二导电层，用于还限定电子器件。第一区域形成在用于限定电子器件的至少一个第一导电层中，并且在整个半导体衬底上形成第一密封层以密封第一区域。第二区域形成在用于限定电子器件的第二导电层中，并且在整个半导体衬底上形成第二密封层以密封第二区域。

10. 发明授权

US06350637B1 Method of fabrication of a no-field MOS transistor 失效
标题翻译：无场MOS晶体管的制造方法
公开(公告)号：US06350637B1
公开(公告)日：2002-02-26
申请号：US09543400
申请日：2000-04-05
申请人： Alfonso Maurelli , Paola Zabberoni
发明人： Alfonso Maurelli , Paola Zabberoni
IPC分类号： H01L21336
CPC分类号： H01L29/0847 , H01L29/4238 , H01L29/66477
摘要： Method of fabrication of a no-field transistor with no extra process costs, providing for defining an active area for the transistor surrounded by a thick field oxide layer, insulatively placing a polysilicon gate electrode across the active area to define source/drain regions of the no-field transistor, providing an implant protection mask over a boundary between at least one of the source/drain regions and the field oxide layer, selectively implanting in said source/drain regions a relatively heavy dose of dopants to form relatively heavily doped source/drain regions and to simultaneously dope the polysilicon gate electrode, the polysilicon gate electrode formed with lateral wings extending towards the at least one source/drain region, and the implant protection mask extending over the lateral wings but not over the polysilicon gate.
摘要翻译：制造没有额外工艺成本的无场晶体管的方法，提供限定由厚场氧化物层围绕的晶体管的有源区域，绝缘地将多晶硅栅极电极放置在有源区域上以限定源极/漏极区域无源晶体管，在源极/漏极区域和场氧化物层中的至少一个之间的边界上提供注入保护掩模，选择性地在所述源/漏区域中注入相对较大剂量的掺杂剂以形成相对高掺杂的源极/ 漏极区域并且同时掺杂多晶硅栅电极，形成有朝向至少一个源极/漏极区域延伸的侧翼的多晶硅栅极电极以及在侧翼上延伸但不在多晶硅栅极上的植入物保护掩模。

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