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21. 发明授权

US06438014B2 High speed access compatible memory module 有权
标题翻译：高速存取兼容内存模块
公开(公告)号：US06438014B2
公开(公告)日：2002-08-20
申请号：US09803148
申请日：2001-03-12
申请人： Seiji Funaba , Yoshinobu Nakagome , Masashi Horiguchi , Yoji Nishio
发明人： Seiji Funaba , Yoshinobu Nakagome , Masashi Horiguchi , Yoji Nishio
IPC分类号： G11C506
CPC分类号： G11C5/06 , G11C5/04 , G11C5/063 , H01L23/5387 , H01L25/065 , H01L25/0655 , H01L25/0657 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06579 , H01L2924/01055 , H01L2924/15312 , H01L2924/1532 , H01L2924/3011
摘要： A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each of the individual memory modules are connected in serial form, and each of the individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.
摘要翻译：模块基板具有与多个存储器芯片中的各个芯片数据端子相关联地分别设置的多个模块数据端子对，以及分别连接在多个模块数据端子对之间的多个模块数据布线。多个模块数据布线连接到它们对应的芯片数据终端，并被配置为可用作存储器访问数据总线。在并行布置多个存储器模块的存储器系统中，各个存储器模块的模块数据布线以串行形式连接，并且每个单独的模块数据配线不构成相对于数据的分支布线总线在内存系统的主板上。在存储器模块中，确保与存储器访问数据总线的宽度相对应的位数的并行访问。

22. 发明授权

US06356119B2 Semiconductor integrated circuit device having power reduction mechanism 失效
公开(公告)号：US06356119B2
公开(公告)日：2002-03-12
申请号：US09766979
申请日：2001-01-23
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： H03K19094
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

23. 发明授权

US06275440B1 Semiconductor integrated circuit device and method of activating the same 有权
公开(公告)号：US06275440B1
公开(公告)日：2001-08-14
申请号：US09729273
申请日：2000-12-05
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

24. 发明授权

US06270935B1 Index photograph, exposed film package, and film package producing system 有权
公开(公告)号：US06270935B1
公开(公告)日：2001-08-07
申请号：US09759135
申请日：2001-01-16
申请人： Setsuji Tatsumi , Kazuhiro Tagawa , Toru Kurokawa , Katsumi Otake , Masashi Horiguchi , Toru Tsuji
发明人： Setsuji Tatsumi , Kazuhiro Tagawa , Toru Kurokawa , Katsumi Otake , Masashi Horiguchi , Toru Tsuji
IPC分类号： G03C1100
摘要： An exposed film package for preserving one strip of exposed photographic film includes a film sheath, which has plural pockets. Plural film pieces are formed by cutting the one strip of the exposed film, and contained respectively in the pockets in the film sheath. An index photograph is constituted of photographic paper, on which positive images of frames from the one strip of the exposed film are printed. The photographic paper has a size substantially equal to the film pieces. The positive images are formed in reducing a size of the frames, and grouped in association with the film pieces. Groups of the positive images are arranged in consideration of an order of exposure of the frames. The index photograph is contained in one of the pockets in association with the film pieces constituting the one strip.

25. 发明授权

US06270932B1 Index photograph, exposed film package, and film package producing system 有权
公开(公告)号：US06270932B1
公开(公告)日：2001-08-07
申请号：US09759326
申请日：2001-01-16
申请人： Setsuji Tatsumi , Kazuhiro Tagawa , Toru Kurokawa , Katsumi Otake , Masashi Horiguchi , Toru Tsuji
发明人： Setsuji Tatsumi , Kazuhiro Tagawa , Toru Kurokawa , Katsumi Otake , Masashi Horiguchi , Toru Tsuji
IPC分类号： G03C1100
摘要： An exposed film package for preserving one strip of exposed photographic film includes a film sheath, which has plural pockets. Plural film pieces are formed by cutting the one strip of the exposed film, and contained respectively in the pockets in the film sheath. An index photograph is constituted of photographic paper, on which positive images of frames from the one strip of the exposed film are printed. The photographic paper has a size substantially equal to the film pieces. The positive images are formed in reducing a size of the frames, and grouped in association with the film pieces. Groups of the positive images are arranged in consideration of an order of exposure of the frames. The index photograph is contained in one of the pockets in association with the film pieces constituting the one strip.

26. 发明授权

US6107869A Semiconductor integrated circuit 失效
公开(公告)号：US6107869A
公开(公告)日：2000-08-22
申请号：US96456
申请日：1998-06-11
申请人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
发明人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
IPC分类号： G11C11/41 , G11C5/14 , G11C8/08 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/3205 , H01L21/822 , H01L21/8242 , H01L23/52 , H01L27/04 , H01L27/108 , G05F3/02
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002
摘要： It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.

27. 发明授权

US6107836A Semiconductor integrated circuit device having power reduction mechanism 失效
公开(公告)号：US6107836A
公开(公告)日：2000-08-22
申请号：US199199
申请日：1998-11-25
申请人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
发明人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
IPC分类号： H01L27/00 , H01L27/02 , H03K3/356 , H03K19/00 , H03K19/094 , H03K19/20
CPC分类号： H03K3/356113 , H03K19/0016 , H01L27/0218
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

28. 发明授权

US5983358A Semiconductor memory having redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器
公开(公告)号：US5983358A
公开(公告)日：1999-11-09
申请号：US938962
申请日：1997-09-26
申请人： Masashi Horiguchi , Shinichi Miyatake , Tathunori Mushya , Yasuhiro Kasama , Yoichi Matsuno , Yasushi Kawase , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Shinichi Miyatake , Tathunori Mushya , Yasuhiro Kasama , Yoichi Matsuno , Yasushi Kawase , Yoshinobu Nakagome
IPC分类号： G11C11/401 , G06F11/00 , G11C29/00 , G11C29/04
CPC分类号： G11C29/842
摘要： A semiconductor memory having a redundancy circuit includes a judgment device for receiving outputs of first ROMs for storing a defective address therein and judging whether or not a defective memory cell and a spare memory cell to replace the defective memory cell belong to the same memory cell, and also includes a timing adjustment circuit for changing the timing of control signals applied to memory mat control circuits according to an output of the judgment device. When the defective and spare memory cells belong to the same memory mat, the timing of the control signals is made fast.
摘要翻译：具有冗余电路的半导体存储器包括判断装置，用于接收用于存储缺陷地址的第一ROM的输出，并判断有缺陷的存储单元和备用存储单元是否属于同一个存储单元，并且还包括定时调整电路，用于根据判断装置的输出来改变施加到存储器垫控制电路的控制信号的定时。当有缺陷的和备用的存储器单元属于相同的存储器存储器时，控制信号的定时变得快。

29. 发明授权

US5815448A Semiconductor memory having redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器
公开(公告)号：US5815448A
公开(公告)日：1998-09-29
申请号：US825605
申请日：1997-03-31
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A redundancy technique is introduced for a semiconductor memory and, more particularly, a redundancy technique for a dynamic random access memory (DRAM) having a storage capacity of 16 mega bits or more. In such a DRAM, the memory array is divided into memory mats. According to the present redundancy technique, for a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, memory cells disposed at desired ones of the two-level crossings, and spare bit lines, there is provided a redundancy circuit having a memory for storing therein a defective address existing in the memory array and comparing an address to be accessed with the stored defective address, and selection circuitry including logical OR gates for replacing a defective bit line by a spare bit line in accordance with the result of the comparison. Each of the address comparing circuits has stored therein the column address of a defective bit line and a part of the row address indicating the memory mat corresponding to the defective bit line.
摘要翻译：引入冗余技术用于半导体存储器，更具体地，涉及具有16兆位或更多存储容量的动态随机存取存储器（DRAM）的冗余技术。在这样的DRAM中，存储器阵列被分成存储器垫。根据本技术的冗余技术，对于包含具有多个字线的存储器阵列的半导体存储器，配置成在字线和位线之间形成2级交叉的多位位线，位于提供了两级交叉中的期望的和备用位线，提供了一种冗余电路，其具有用于在其中存储存在于存储器阵列中的缺陷地址并将要访问的地址与所存储的缺陷地址进行比较的存储器，以及选择电路包括用于根据比较结果用备用位线替换有缺陷位线的逻辑“或”门。每个地址比较电路在其中存储有缺陷位线的列地址和指示与有缺陷位线对应的存储器堆的行地址的一部分。

30. 发明授权

US5706474A Synchronous memory system with asynchronous internal memory operation 失效
标题翻译：具有异步内部存储器操作的同步存储器系统
公开(公告)号：US5706474A
公开(公告)日：1998-01-06
申请号：US455155
申请日：1995-05-31
申请人： Kan Takeuchi , Masashi Horiguchi , Masakazu Aoki , Takeshi Sakata , Hitoshi Tanaka , Katsumi Matsuno
发明人： Kan Takeuchi , Masashi Horiguchi , Masakazu Aoki , Takeshi Sakata , Hitoshi Tanaka , Katsumi Matsuno
IPC分类号： G11C11/407 , G06F12/00 , G06F13/16 , G11C7/10 , G11C11/401 , G11C11/409
CPC分类号： G11C7/1072 , G06F13/1689 , Y02B60/1228
摘要： A memory system is provided which is capable of eliminating deterioration in a processing rate due to possible signal delays between an input/output circuit and memory blocks. Complication of design is also reduced, especially when the scale and chip area of the memory system increase. A memory chip includes a plurality of memory array blocks each including an address buffer and an address counter, and operates on the basis of a local clock cycle. A control circuit is synchronous with a clock of an external device, and synchronous data-transfer circuitry includes a buffer which modulates the transfer rate of serial data which arrives from a memory array block at a local clock cycle so as to be synchronous with the clock of the control circuit. External clock signal lines are not distributed to the memory array blocks.
摘要翻译：提供了一种能够消除由于输入/输出电路和存储块之间的信号延迟引起的处理速率恶化的存储器系统。设计的复杂性也降低了，特别是当存储器系统的规模和芯片面积增加时。存储器芯片包括多个存储器阵列块，每个存储器阵列块包括地址缓冲器和地址计数器，并且基于本地时钟周期进行操作。控制电路与外部设备的时钟同步，同步数据传输电路包括一个缓冲器，该缓冲器调制在本地时钟周期从存储器阵列块到达的串行数据的传输速率，以便与时钟同步的控制电路。外部时钟信号线不分配给存储器阵列块。

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