专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5983358A Semiconductor memory having redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器
公开(公告)号：US5983358A
公开(公告)日：1999-11-09
申请号：US938962
申请日：1997-09-26
申请人： Masashi Horiguchi , Shinichi Miyatake , Tathunori Mushya , Yasuhiro Kasama , Yoichi Matsuno , Yasushi Kawase , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Shinichi Miyatake , Tathunori Mushya , Yasuhiro Kasama , Yoichi Matsuno , Yasushi Kawase , Yoshinobu Nakagome
IPC分类号： G11C11/401 , G06F11/00 , G11C29/00 , G11C29/04
CPC分类号： G11C29/842
摘要： A semiconductor memory having a redundancy circuit includes a judgment device for receiving outputs of first ROMs for storing a defective address therein and judging whether or not a defective memory cell and a spare memory cell to replace the defective memory cell belong to the same memory cell, and also includes a timing adjustment circuit for changing the timing of control signals applied to memory mat control circuits according to an output of the judgment device. When the defective and spare memory cells belong to the same memory mat, the timing of the control signals is made fast.
摘要翻译：具有冗余电路的半导体存储器包括判断装置，用于接收用于存储缺陷地址的第一ROM的输出，并判断有缺陷的存储单元和备用存储单元是否属于同一个存储单元，并且还包括定时调整电路，用于根据判断装置的输出来改变施加到存储器垫控制电路的控制信号的定时。当有缺陷的和备用的存储器单元属于相同的存储器存储器时，控制信号的定时变得快。

2. 发明授权

US07199648B2 Semiconductor integrated circuit including first and second switching transistors having operation states corresponding to operation states of first and second logic circuits 有权
标题翻译：包括具有对应于第一和第二逻辑电路的操作状态的操作状态的第一和第二开关晶体管的半导体集成电路
公开(公告)号：US07199648B2
公开(公告)日：2007-04-03
申请号：US10859141
申请日：2004-06-03
申请人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
发明人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
IPC分类号： G05F1/10
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit is provided having first and second logic circuits coupled to first and second sub-power supply lines, respectively. First and second switching transistors are also provided to connect the first and second sub-power supply lines to a main power supply line. The first and second switching transistors are kept off in an operation stop state of the first and second logic circuits, and are kept on in operable state of the first and second logic circuits.
摘要翻译：提供半导体集成电路，其具有分别耦合到第一和第二子电源线的第一和第二逻辑电路。还提供第一和第二开关晶体管以将第一和第二子电源线连接到主电源线。第一和第二开关晶体管被保持在第一和第二逻辑电路的操作停止状态，并且保持在第一和第二逻辑电路的可操作状态。

3. 发明授权

US6107869A Semiconductor integrated circuit 失效
公开(公告)号：US6107869A
公开(公告)日：2000-08-22
申请号：US96456
申请日：1998-06-11
申请人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
发明人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
IPC分类号： G11C11/41 , G11C5/14 , G11C8/08 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/3205 , H01L21/822 , H01L21/8242 , H01L23/52 , H01L27/04 , H01L27/108 , G05F3/02
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002
摘要： It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.

4. 发明授权

US06747509B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06747509B2
公开(公告)日：2004-06-08
申请号：US10045105
申请日：2002-01-15
申请人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
发明人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
IPC分类号： G05F110
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002 , H01L2924/00
摘要： It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.
摘要翻译：可以减小副电源线上的电压降，以降低亚阈值电流，从而防止逻辑电路的工作速度降低。主电源线沿着包括其亚阈值电流必须减小的MOS逻辑电路的矩形区域的一侧布置，并且在垂直于主电源线的方向上的区域上布置多个子电源线。用于将副电源线选择性地电连接到主电源线的多个开关MOS晶体管相对于主电源线分散布置。通过相对于主电源线分散配置开关MOS晶体管，与在一个地方设置开关MOS晶体管的情况相比，可以降低副电源线的等效电阻。

5. 发明授权

US06339358B1 Semiconductor integrated circuit 有权
公开(公告)号：US06339358B1
公开(公告)日：2002-01-15
申请号：US09513929
申请日：2000-02-28
申请人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
发明人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
IPC分类号： G05F110
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002 , H01L2924/00
摘要： It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.

6. 发明申请

US20050237839A1 Semiconductor memory device 有权
公开(公告)号：US20050237839A1
公开(公告)日：2005-10-27
申请号：US11168291
申请日：2005-06-29
申请人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
发明人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
IPC分类号： G11C11/403 , G11C7/00 , G11C11/34 , G11C11/401 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

7. 发明申请

US20060227642A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060227642A1
公开(公告)日：2006-10-12
申请号：US11448016
申请日：2006-06-07
申请人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
发明人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
摘要翻译：为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时发出用于从每个存储单元读取存储器信息的存储器操作的指令，每个存储器单元需要周期性地保持存储器信息的刷新操作，或者写入其中的存储器信息，执行与之前或之前的存储器操作不同的基于寻址的自主刷新操作，内存操作后。伪静态RAM包括用于行和列的地址信号转换检测器，以及根据第二地址信号转换检测器的地址信号转移检测信号独立地执行列地址选择操作的页模式。

8. 发明申请

US20050073895A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20050073895A1
公开(公告)日：2005-04-07
申请号：US10636558
申请日：2003-08-08
申请人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
发明人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
IPC分类号： G11C11/403 , G11C7/00 , G11C11/34 , G11C11/401 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
摘要翻译：为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时发出用于从每个存储单元读取存储器信息的存储器操作的指令，每个存储器单元需要周期性地保持存储器信息的刷新操作，或者写入其中的存储器信息，执行与之前或之前的存储器操作不同的基于寻址的自主刷新操作，内存操作后。伪静态RAM包括用于行和列的地址信号转换检测器，以及根据第二地址信号转换检测器的地址信号转移检测信号独立地执行列地址选择操作的页模式。

9. 发明授权

US07203116B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07203116B2
公开(公告)日：2007-04-10
申请号：US11448016
申请日：2006-06-07
申请人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
发明人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
摘要翻译：为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时发出用于从每个存储单元读取存储器信息的存储器操作的指令，每个存储器单元需要周期性地保持存储器信息的刷新操作，或者写入其中的存储器信息，执行与之前或之前的存储器操作不同的基于寻址的自主刷新操作，内存操作后。伪静态RAM包括用于行和列的地址信号转换检测器，以及根据第二地址信号转换检测器的地址信号转移检测信号独立地执行列地址选择操作的页模式。

10. 发明授权

US07082063B2 Semiconductor memory device 有权
公开(公告)号：US07082063B2
公开(公告)日：2006-07-25
申请号：US11168291
申请日：2005-06-29
申请人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
发明人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式