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21. 发明授权

US5260226A Semiconductor device having different impurity concentration wells 失效
标题翻译：具有不同杂质浓度的孔的半导体器件
公开(公告)号：US5260226A
公开(公告)日：1993-11-09
申请号：US928527
申请日：1992-08-12
申请人： Shizuo Sawada , Syuso Fujii , Masaki Ogihara
发明人： Shizuo Sawada , Syuso Fujii , Masaki Ogihara
IPC分类号： H01L21/8234 , H01L27/105 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L21/823493 , H01L27/10808 , H01L27/10829 , H01L27/105 , H01L2924/0002
摘要： A semiconductor device comprises an N-type semiconductor substrate, a first P-type well formed in the semiconductor substrate, a second P-type well formed adjacent to the first P-type well in the semiconductor substrate, the surface impurity concentration of the second P-type well being set lower than that of the first P-type well, a DRAM memory cell structure formed in the first P-type well, and an MOS transistor structure formed in the second P-type well to function in combination with the memory cell structure.
摘要翻译：半导体器件包括N型半导体衬底，在半导体衬底中形成的第一P型阱，与半导体衬底中的第一P型阱相邻形成的第二P型阱，第二P阱的表面杂质浓度 P型阱的设定比第一P型阱低，形成在第一P型阱中的DRAM存储单元结构，以及形成在第二P型阱中的MOS晶体管结构，其与记忆体结构。

22. 发明授权

US5144388A Semiconductor device having a plurality of FETs formed in an element area 失效
标题翻译：具有在元件区域形成的多个FET的半导体器件
公开(公告)号：US5144388A
公开(公告)日：1992-09-01
申请号：US664827
申请日：1991-03-05
申请人： Shizuo Sawada , Masaki Ogihara
发明人： Shizuo Sawada , Masaki Ogihara
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/06 , H01L29/423 , H01L29/78
CPC分类号： H01L27/092 , H01L27/088 , H01L29/0692 , H01L29/4238 , H01L29/7831
摘要： According to this invention, in an element region formed in a semiconductor substrate, a plurality of regions for constituting one electrode of source and drain electrodes of an FET are formed. A gate electrode is formed to surround the plurality of regions. The other electrode of the FET is formed in the element region except for the plurality of regions surrounded by the gate electrode.

23. 发明授权

US5111275A Multicell semiconductor memory device 失效
标题翻译：多芯半导体存储器件
公开(公告)号：US5111275A
公开(公告)日：1992-05-05
申请号：US286018
申请日：1988-12-19
申请人： Shizuo Sawada , Masaki Ogihara
发明人： Shizuo Sawada , Masaki Ogihara
IPC分类号： H01L23/522 , H01L21/768 , H01L21/8242 , H01L23/528 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10805 , H01L23/528 , H01L2924/0002
摘要： A semiconductor device is disclosed which connects a bit line via a bit line contact to cells in a dynamic access memory which are constructed of a transistor and capacitor. The semiconductor device includes a first conductive layer connected to the cell of a cell array via a bit line contact and a second conductive layer connected to the first conductive layer via a contact hole which is formed over the first conductive layer. By providing the first conductive layer between the bit line contact and the bit line, it is possible to increase a flat line width around a bit line contact and hence to adequately lower the bit line's resistance.
摘要翻译：公开了一种半导体器件，其将位线经由位线接触连接到由晶体管和电容器构成的动态存取存储器中的单元。半导体器件包括通过位线接触连接到单元阵列的单元的第一导电层和经由形成在第一导电层上的接触孔连接到第一导电层的第二导电层。通过在位线接触和位线之间提供第一导电层，可以增加位线接触周围的平坦线宽度，从而充分降低位线的电阻。

24. 发明授权

US5712827A Dynamic type memory 失效
标题翻译：动态类型内存
公开(公告)号：US5712827A
公开(公告)日：1998-01-27
申请号：US530725
申请日：1995-09-19
申请人： Masaki Ogihara , Satoru Takase , Kiyofumi Sakurai
发明人： Masaki Ogihara , Satoru Takase , Kiyofumi Sakurai
IPC分类号： G11C11/401 , G11C5/02 , G11C7/06 , G11C7/10 , G11C11/409 , G11C11/4093 , G11C11/4096 , G11C13/00 , G11C11/34
CPC分类号： G11C7/1012 , G11C11/4093 , G11C11/4096 , G11C5/025 , G11C7/06 , G11C7/10 , G11C7/1006
摘要： In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.
摘要翻译：在动态类型存储器中，存储器单元阵列被划分成存储器芯片上的多个子阵列。每个子阵列设置有与字线并行形成的数据线。数据缓冲器和多路复用器电路和I / O焊盘与位线并行布置在存储器芯片的一侧。这种布置允许数据路径被缩短并且能够高速传送数据。

25. 发明授权

US5550504A Dram using word line potential control circuit 失效
标题翻译：使用字线电位控制电路
公开(公告)号：US5550504A
公开(公告)日：1996-08-27
申请号：US240368
申请日：1994-05-10
申请人： Masaki Ogihara
发明人： Masaki Ogihara
IPC分类号： G11C11/407 , G11C8/08 , G11C11/4074 , G11C11/408 , G05F3/16 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4074 , G11C11/4085 , G11C11/4087
摘要： Memory cells includes at least one memory cell having an n-channel MOS transistor and an n-channel MOS capacitor. A word line is connected to the memory cells. A word line drive circuit for driving the word line includes a p-channel MOS transistor for transferring a potential to the word line. The word line drive circuit is controlled by an output from a word line potential control circuit. The word line potential control circuit applies a power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are not selected, and the word line potential control circuit applies a potential higher than a potential obtained by adding a threshold voltage of the n-channel MOS transistor to the power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are selected.
摘要翻译：存储单元包括具有n沟道MOS晶体管和n沟道MOS电容器的至少一个存储单元。字线连接到存储单元。用于驱动字线的字线驱动电路包括用于将电位传送到字线的p沟道MOS晶体管。字线驱动电路由字线电位控制电路的输出控制。当没有选择存储单元时，字线电位控制电路通过字线驱动电路中的p沟道MOS晶体管的电流路径向字线施加电源电位，并且字线电位控制电路施加电位高于通过在选择存储单元时通过字线驱动电路中的p沟道MOS晶体管的电流路径将n沟道MOS晶体管的阈值电压加到字线而获得的电位。

26. 发明授权

US5371710A Semiconductor memory device having test mode 失效
标题翻译：具有测试模式的半导体存储器件
公开(公告)号：US5371710A
公开(公告)日：1994-12-06
申请号：US46799
申请日：1993-04-16
申请人： Masaki Ogihara
发明人： Masaki Ogihara
IPC分类号： G11C29/00 , G11C8/12 , G11C11/401 , G11C11/407 , G11C29/06 , G11C29/34 , G11C29/46 , G11C29/50 , G11C13/00
CPC分类号： G11C29/50 , G11C29/34 , G11C29/46 , G11C8/12 , G11C11/401
摘要： A memory cell array, which is one of a plurality of divisional memory cell arrays, is selected by an address signal. One of the word lines incorporated in the memory cell array is selected by a row decoder. An OR circuit is supplied with a control signal for setting a burn-in test mode, and with the address signal for selecting the memory cell array. In the burn-in test mode, since the level of the control signal becomes high, the output level of the OR circuit becomes high irrespective of the address signal. Thus, the overall memory cell arrays are simultaneously selected, and hence more word lines than those accessed in a normal operation mode are simultaneously accessed.
摘要翻译：作为多个分割存储单元阵列之一的存储单元阵列由地址信号选择。结合在存储单元阵列中的字线之一由行解码器选择。 OR电路具有用于设置老化测试模式的控制信号，以及用于选择存储单元阵列的地址信号。在老化测试模式中，由于控制信号的电平变高，所以与电路信号无关，OR电路的输出电平变高。因此，同时选择整个存储单元阵列，因此与正常操作模式下访问的字线相比更多的字线被同时访问。

27. 发明授权

US5238860A Semiconductor device having different impurity concentration wells 失效
公开(公告)号：US5238860A
公开(公告)日：1993-08-24
申请号：US816565
申请日：1992-01-03
申请人： Shizuo Sawada , Syuso Fujii , Masaki Ogihara
发明人： Shizuo Sawada , Syuso Fujii , Masaki Ogihara
IPC分类号： H01L21/8234 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10808 , H01L21/823493 , H01L27/10829 , H01L27/105 , H01L2924/0002
摘要： A semiconductor device comprises an N-type semiconductor substrate, a first P-type well formed in the semiconductor substrate, a second P-type well formed adjacent to the first P-type well in the semiconductor substrate, the surface impurity concentration of the second P-type well being set lower than that of the first P-type well, a DRAM memory cell structure formed in the first P-type well, and an MOS transistor structure formed in the second P-type well to function in combination with the memory cell structure.

28. 发明授权

US5079613A Semiconductor device having different impurity concentration wells 失效
标题翻译：具有不同浓度浓度的晶体管的半导体器件
公开(公告)号：US5079613A
公开(公告)日：1992-01-07
申请号：US609076
申请日：1990-11-07
申请人： Shizuo Sawada , Syuso Fujii , Masaki Ogihara
发明人： Shizuo Sawada , Syuso Fujii , Masaki Ogihara
IPC分类号： H01L21/8234 , H01L27/105 , H01L27/108
CPC分类号： H01L21/823493 , H01L27/10808 , H01L27/10829 , H01L27/105 , H01L2924/0002
摘要： A semiconductor device comprises an N-type semiconductor substrate, a first P-type well formed in the semiconductor substrate, a second P-type well formed adjacent to the first P-type well in the semiconductor substrate, the surface impurity concentration of the second P-type well being set lower than that of the first P-type well, a DRAM memory cell structure formed in the first P-type well, and an MOS transistor structure formed in the second P-type well to function in combination with the memory cell structure.

29. 发明授权

US5586078A Dynamic type memory 失效
标题翻译：动态类型内存
公开(公告)号：US5586078A
公开(公告)日：1996-12-17
申请号：US528306
申请日：1995-09-14
申请人： Satoru Takase , Kiyofumi Sakurai , Masaki Ogihara
发明人： Satoru Takase , Kiyofumi Sakurai , Masaki Ogihara
IPC分类号： G11C11/401 , G06F12/08 , G11C11/409 , G11C11/4091 , G11C11/4096 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G06F12/0893 , G11C11/4091 , G11C11/4096
摘要： A DRAM includes memory blocks in a form of division of shared sense amplifier configuration in which sub arrays and sense amplifiers serving as cache memories are alternately arranged in the X direction of a memory chip. The memory blocks are arranged in the Y direction. Data lines are formed in parallel with the Y direction for the corresponding sub arrays, for transferring data held in the sense amplifiers corresponding to the sub arrays. I/O pads are arranged in parallel with the X direction, for inputting/outputting data to/from the corresponding sub arrays via the data lines. When the shared sense amplifier configuration and sense amplifier cache system are achieved in a small area of the DRAM, the hit rate of the cache memories is increased, and data can be transferred at high speed by shortening data paths formed in the memory chip.
摘要翻译： DRAM包括以共享读出放大器配置划分的形式的存储器块，其中用作高速缓冲存储器的子阵列和读出放大器在存储器芯片的X方向上交替排列。存储块沿Y方向排列。数据线与对应的子阵列的Y方向平行地形成，用于传送保持在与子阵列相对应的读出放大器中的数据。 I / O焊盘与X方向平行布置，用于经由数据线向/从相应的子阵列输入/输出数据。当在DRAM的小区域中实现共享读出放大器配置和读出放大器缓存系统时，高速缓冲存储器的命中率增加，并且可以通过缩短存储芯片中形成的数据路径来高速传输数据。

30. 发明授权

US5335205A DRAM using word line potential control circuitcircuit 失效
标题翻译： DRAM采用字线电位控制电路
公开(公告)号：US5335205A
公开(公告)日：1994-08-02
申请号：US757632
申请日：1991-09-11
申请人： Masaki Ogihara
发明人： Masaki Ogihara
IPC分类号： G11C11/407 , G11C8/08 , G11C11/4074 , G11C11/408 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4074 , G11C11/4085 , G11C11/4087
摘要： Memory, cells includes at least one memory cell having an n-channel MOS transistor and an n-channel MOS capacitor. A word line is connected to the memory cells. A word line drive circuit for driving the word line includes a p-channel MOS transistor for transferring a potential to the word line. The word line drive circuit is controlled by an output from a word line potential control circuit. The word line potential control circuit applies a power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are not selected, and the word line potential control circuit applies a potential higher than a potential obtained by adding a threshold voltage of the n-channel MOS transistor to the power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are selected.
摘要翻译：存储器单元包括至少一个具有n沟道MOS晶体管和n沟道MOS电容器的存储单元。字线连接到存储单元。用于驱动字线的字线驱动电路包括用于将电位传送到字线的p沟道MOS晶体管。字线驱动电路由字线电位控制电路的输出控制。当没有选择存储单元时，字线电位控制电路通过字线驱动电路中的p沟道MOS晶体管的电流路径向字线施加电源电位，并且字线电位控制电路施加电位高于通过在选择存储单元时通过字线驱动电路中的p沟道MOS晶体管的电流路径将n沟道MOS晶体管的阈值电压加到字线而获得的电位。

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