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21. 发明授权

US5381544A Copyback memory system and cache memory controller which permits access while error recovery operations are performed 失效
标题翻译：复制存储器系统和高速缓冲存储器控制器，其允许在执行错误恢复操作时进行访问
公开(公告)号：US5381544A
公开(公告)日：1995-01-10
申请号：US822110
申请日：1992-01-17
申请人： Koichi Okazawa , Kazushi Kobayashi , Ichiharu Aburano
发明人： Koichi Okazawa , Kazushi Kobayashi , Ichiharu Aburano
IPC分类号： G06F12/08 , G06F12/12 , G06F12/16 , G11C29/00 , G06F11/00
CPC分类号： G11C29/88 , G06F12/0802
摘要： A cache memory system for controlling a cache memory. The cache memory system is connected to a central processing unit and a main memory and the cache memory system is controlled to operate in a copyback operation mode. The cache memory system includes the cache memory which operates as cache memory to the central processing unit and a control circuit, responsive to detection of an error in the cache memory, for suspending an updating operation of an entry in the cache memory in which the error was detected, controlling access to valid entries in the cache memory, and causing the cache memory to operate as cache memory only when access from the central processing unit hits the valid entries of the cache memory.
摘要翻译：一种用于控制高速缓冲存储器的高速缓冲存储器系统。高速缓冲存储器系统连接到中央处理单元和主存储器，并且高速缓存存储器系统被控制为以回拷操作模式操作。高速缓冲存储器系统包括高速缓存存储器，其作为高速缓冲存储器运行到中央处理单元，以及控制电路，响应于检测到高速缓冲存储器中的错误，用于暂停高速缓冲存储器中的条目的更新操作，其中错误被检测到，控制对高速缓冲存储器中的有效条目的访问，并且仅当来自中央处理单元的访问命中高速缓冲存储器的有效条目时，才使高速缓冲存储器仅用作高速缓存存储器。

22. 发明授权

US5193196A Process request arbitration system which preferentially maintains previously selected process request upon receipt of a subsequent request of identical priority 失效
标题翻译：处理请求仲裁系统，其在接收到相同优先级的后续请求时优先维护先前选择的进程请求
公开(公告)号：US5193196A
公开(公告)日：1993-03-09
申请号：US331297
申请日：1989-03-31
申请人： Tetsuya Mochida , Shigeo Tsujioka , Masami Jikihara , Hitoshi Sadamitsu , Kazushi Kobayashi
发明人： Tetsuya Mochida , Shigeo Tsujioka , Masami Jikihara , Hitoshi Sadamitsu , Kazushi Kobayashi
IPC分类号： G06F13/30 , G06F13/364
CPC分类号： G06F13/30 , G06F13/364
摘要： A plurality of process requests generated from processing units, for example, direct memory access (DMA) channels are controlled by a preference circuit in accordance with a priority level assigned to each of the processing unit. An information of the highest priority obtained processing unit and its priority level is stored in latches. Another process requests having the same priority level as the stored processing unit are inhibited from being supplied to the preference circuit, so that the first generated process request is accepted and executed prior to acceptance of the another process requests having the same priority level.
摘要翻译：从处理单元产生的多个处理请求，例如直接存储器访问（DMA）信道由优先级电路根据分配给每个处理单元的优先级控制。最高优先级获得的处理单元及其优先级的信息被存储在锁存器中。禁止具有与存储的处理单元相同的优先级的另一处理请求被提供给偏好电路，使得在接受具有相同优先级的另一进程请求之前接受并执行第一生成的处理请求。

23. 发明申请

US20100035166A1 PHOTOSENSITIVE COMPOSITION, PARTITION WALLS, BLACK MATRIX AND PROCESS FOR PRODUCING COLOR FILTER 审中-公开
标题翻译：感光性组合物，分隔壁，黑色矩阵和生产彩色滤光片的方法
公开(公告)号：US20100035166A1
公开(公告)日：2010-02-11
申请号：US12578625
申请日：2009-10-14
申请人： Kenji Ishizeki , Kazushi Kobayashi , Hideyuki Takahashi
发明人： Kenji Ishizeki , Kazushi Kobayashi , Hideyuki Takahashi
IPC分类号： G03F1/00 , G03F7/004 , G03F7/20
CPC分类号： G03F7/0388 , G03F7/0007 , G03F7/0046 , H01L27/3295
摘要： To provide a photosensitive composition with which partition walls (black matrix) having high sensitivity to light and being excellent in liquid repellency, and pixels excellent in the uniformity in the ink layer thickness, can be formed.A photosensitive composition, which comprises a fluoropolymer (A) having a side chain containing a group such as —(CF2)6F and a side chain containing an ethylenic double bond in one molecule, an alkali soluble photosensitive resin (B), a photopolymerization initiator (C), a black pigment (D), a polymer dispersing agent (E) having basic functional groups, and fine particles (F) other than the black pigment (D).
摘要翻译：为了提供一种光敏组合物，可以形成具有对光的高灵敏度和疏液性优异的分隔壁（黑矩阵）和油墨层厚度均匀性优异的像素。一种感光性组合物，其包含具有侧链的含氟聚合物（A），其含有 - （CF 2）6 F等基团，在1分子中含有乙烯性双键的侧链，碱溶性感光性树脂（B），光聚合引发剂（C），黑色颜料（D），具有碱性官能团的高分子分散剂（E）和黑色颜料（D）以外的微粒（F）。

24. 发明授权

US06598139B2 Information processing apparatus 有权
公开(公告)号：US06598139B2
公开(公告)日：2003-07-22
申请号：US09983417
申请日：2001-10-24
申请人： Hitoshi Kawaguchi , Koichi Kimura , Hideki Kamimaki , Takayuki Tamura , Kazushi Kobayashi
发明人： Hitoshi Kawaguchi , Koichi Kimura , Hideki Kamimaki , Takayuki Tamura , Kazushi Kobayashi
IPC分类号： G06F1314
CPC分类号： G06F13/1689
摘要： An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.

25. 发明授权

US06570580B1 Apparatus and method for information display 有权
标题翻译：信息显示装置及方法
公开(公告)号：US06570580B1
公开(公告)日：2003-05-27
申请号：US09440286
申请日：1999-11-15
申请人： Hitoshi Suzuki , Naohisa Koizumi , Goro Ohnishi , Tomohisa Kohiyama , Kazushi Kobayashi , Takeshi Igarashi , Hironori Oikawa , Hiroyuki Mano
发明人： Hitoshi Suzuki , Naohisa Koizumi , Goro Ohnishi , Tomohisa Kohiyama , Kazushi Kobayashi , Takeshi Igarashi , Hironori Oikawa , Hiroyuki Mano
IPC分类号： G09G524
CPC分类号： G06F3/1446 , Y10S715/963
摘要： An apparatus for information display for displaying not only periodic information in accordance with schedule, but also non-periodic information regardless of the schedule, to passengers and passersby in stations, airports, harbors, bus terminals and streets, and the like. The apparatus comprises an information-storing section for storing a plurality of non-periodic information to be displayed regardless of the schedule, an input circuit for receiving a plurality of input signals transmitted from an external device or a remote place and display control section for simultaneously displaying the non-periodic information and periodic information which correspond to the kind of an input signal, when the apparatus receives this input signal from the external apparatus or the remote place. The apparatus may be a multi-screen display type having a plurality of screens. In this case, a combined screen data consisting of a non-periodic information and a periodic information can be displayed, or the non-periodic information or the periodic information can be displayed, on at least one of the screens.
摘要翻译：一种用于信息显示的装置，不仅根据时间表显示周期性信息，而且还可以不依赖于时间表显示非周期性信息给站，机场，港口，公共汽车站和街道等中的乘客和路人。该装置包括一个信息存储部分，用于存储要被显示的多个非周期性信息，而不管时间表如何;输入电路，用于接收从外部设备或远程位置发送的多个输入信号以及同时显示控制部分当设备从外部设备或远程位置接收到该输入信号时，显示与输入信号的种类相对应的非周期信息和周期性信息。该装置可以是具有多个屏幕的多屏显示类型。在这种情况下，可以在至少一个屏幕上显示由非周期性信息和周期性信息组成的组合屏幕数据，或者可以显示非周期性信息或周期性信息。

26. 发明授权

US06334164B1 Bus system for use with information processing apparatus 失效
标题翻译：与信息处理设备一起使用的总线系统
公开(公告)号：US06334164B1
公开(公告)日：2001-12-25
申请号：US09690998
申请日：2000-10-18
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F1314
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

27. 发明授权

US06195719B1 Bus system for use with information processing apparatus 失效
标题翻译：与信息处理设备一起使用的总线系统
公开(公告)号：US06195719B1
公开(公告)日：2001-02-27
申请号：US09518696
申请日：2000-03-03
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F1314
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and controL buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。该控制系统包括总线存储器连接控制器，分别连接到地址总线和分别由处理器，存储器和系统总线控制的总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

28. 发明授权

US6006302A Multiple bus system using a data transfer unit 失效
标题翻译：多总线系统使用数据传输单元
公开(公告)号：US6006302A
公开(公告)日：1999-12-21
申请号：US276968
申请日：1999-03-26
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/40 , G06F13/14
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

29. 发明授权

US5749093A Enhanced information processing system using cache memory indication during DMA accessing 失效
标题翻译：在DMA访问期间使用高速缓存存储器指示的增强型信息处理系统
公开(公告)号：US5749093A
公开(公告)日：1998-05-05
申请号：US389080
申请日：1995-02-14
申请人： Kazushi Kobayashi , Takeshi Aoki , Koichi Okazawa , Ichiharu Aburano
发明人： Kazushi Kobayashi , Takeshi Aoki , Koichi Okazawa , Ichiharu Aburano
IPC分类号： G06F12/02 , G06F12/08 , G06F12/10 , G06F13/12 , G06F13/28
CPC分类号： G06F12/1081 , G06F12/0835 , G06F13/28 , G06F12/0292
摘要： An information processing system includes a central processing unit, a main storage, a main storage controller for controlling the main storage, a cache memory having a content of at least one part of addresses stored in the main storage, at least one DMA controller which is capable of referring to the main storage and a DMA address translation unit for translating a logical address outputted from the DMA controller into a physical address for referring to the main storage. The DMA address translation unit has a flag representing whether or not the cache memory is referred to on DMA. The main storage controller performs either of reference to the cache memory or direct reference to the main storage based upon the flag on DMA.
摘要翻译：信息处理系统包括中央处理单元，主存储器，用于控制主存储器的主存储控制器，具有存储在主存储器中的至少一部分地址的内容的高速缓存存储器，至少一个DMA控制器，能够参考主存储器和DMA地址转换单元，用于将从DMA控制器输出的逻辑地址转换为用于参考主存储器的物理地址。 DMA地址转换单元具有表示在DMA上是否参考高速缓冲存储器的标志。主存储控制器根据DMA上的标志执行对高速缓冲存储器的引用或对主存储器的直接引用。

30. 发明授权

US5506973A Bus system for use with information processing apparatus 失效
公开(公告)号：US5506973A
公开(公告)日：1996-04-09
申请号：US443361
申请日：1995-05-17
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/16 , G06F12/00 , G06F13/36 , G06F13/40 , G06F13/14
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

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