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    • 24. 发明申请
      US20070212121A1 DEVELOPING DEVICE USING ELECTROSTATIC TRANSPORT & HOPPING (ETH) 失效
    • DEVELOPING DEVICE USING ELECTROSTATIC TRANSPORT & HOPPING (ETH)
    • 使用静电运输（ETH）开发设备
    • US20070212121A1
    • 2007-09-13
    • US11681940
    • 2007-03-05
    • Tomoko TAKAHASHI , Katsuhiro AOKI , Hideki ZEMBA
    • Tomoko TAKAHASHI , Katsuhiro AOKI , Hideki ZEMBA
    • G03G15/08
    • G03G15/065 , G03G15/0813
    • A developing device, process cartridge, and image forming apparatus that use ETH development, and are capable of forming good multi-color images with a simple construction, and are capable of preventing the dispersal of powder. The developing device is for developing latent images on a latent image carrying member by applying powder to the latent image carrying member, and comprises: a transport member disposed in opposition to the latent image carrying member and having a plurality of transport electrodes that generate a progressive wave electric field to move the powder; a voltage supply device for applying a multi-phase voltage to the transport electrodes; and a transport member surface potential determination device for determining the surface potential of the transport member. The voltage supply device in the developing device according to the present invention applies a multi-phase voltage to the transport electrodes so that the surface potential on the transport member is between the potential of the image portions and the potential of the non-image portions of the latent image carrying member.
    • 使用ETH显影的显影装置，处理盒和成像装置，能够以简单的结构形成良好的多色图像，并且能够防止粉末的分散。 显影装置用于通过将粉末施加到潜像承载构件上而在潜像承载构件上显影潜像，并且包括：与潜像承载构件相对设置的传送构件，并且具有多个传送电极，其产生渐进 波电场移动粉末; 用于向所述输送电极施加多相电压的电压供给装置; 以及传送构件表面电位确定装置，用于确定传送构件的表面电位。 根据本发明的显影装置中的电压供应装置向输送电极施加多相电压，使得输送部件上的表面电位在图像部分的电位和非图像部分的电位之间 潜像携带部件。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 26. 发明申请
      US20060198663A1 Developing device, and image forming apparatus and process cartridge using the developing device 有权
    • Developing device, and image forming apparatus and process cartridge using the developing device
    • 显影装置，以及使用显影装置的图像形成装置和处理盒
    • US20060198663A1
    • 2006-09-07
    • US11363052
    • 2006-02-28
    • Yasuo Miyoshi , Hajime Oyama , Katsuhiro Aoki , Hiroshi Ikeguchi , Daichi Yamaguchi
    • Yasuo Miyoshi , Hajime Oyama , Katsuhiro Aoki , Hiroshi Ikeguchi , Daichi Yamaguchi
    • G03G15/08
    • G03G15/0808 , G03G15/0812 , G03G2215/0634
    • A developing device including a rotating developing roller bearing toner thereon, capable of developing an electrostatic latent image with the toner; a toner layer forming member configured to form a toner layer on the developing roller, and charge the toner of the toner layer at a nip between the developing roller and the toner layer forming member; and a toner supplying device configured to supply fresh toner to the developing device, wherein a charge quantity (q) of the toner on the developing roller varies according to the following equation q(t)=A·{1−exp(−t/tg)} wherein t represents a nip passing time of the toner on the developing roller, tg represents a time constant of charging the toner, and A represents a constant, and wherein the time constant tg is smaller than a rotation time of the developing roller per rotation; and an image forming apparatus and a process cartridge using the developing device.
    • 一种显影装置，包括在其上承载调色剂的旋转显影辊，能够利用调色剂显影静电潜像; 调色剂层形成部件，被配置为在所述显影辊上形成调色剂层，并且在所述显影辊和所述调色剂层形成部件之间的辊隙处对所述调色剂层的调色剂充电; 以及调色剂供应装置，其被配置为向显影装置供应新鲜的调色剂，其中显影辊上的调色剂的电荷量（q）根据以下等式q（t）= A。{1-exp（-t / t表示调色剂在显影辊上的辊隙通过时间，t表示调色剂的充电时间常数，A表示常数， 并且其中所述时间常数t T g小于每旋转一次所述显影辊的旋转时间; 以及使用该显影装置的图像形成装置和处理盒。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 29. 发明授权
      US06728128B2 Dummy cell structure for 1T1C FeRAM cell array 有权
    • Dummy cell structure for 1T1C FeRAM cell array
    • 1T1C FeRAM单元阵列的虚拟单元结构
    • US06728128B2
    • 2004-04-27
    • US10397878
    • 2003-03-26
    • Akitoshi Nishimura , Yukio Fukuda , Katsuhiro Aoki
    • Akitoshi Nishimura , Yukio Fukuda , Katsuhiro Aoki
    • G11C1122
    • G11C11/22 , G11C7/14
    • A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state. As charge sharing takes place between the bias states of the dummy cells and the shorted bitlines, an averaged reference voltage is produced which is substantially centered between the “0” or “1” states. A sense amplifier receives a sense signal from the target memory cell on an associated bitline, and the averaged reference voltage is received on another bitline input of the sense amplifier. Thus, a new ferroelectric memory structure provides a centered reference voltage and a simple sensing scheme for the accurate sensing of the logic state of an FeRAM 1T1C cell for a read operation.
    • 对于FeRAM存储器件应用的铁电电容器单元阵列中的1T1C布置描述了铁电存储器结构。 器件结构为读取FeRAM阵列的目标存储单元的状态的读出放大器提供精确的参考电压和简单的感测方案。 参考电路产生参考电压，其是在多个FeRAM虚拟单元之间共享的电荷的函数。 多个FeRAM虚拟单元中的每个虚拟单元选择性地耦合到多个位线。 参考电路中的短路晶体管将与所选择的目标存储器单元相邻的两个位线或两个位线条耦合。 一个虚拟单元耦合到两个短路位线或位线条中的选择一个，另一个虚设单元耦合到两个短路位线或位线条中的另一个，其中至少一个虚设单元偏置为“0” “状态，并且至少一个其他虚拟单元被偏置到”1“状态。 由于在虚设单元的偏置状态和短路位线之间发生电荷共享，产生基本上以“0”或“1”状态为中心的平均参考电压。 感测放大器在相关联的位线上接收来自目标存储器单元的感测信号，并且平均参考电压在读出放大器的另一位线输入端上被接收。 因此，新的铁电存储器结构提供了居中的参考电压和用于精确检测用于读取操作的FeRAM 1T1C单元的逻辑状态的简单感测方案。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 30. 发明授权
      US06724646B2 Dummy cell structure for 1T1C FeRAM cell array 有权
    • Dummy cell structure for 1T1C FeRAM cell array
    • US06724646B2
    • 2004-04-20
    • US10397409
    • 2003-03-26
    • Akitoshi Nishimura , Yukio Fukuda , Katsuhiro Aoki
    • Akitoshi Nishimura , Yukio Fukuda , Katsuhiro Aoki
    • G11C1122
    • G11C11/22 , G11C7/14
    • A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state. As charge sharing takes place between the bias states of the dummy cells and the shorted bitlines, an averaged reference voltage is produced which is substantially centered between the “0” or “1” states. A sense amplifier receives a sense signal from the target memory cell on an associated bitline, and the averaged reference voltage is received on another bitline input of the sense amplifier. Thus, a new ferroelectric memory structure provides a centered reference voltage and a simple sensing scheme for the accurate sensing of the logic state of an FeRAM 1T1C cell for a read operation.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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