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21. 发明申请

US20110090651A1 PACKAGE STRUCTURE 审中-公开
标题翻译：包装结构
公开(公告)号：US20110090651A1
公开(公告)日：2011-04-21
申请号：US12765619
申请日：2010-04-22
申请人： Sunghae Jung , Dong Suk Jun , Jong Tae Moon , Hyun-cheol Bae , Moo Jung Chu
发明人： Sunghae Jung , Dong Suk Jun , Jong Tae Moon , Hyun-cheol Bae , Moo Jung Chu
IPC分类号： H05K7/00
CPC分类号： H03H9/0557 , H01L2224/48091 , H01L2924/1461 , H03H9/0514 , H03H9/1014 , H01L2924/00014 , H01L2924/00
摘要： Provided is a package structure. The package structure includes a first substrate, a first device, a second substrate, a first via contact, and at least one second device. The first device is formed on the first substrate. The second substrate has an air gap over the first substrate and covers the first device. The first via contact is connected to the first device through the second substrate. At least one second device is electrically connected to the first via contact, and is stacked on the second substrate.
摘要翻译：提供了一种封装结构。封装结构包括第一衬底，第一器件，第二衬底，第一通孔触点和至少一个第二器件。第一装置形成在第一基板上。第二基板在第一基板上具有空隙并覆盖第一装置。第一通孔接触件通过第二基板连接到第一器件。至少一个第二装置电连接到第一通孔接触件，并且堆叠在第二基板上。

22. 发明申请

US20110089577A1 METHOD AND STRUCTURE FOR BONDING FLIP CHIP 有权
标题翻译：用于粘接卷芯片的方法和结构
公开(公告)号：US20110089577A1
公开(公告)日：2011-04-21
申请号：US12761715
申请日：2010-04-16
申请人： Yong Sung Eom , Jong Tae Moon , Kwang-Seong Choi
发明人： Yong Sung Eom , Jong Tae Moon , Kwang-Seong Choi
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L25/50 , H01L24/29 , H01L2224/114 , H01L2224/1152 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/1403 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/2929 , H01L2224/73104 , H01L2224/73204 , H01L2224/81191 , H01L2224/83101 , H01L2224/83138 , H01L2224/83191 , H01L2225/06513 , H01L2225/06575 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/15787 , H01L2924/01083 , H01L2924/00014 , H01L2924/00012
摘要： Provided is a method and structure for bonding a flip chip while increasing the manufacturing yield. In the method, solder bumps are formed on first electrodes and/or second electrodes disposed on first and second substrates, respectively. In addition, the first and second electrodes are arranged to face each other with a second resin including spacer balls being disposed between the first and second substrates. In addition, while flowing the second resin, the first and second substrates are pressed until the distance between the first and second substrates is decreased smaller than diameter of the spacer balls so as to connect the solder bumps between the first and second electrodes.
摘要翻译：提供了一种在提高制造成品率的同时将倒装芯片接合的方法和结构。在该方法中，分别在设置在第一和第二基板上的第一电极和/或第二电极上形成焊料凸点。此外，第一和第二电极被布置成使第二树脂彼此面对，该第二树脂包括设置在第一和第二基板之间的间隔球。此外，在流动第二树脂时，第一和第二基板被压制直到第一和第二基板之间的距离小于间隔球的直径，以便连接第一和第二电极之间的焊料凸块。

23. 发明授权

US07733207B2 Vertically formed inductor and electronic device having the same 失效
标题翻译：垂直成型的电感器和具有该电感器的电子器件
公开(公告)号：US07733207B2
公开(公告)日：2010-06-08
申请号：US12053716
申请日：2008-03-24
申请人： Ho Gyeong Yun , Kwang Seong Choi , Jong Tae Moon
发明人： Ho Gyeong Yun , Kwang Seong Choi , Jong Tae Moon
IPC分类号： H01F5/00 , H01F21/02 , H01F27/28
CPC分类号： H01F17/0013 , H01F17/0033 , H01F27/34 , H01F2017/002
摘要： Provided are an inductor, which is vertically formed, and an electronic device having the inductor, and more particularly, an inductor capable of minimizing loss of a surface area and accomplishing high efficiency impedance by vertically forming the inductor in a plurality of insulating layers, and an electronic device having the same. The inductor includes a plurality of conductive lines disposed in the insulating layers; and vias vertically formed in the insulating layers to electrically connect the plurality of conductive lines. When a board or an electronic device including an inductor proposed by the present invention is manufactured, the inductor can occupy a minimum area in the electronic device or board while providing high inductance. In particular, the surface area of the electronic device or board occupied by the inductor can be remarkably decreased to reduce manufacturing costs.
摘要翻译：提供了一种垂直形成的电感器，以及具有电感器的电子器件，更具体地说，一种电感器，其能够通过在多个绝缘层中垂直形成电感器来最小化表面积的损失并实现高效率阻抗，以及具有该电子设备的电子设备。电感器包括布置在绝缘层中的多条导线; 以及在绝缘层中垂直形成的通孔，以电连接多条导线。当制造包括由本发明提出的电感器的电路板或电子设备时，电感器可以在提供高电感的同时占据电子设备或电路板中的最小面积。特别地，电感器占用的电子设备或板的表面积可以显着降低，从而降低制造成本。

24. 发明申请

US20050046868A1 System for monitoring optical output/wavelength 失效
标题翻译：监控光输出/波长的系统
公开(公告)号：US20050046868A1
公开(公告)日：2005-03-03
申请号：US10802095
申请日：2004-03-15
申请人： Jong-Deog Kim , Byung-Seok Choi , Jong-Hyun Lee , Hogyeong Yun , Kwang-Seong Choi , Jong-Tae Moon
发明人： Jong-Deog Kim , Byung-Seok Choi , Jong-Hyun Lee , Hogyeong Yun , Kwang-Seong Choi , Jong-Tae Moon
IPC分类号： H04B10/08 , G01B9/02 , G02B6/34 , H01S5/024 , H01S5/0683
CPC分类号： H01S5/0612 , H01S5/0683 , H01S5/0687
摘要： A system for monitoring an optical output/wavelength is employed to be used for a WDM system having a narrow channel space by structuring an etalon and photodiode as an integrated structure. The system includes: a laser source control unit for controlling the laser source; an optical/wavelength monitoring unit for monitoring an optical output/wavelength of the controlled laser source; a TEC control unit for controlling a TEC in order to constantly maintain the laser source of the optical output/wavelength monitoring unit to have a predetermined temperature; a temperature control unit for controlling a heater and a thermistor to set an etalon to a predetermined temperature, wherein the heater is attached on the optical output/wavelength monitoring unit and the thermistor is attached on the heater; a comparison unit for comparing the optical output signal and the wavelength signal, each of which is monitored by the optical output/wavelength monitoring unit; and a processing unit for comparing values of the compared signals with a preset value to control an input current or a temperature of the laser source.
摘要翻译：用于监测光输出/波长的系统被用于通过构造标准具和光电二极管作为一体结构而具有窄通道空间的WDM系统。该系统包括：用于控制激光源的激光源控制单元; 用于监测受控激光源的光输出/波长的光/波长监测单元; 用于控制TEC的TEC控制单元，以便将光输出/波长监视单元的激光源恒定地保持为预定温度; 温度控制单元，用于控制加热器和热敏电阻以将标准具设定到预定温度，其中加热器安装在光输出/波长监测单元上，热敏电阻附着在加热器上; 比较单元，用于比较光输出信号和波长信号，每个波长信号由光输出/波长监测单元监视; 以及处理单元，用于将比较的信号的值与预设值进行比较，以控制激光源的输入电流或温度。

25. 发明授权

US06297543B1 Chip scale package 失效
标题翻译：芯片级封装
公开(公告)号：US06297543B1
公开(公告)日：2001-10-02
申请号：US09455669
申请日：1999-12-07
申请人： Sung Hak Hong , Jong Tae Moon , Chang Jun Park , Yoon Hwa Choi
发明人： Sung Hak Hong , Jong Tae Moon , Chang Jun Park , Yoon Hwa Choi
IPC分类号： H01L23495
CPC分类号： H01L23/3114 , H01L24/45 , H01L24/48 , H01L2224/32014 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/00 , H01L2224/05599
摘要： The present invention discloses a chip scale package. According to this invention, a lead frame 130 is bonded with an adhesive 140 to a bottom face of a semiconductor chip 110. An inner lead 131 of the lead frame 130 is connected to a pad 111 of the semiconductor chip with a metal wire 120, and thickness of the inner lead 131 is equal to an original thickness of the lead frame 130. An outer lead 132 of the lead frame 130 is formed by partially etching a bottom face of the lead frame 130. The entire resultant is encapsulated with a molding compound 100 such that the outer lead 132 is exposed therefrom, especially there is formed a downward protruding portion 101 at the molding compound 100 in the lower inner lead portion 131. This protruding portion raises the margin controlling the bonding height during the wire-bonding process such that the metal wire 120 is not exposed from the molding compound 100. Furthermore, the outer leads 134 at both sides where no solder balls are mounted on, are exposed from the molding compound 100. The outer leads 132 at both sides being exposed from the molding compound 100 act for dissipating outwardly heat that is transmitted from the semiconductor chip 110 to the lead frame 130. A solder ball 150 is mounted at the inside of the outer lead 132 exposed from the molding compound 100.
摘要翻译：本发明公开了一种芯片级封装。根据本发明，引线框架130用粘合剂140粘合到半导体芯片110的底面。引线框架130的内引线131通过金属线120连接到半导体芯片的焊盘111，并且内引线131的厚度等于引线框架130的原始厚度。引线框架130的外引线132通过部分蚀刻引线框架130的底面而形成。整个结合物被封装成型化合物100，使得外引线132暴露于其中，特别是在下内引线部分131中的模塑料100处形成向下突出部分101.该突出部分在引线接合过程中增加控制接合高度的边缘使得金属线120不会从模塑料100暴露出来。此外，没有焊球的两侧的外引线134从模塑料100露出。外部的I 从模制化合物100露出的两侧的阴极132用于散发从半导体芯片110传递到引线框架130的向外的热。焊球150安装在从模塑料暴露的外引线132的内部 100。

26. 发明授权

US08598768B2 Piezoelectric micro energy harvester and manufacturing method thereof 有权
标题翻译：压电微能收割机及其制造方法
公开(公告)号：US08598768B2
公开(公告)日：2013-12-03
申请号：US13316590
申请日：2011-12-12
申请人： Chi Hoon Jun , Sang Choon Ko , Jong Tae Moon
发明人： Chi Hoon Jun , Sang Choon Ko , Jong Tae Moon
IPC分类号： H01L41/08
CPC分类号： H01L41/29 , H01L41/1136 , H01L41/31 , H01L41/316 , H01L41/317 , H01L41/318 , H02N2/188 , Y10T29/42
摘要： Disclosed is a piezoelectric micro energy harvester and manufacturing method thereof, the method including: forming an insulation film on a substrate; patterning the insulation film and forming an electrode pad pattern, a center electrode pattern, and a side electrode pattern; forming an open cavity at an inside of the substrate for suspension of the center electrode pattern and the side electrode pattern; disposing a conductive film on the electrode pad pattern, the center electrode pattern, and the side electrode pattern and forming electrode pads, a center electrode, and a side electrode; and forming a piezoelectric film so as to cover a space between the center electrode and the side electrode and upper surfaces of the center electrode and the side electrode.
摘要翻译：公开了一种压电微能量收集器及其制造方法，该方法包括：在基板上形成绝缘膜; 图案化绝缘膜并形成电极焊盘图案，中心电极图案和侧面电极图案; 在所述基板的内部形成开放空腔，以悬浮所述中心电极图案和所述侧面电极图案; 在电极焊盘图形，中心电极图案和侧面电极图案上设置导电膜，形成电极焊盘，中心电极和侧面电极; 以及形成压电膜以覆盖中心电极和侧电极之间的空间以及中心电极和侧电极的上表面。

27. 发明申请

US20120161326A1 COMPOSITION FOR FILLING THROUGH SILICON VIA (TSV), TSV FILLING METHOD AND SUBSTRATE INCLUDING TSV PLUG FORMED OF THE COMPOSITION 审中-公开
标题翻译：用于通过硅（TSV）填充的组合物，TSV填充方法和包括形成组合物的TSV插入物的基底
公开(公告)号：US20120161326A1
公开(公告)日：2012-06-28
申请号：US13330719
申请日：2011-12-20
申请人： Kwang-Seong Choi , Yong Sung Eom , Hyun-cheol Bae , Jong Tae Moon
发明人： Kwang-Seong Choi , Yong Sung Eom , Hyun-cheol Bae , Jong Tae Moon
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/486 , H01L23/147 , H01L23/49827 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： Provided is a composition for filling a Through Silicon Via (TSV) including: a metal powder; a solder powder; a curable resin; a reducing agent; and a curing agent. A TSV filling method using the composition and a substrate including a TSV plug formed of the composition are also provided.
摘要翻译：提供了一种用于填充通硅（TSV）的组合物，其包括：金属粉末; 焊粉; 可固化树脂; 还原剂; 和固化剂。还提供了使用该组合物的TSV填充方法和包含由该组合物形成的TSV塞的基板。

28. 发明申请

US20120153778A1 PIEZOELECTRIC MICRO ENERGY HARVESTER AND MANUFACTURING METHOD THEREOF 有权
标题翻译：压电微型收割机及其制造方法
公开(公告)号：US20120153778A1
公开(公告)日：2012-06-21
申请号：US13316590
申请日：2011-12-12
申请人： Chi Hoon JUN , Sang Choon KO , Jong Tae MOON
发明人： Chi Hoon JUN , Sang Choon KO , Jong Tae MOON
IPC分类号： H02N2/18 , H01L41/22
CPC分类号： H01L41/29 , H01L41/1136 , H01L41/31 , H01L41/316 , H01L41/317 , H01L41/318 , H02N2/188 , Y10T29/42
摘要： Disclosed is a piezoelectric micro energy harvester and manufacturing method thereof, the method including: forming an insulation film on a substrate; patterning the insulation film and forming an electrode pad pattern, a center electrode pattern, and a side electrode pattern; forming an open cavity at an inside of the substrate for suspension of the center electrode pattern and the side electrode pattern; disposing a conductive film on the electrode pad pattern, the center electrode pattern, and the side electrode pattern and forming electrode pads, a center electrode, and a side electrode; and forming a piezoelectric film so as to cover a space between the center electrode and the side electrode and upper surfaces of the center electrode and the side electrode.
摘要翻译：公开了一种压电微能量收集器及其制造方法，该方法包括：在基板上形成绝缘膜; 图案化绝缘膜并形成电极焊盘图案，中心电极图案和侧面电极图案; 在所述基板的内部形成开放空腔，以悬浮所述中心电极图案和所述侧面电极图案; 在电极焊盘图形，中心电极图案和侧面电极图案上设置导电膜，形成电极焊盘，中心电极和侧面电极; 以及形成压电膜以覆盖中心电极和侧电极之间的空间以及中心电极和侧电极的上表面。

29. 发明授权

US08044757B2 Electronic device including LTCC inductor 失效
标题翻译：电子器件包括LTCC电感
公开(公告)号：US08044757B2
公开(公告)日：2011-10-25
申请号：US12648117
申请日：2009-12-28
申请人： Hyun-Cheol Bae , Kwang-Seong Choi , Yong Sung Eom , Jong Tae Moon , Moo Jung Chu , Jong-Hyun Lee
发明人： Hyun-Cheol Bae , Kwang-Seong Choi , Yong Sung Eom , Jong Tae Moon , Moo Jung Chu , Jong-Hyun Lee
IPC分类号： H01F5/00 , H01F27/29 , H01F27/28 , H01L23/34 , H01L23/48
CPC分类号： H01F17/0013 , H01F2017/002 , H01L2224/48091 , H01L2224/73257 , H01L2924/19107 , H01L2924/00014
摘要： Provided is an electronic device that includes an LTCC inductor including a first sheet disposed on a substrate and including a first conductive pattern, a second sheet disposed on the first sheet and including a second conductive pattern, and a via electrically connecting the first conductive pattern to the second conductive pattern, and a spacer disposed on a lower surface of the first sheet to provide an air gap between the substrate and the first sheet, wherein the first conductive pattern is exposed out of the lower surface of the first sheet.
摘要翻译：提供一种电子设备，其包括LTCC电感器，其包括设置在基板上的第一片，并且包括第一导电图案，设置在第一片上并包括第二导电图案的第二片，以及将第一导电图案电连接到第二导电图案和设置在第一片的下表面上的间隔件，以在基片和第一片之间提供气隙，其中第一导电图案从第一片的下表面露出。

30. 发明申请

US20110115036A1 DEVICE PACKAGES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：装置包装及其制造方法
公开(公告)号：US20110115036A1
公开(公告)日：2011-05-19
申请号：US12768551
申请日：2010-04-27
申请人： Jong Tae MOON , Jong-Hyun Lee , Dong Suk Jun , Hyun-cheol Bae , Sunghae Jung , Moo Jung Chu
发明人： Jong Tae MOON , Jong-Hyun Lee , Dong Suk Jun , Hyun-cheol Bae , Sunghae Jung , Moo Jung Chu
IPC分类号： H01L29/84 , H01L21/60 , H01L23/488
CPC分类号： H01L21/6835 , B81B2207/093 , B81B2207/097 , B81C1/00269 , B81C2203/0109 , B81C2203/0127 , B81C2203/019 , B81C2203/032 , B81C2203/035 , H01L23/04 , H01L23/10 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/01014 , H01L2924/01028 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/07802 , H01L2924/09701 , H01L2924/10253 , H01L2924/1461 , H01L2924/16235 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Provided is a method for fabricating a device package. The method includes: preparing a substrate where respectively corresponding device structures and input and output pads are disposed on an active surface; preparing a carrier substrate where a metal lid corresponding to the device structure is disposed on one surface; and contacting the active surface of the substrate with the metal lid of the carrier substrate to cover and seal the device structure corresponding to the metal lid.
摘要翻译：提供了一种用于制造器件封装的方法。该方法包括：准备衬底，其中分别对应的器件结构和输入和输出焊盘设置在有源表面上; 准备载体基板，其中与所述装置结构相对应的金属盖设置在一个表面上; 并使基板的活性表面与载体基板的金属盖接触，以覆盖并密封与金属盖对应的装置结构。

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