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21. 发明授权

US5764952A Diagnostic system including a LSI or VLSI integrated circuit with a diagnostic data port 失效
标题翻译：诊断系统包括具有诊断数据端口的LSI或VLSI集成电路
公开(公告)号：US5764952A
公开(公告)日：1998-06-09
申请号：US450456
申请日：1995-05-25
申请人： John P. Hill
发明人： John P. Hill
IPC分类号： G01R31/3185 , G06F11/267 , G06F11/273 , G11C29/32 , G01R31/28 , G06F3/00
CPC分类号： G06F11/2221 , G01R31/318572 , G06F11/2733 , G11C29/32
摘要： A two-wire dedicated diagnostic data port in an integrated circuit provides visibility for all internal functions of the integrated circuit. An internal signal or signals are written to a serially connected memory in the dedicated diagnostic data port. The serially connected memory is connected to a two-wire output port of the dedicated diagnostic data port. A first wire in the two-wire output port is a data wire and a second wire in the two-wire output port is a clock wire. Transfer of the stored information from the serially connected memory to the two-wire output port is initiated by writing to a control register in the dedicated diagnostic data port. In response to writing to the control register, a clock signal on a clock input line to the dedicated diagnostic data port is coupled to the second wire, and is used to serially shift the stored information from the serially connected memory to the data wire. The signals on the two-wires from the integrated circuit are processed by a shift/latch control circuit that is external to the integrated circuit. A predetermined time after the clock signal on the clock wire terminates, i.e., remains inactive for a predetermined period, the shift/latch control circuit generates a latch signal that can be used to capture the data transmitted over the data wire.
摘要翻译：集成电路中的两线专用诊断数据端口为集成电路的所有内部功能提供可见性。将内部信号或信号写入专用诊断数据端口中的串行存储器。串行连接的存储器连接到专用诊断数据端口的两线输出端口。双线输出端口中的第一根导线是数据线，二线输出端口中的第二根导线是时钟导线。将存储的信息从串行连接的存储器传送到两线输出端口是通过写入专用诊断数据端口中的控制寄存器来启动的。响应于向控制寄存器的写入，到专用诊断数据端口的时钟输入线上的时钟信号被耦合到第二线，并且用于将存储的信息从串行连接的存储器顺序地移位到数据线。来自集成电路的两线上的信号由集成电路外部的移位/锁存控制电路处理。在时钟线上的时钟信号终止之后的预定时间，即在预定时间段内保持不活动，移位/锁存控制电路产生可用于捕获通过数据线发送的数据的锁存信号。

22. 发明授权

US5684972A Programmable servo burst sequencer for a disk drive 失效
标题翻译：用于磁盘驱动器的可编程伺服脉冲序列发生器
公开(公告)号：US5684972A
公开(公告)日：1997-11-04
申请号：US294234
申请日：1994-08-22
申请人： John P. Hill , David L. Dyer , Nicolas C. Assoud
发明人： John P. Hill , David L. Dyer , Nicolas C. Assoud
IPC分类号： G11B5/596 , G06F13/00 , G05B19/29
CPC分类号： G11B5/59605 , G11B5/59688
摘要： An integrated circuit includes a programmable servo burst sequencer that includes an instruction memory, an instruction register, and an address control circuit. The instruction register drives a plurality of output lines of the programmable servo burst sequencer. The programmable servo burst sequencer can process a plurality of fields in any one of a plurality of servo sectors. The programmable servo burst sequencer eliminates the need for a specific servo burst sequencer for each possible configuration of the plurality of fields in a servo sector. The user simply uses a plurality of instructions to configure the programmable servo burst sequencer so that the programmed servo burst sequencer can process the plurality of fields in the servo sector information on the user's disk drive.
摘要翻译：集成电路包括可编程伺服脉冲序列发生器，其包括指令存储器，指令寄存器和地址控制电路。指令寄存器驱动可编程伺服脉冲序列发生器的多条输出线。可编程伺服脉冲序列发生器可以处理多个伺服扇区中的任何一个中的多个场。可编程伺服脉冲序列发生器消除了对伺服扇区中的多个场的每个可能配置的特定伺服脉冲序列发生器的需要。用户简单地使用多个指令来配置可编程伺服脉冲序列发生器，使得编程的伺服脉冲序列发生器可以处理用户磁盘驱动器上的伺服扇区信息中的多个场。

23. 发明授权

US5544107A Diagnostic data port for a LSI or VLSI integrated circuit 失效
标题翻译：用于LSI或VLSI集成电路的诊断数据端口
公开(公告)号：US5544107A
公开(公告)日：1996-08-06
申请号：US294127
申请日：1994-08-22
申请人： John P. Hill
发明人： John P. Hill
IPC分类号： G01R31/3185 , G06F11/267 , G06F11/273 , G11C29/32 , H03K19/177 , G06F11/26
CPC分类号： G06F11/2221 , G01R31/318572 , G06F11/2733 , G11C29/32
摘要： A two-wire dedicated diagnostic data port in an integrated circuit provides visibility for all internal functions of the integrated circuit. An internal signal or signals are written to a serially connected memory in the dedicated diagnostic data port. The serially connected memory is connected to a two-wire output port of the dedicated diagnostic data port. A first wire in the two-wire output port is a data wire and a second wire in said the wire output port is a clock wire. Transfer of the stored information from the serially connected memory to the two-wire output port is initiated by writing to a control register in the dedicated diagnostic data port. In response to writing to the control register, a clock signal on a clock input line to the dedicated diagnostic data port is coupled to the second wire, and is used to serially shift the stored information from the serially connected memory to the data wire. The signals on the two-wires from the integrated circuit are processed by a shift/latch control circuit that is external to the integrated circuit. A predetermined time after the clock signal on the clock wire terminates, i.e., remains inactive for a predetermined period, the shift/latch control circuit generates a latch signal that can be used to capture the data transmitted over the data wire.
摘要翻译：集成电路中的两线专用诊断数据端口为集成电路的所有内部功能提供可见性。将内部信号或信号写入专用诊断数据端口中的串行存储器。串行连接的存储器连接到专用诊断数据端口的两线输出端口。双线输出端口中的第一线是数据线，并且所述线输出端口中的第二线是时钟线。将存储的信息从串行连接的存储器传送到两线输出端口是通过写入专用诊断数据端口中的控制寄存器来启动的。响应于向控制寄存器的写入，到专用诊断数据端口的时钟输入线上的时钟信号被耦合到第二线，并且用于将存储的信息从串行连接的存储器顺序地移位到数据线。来自集成电路的两线上的信号由集成电路外部的移位/锁存控制电路处理。在时钟线上的时钟信号终止之后的预定时间，即在预定时间段内保持不活动，移位/锁存控制电路产生可用于捕获通过数据线发送的数据的锁存信号。

24. 发明申请

US20100142910A1 MODULAR OPTICAL FIBER CASSETTE 有权
标题翻译：模块化光纤箱体
公开(公告)号：US20100142910A1
公开(公告)日：2010-06-10
申请号：US12704982
申请日：2010-02-12
申请人： John P. Hill , Todd F. Husom , Walter E. Power, II
发明人： John P. Hill , Todd F. Husom , Walter E. Power, II
IPC分类号： G02B6/00
CPC分类号： G02B6/4454
摘要： The present disclosure includes apparatus and methods for a modular optical fiber cassette. One embodiment includes a base housing configured to receive additional nested components and an adapter plate resiliently connected to the housing and comprising a plurality of optical fiber connectors. The adapter plate is releasable from the housing and providing access to both sides of the adapter plate. The cassette further includes a radius limiter nested with and resiliently connected to the base housing, a first expansion housing having an exterior contour substantially aligned with the base housing and configured to resiliently interlock with the base housing, and a cover resiliently connected to the expansion housing.
摘要翻译：本公开包括用于模块化光纤盒的装置和方法。一个实施例包括被配置为接收附加嵌套部件的基座壳体和弹性地连接到壳体并且包括多个光纤连接器的适配器板。适配器板可从壳体释放并提供对适配器板两侧的通路。所述盒还包括嵌入并弹性地连接到所述底座外壳的半径限制器，第一膨胀壳体具有基本上与所述基座壳体对准的外部轮廓并被构造成与所述基座壳体弹性地互锁，以及弹性地连接到所述膨胀壳体。

25. 发明申请

US20090324189A1 MODULAR OPTICAL FIBER CASSETTE 有权
标题翻译：模块化光纤箱体
公开(公告)号：US20090324189A1
公开(公告)日：2009-12-31
申请号：US12552140
申请日：2009-09-01
申请人： John P. Hill , Todd F. Husom , Walter Ernest Power, II
发明人： John P. Hill , Todd F. Husom , Walter Ernest Power, II
IPC分类号： G02B6/00
CPC分类号： G02B6/46 , G02B6/4454
摘要： The present disclosure includes apparatus and methods for a modular optical fiber cassette. One embodiment includes a base housing configured to receive additional nested components and an adapter plate resiliently connected to the housing and comprising a plurality of optical fiber connectors. The adapter plate is releasable from the housing and providing access to both sides of the adapter plate. The cassette further includes a radius limiter nested with and resiliently connected to the base housing, a first expansion housing having an exterior contour substantially aligned with the base housing and configured to resiliently interlock with the base housing, and a cover resiliently connected to the expansion housing.
摘要翻译：本公开包括用于模块化光纤盒的装置和方法。一个实施例包括被配置为接收附加嵌套部件的基座壳体和弹性地连接到壳体并且包括多个光纤连接器的适配器板。适配器板可从壳体释放并提供对适配器板两侧的通路。所述盒还包括嵌入并弹性地连接到所述底座外壳的半径限制器，第一膨胀壳体具有基本上与所述基座壳体对准的外部轮廓并被构造成与所述基座壳体弹性地互锁，以及弹性地连接到所述膨胀壳体。

26. 发明授权

US06320711B2 High-speed unified data interface for a read channel in a disk drive system 失效
标题翻译：用于磁盘驱动器系统中读取通道的高速统一数据接口
公开(公告)号：US06320711B2
公开(公告)日：2001-11-20
申请号：US09072276
申请日：1998-05-04
申请人： John P. Hill
发明人： John P. Hill
IPC分类号： G11B509
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0676
摘要： The invention provides a high-speed interface that transfers user data and other data over a single unified interface between a read channel integrated circuit and another integrated circuit, such as the drive control integrated circuit. The high-speed interface eliminates the need for analog pins on the integrated circuits to lower the cost of the system. The high-speed interface also eliminates the use of the serial interface to transfer the servo position data and other data which speeds up the data transfer. Examples of the other data include read channel settings, read channel performance data, and servo data. A read channel integrated circuit exchanges the user data with a data bus when the disk drive system is reading or writing the user data. The read channel integrated circuit exchanges the other data with the data bus when the disk drive system is reading servo data. The other integrated circuit exchanges the user data with the data bus when the disk drive system is reading or writing the user data. The other integrated circuit exchanges the other data with the data bus when the disk drive system is reading the servo data. The data bus transfers the user data and the other data between the integrated circuits.
摘要翻译：本发明提供了一种高速接口，其通过读通道集成电路和另一集成电路（诸如驱动控制集成电路）之间的单个统一接口传送用户数据和其他数据。高速接口不需要集成电路上的模拟引脚来降低系统的成本。高速接口也消除了使用串行接口传送伺服位置数据和其他数据，从而加快了数据传输速度。其他数据的示例包括读通道设置，读通道性能数据和伺服数据。当磁盘驱动器系统读取或写入用户数据时，读通道集成电路与数据总线交换用户数据。当磁盘驱动器系统读取伺服数据时，读通道集成电路与数据总线交换其他数据。当磁盘驱动器系统读取或写入用户数据时，另一个集成电路与数据总线交换用户数据。当磁盘驱动器系统正在读取伺服数据时，另一个集成电路与数据总线交换其他数据。数据总线在集成电路之间传送用户数据和其他数据。

27. 发明授权

US06317009B2 Frequency shift key modulating oscillator 失效
标题翻译：频移键调制振荡器
公开(公告)号：US06317009B2
公开(公告)日：2001-11-13
申请号：US09836047
申请日：2001-04-16
申请人： John P. Hill
发明人： John P. Hill
IPC分类号： H03C300
CPC分类号： H03C3/16 , H03B5/1847 , H03B5/187 , H03B2201/017
摘要： The present invention teaches a system for selectably oscillating at a first or a second oscillating frequency. The system comprises an oscillator for providing an oscillating output. Moreover, the system comprises a switching device for selecting a first or a second impedance in response to a select signal having a voltage. Each of the first and second impedances are fixed independently of the select signal voltage such that the oscillating output oscillates at the first oscillating frequency when the first impedance is provided and oscillates at the second oscillating frequency when the second impedance is provided.
摘要翻译：本发明教导了一种用于以第一或第二振荡频率可选地振荡的系统。所述系统包括用于提供振荡输出的振荡器。此外，该系统包括用于响应于具有电压的选择信号选择第一或第二阻抗的开关装置。第一和第二阻抗中的每一个都是独立于选择信号电压固定的，使得当提供第一阻抗时，振荡输出以第一振荡频率振荡，并且当提供第二阻抗时以第二振荡频率振荡。

28. 发明授权

US5699021A Balanced and buffered oscillator and transmitter arrangement 失效
标题翻译：平衡和缓冲振荡器和发射机布置
公开(公告)号：US5699021A
公开(公告)日：1997-12-16
申请号：US633280
申请日：1996-04-16
申请人： John P. Hill
发明人： John P. Hill
IPC分类号： H03B5/30 , G08C17/02 , H03B5/32 , H03B5/36 , H04B1/04
CPC分类号： H03C3/42 , G08C17/02 , H03B5/326 , H03B5/36
摘要： A balanced and buffered oscillator and transmitter arrangement includes a first and second oscillator, each of which include a resonator for generating a reference signal, an amplifier for amplifying the reference signal, a resonant tank for generating an oscillating output signal in response to the amplified reference signal, and a buffer circuit for buffering the respective oscillating output signal such that the effects of a parasitic impedance are minimized.
摘要翻译：平衡和缓冲的振荡器和发射器装置包括第一和第二振荡器，每个振荡器包括用于产生参考信号的谐振器，用于放大参考信号的放大器，用于响应于放大参考产生振荡输出信号的谐振槽信号和用于缓冲各个振荡输出信号的缓冲电路，使得寄生阻抗的影响最小化。

29. 发明授权

US5563799A Low cost/low current watchdog circuit for microprocessor 失效
标题翻译：用于微处理器的低成本/低电流看门狗电路
公开(公告)号：US5563799A
公开(公告)日：1996-10-08
申请号：US337084
申请日：1994-11-10
申请人： Gerald M. Brehmer , John P. Hill
发明人： Gerald M. Brehmer , John P. Hill
IPC分类号： G06F11/00 , G06F11/30
CPC分类号： G06F11/0757
摘要： A watchdog circuit and method are provided for monitoring a microprocessor to detect the presence of a malfunction condition such as a program lock-up. The watchdog circuit includes a first capacitor coupled to a supply voltage and a transistor having a collector and emitter coupled in parallel with the first capacitor. The transistor has a base for receiving a signal in response to a status output signal generated by the microprocessor. A voltage threshold detector is provided for comparing a voltage potential associated with the capacitor with a predetermined threshold voltage and producing a reset signal in response thereto. The threshold voltage detector produces a small current which is utilized to charge the first capacitor. The reset signal is provided to the microprocessor to initiate a reset operation which will reset the microprocessor in an attempt to eliminate the malfunction condition. Additionally, a feedback path may be provided between the output and the base of the transistor to allow for repetitive reset signals during a continuous microprocessor malfunction condition.
摘要翻译：提供了一种看门狗电路和方法，用于监视微处理器以检测诸如程序锁定的故障状况的存在。看门狗电路包括耦合到电源电压的第一电容器和具有与第一电容器并联耦合的集电极和发射极的晶体管。晶体管具有响应于由微处理器产生的状态输出信号而接收信号的基极。提供电压阈值检测器，用于将与电容器相关联的电压电势与预定阈值电压进行比较，并响应于此产生复位信号。阈值电压检测器产生用于对第一电容器充电的小电流。复位信号被提供给微处理器以启动复位操作，这将复位微处理器以试图消除故障状况。此外，可以在晶体管的输出和基极之间提供反馈路径，以允许在连续微处理器故障状态期间的重复复位信号。

30. 发明授权

US4539608A Low offset position demodular 失效
标题翻译：低偏移位置解调
公开(公告)号：US4539608A
公开(公告)日：1985-09-03
申请号：US447823
申请日：1982-12-08
申请人： John P. Hill , James J. Touchton
发明人： John P. Hill , James J. Touchton
IPC分类号： G11B5/596 , H03D1/22 , H03D1/06 , G11B21/10
CPC分类号： G11B5/59627 , H03D1/229
摘要： A low offset position demodulator that may be used in the positioning servo of a disk drive or similar device. A first stage of the demodulator circuit multiplies or switches a servo carrier signal, modulated with position information, with a synchronized gate signal. This first stage of the demodulator circuit includes a differential output and means for controlling the common mode operating point thereof with an external control voltage. A low pass filter, also having a differential output, is coupled to the differential output of the first stage of the demodulator. A differential-to-single-ended conversion stage is tied to the low pass filter output to provide a single position output signal. Also coupled to the low pass filter differential output is an averaging network that averages the signal appearing on one of the two differential signal lines with the signal appearing on the other differential signal line. The resulting averaged signal is compared to a zero voltage reference signal and the difference between these two signals is then used to derive the control voltage applied to the first stage of the modulator. Hence, the common mode operating point of the balanced demodulator is forced to assume and maintain a zero volt level.
摘要翻译：可用于磁盘驱动器或类似设备的定位伺服中的低偏移位置解调器。解调器电路的第一级用同步的门信号乘以或切换用位置信息调制的伺服载波信号。解调器电路的第一级包括差分输出和用于利用外部控制电压来控制其共模工作点的装置。也具有差分输出的低通滤波器耦合到解调器的第一级的差分输出。差分到单端转换级与低通滤波器输出相连以提供单个位置输出信号。还耦合到低通滤波器差分输出的是平均网络，其平均化出现在两个差分信号线之一上的信号，信号出现在另一个差分信号线上。将所得到的平均信号与零电压参考信号进行比较，然后使用这两个信号之间的差异来推导施加到调制器的第一级的控制电压。因此，平衡解调器的共模工作点被强制为维持零伏电平。

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