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21. 发明授权

US08036053B2 Semiconductor memory device capable of suppressing a coupling effect of a test-disable transmission line 有权
标题翻译：能够抑制测试禁止传输线的耦合效应的半导体存储器件
公开(公告)号：US08036053B2
公开(公告)日：2011-10-11
申请号：US12134865
申请日：2008-06-06
申请人： Jeong-Yoon Ahn , Ji-Eun Jang , Young-Jun Ku
发明人： Jeong-Yoon Ahn , Ji-Eun Jang , Young-Jun Ku
IPC分类号： G11C29/00
CPC分类号： G11C29/46 , G11C29/02 , G11C29/025 , G11C29/1201 , G11C2029/1206
摘要： Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.
摘要翻译：半导体器件和半导体存储器件包括多个内部电路，其被配置为响应于它们各自的测试模式信号执行测试操作;以及多个测试模式控制单元，被配置为响应于所述内部电路被禁用而控制内部电路的测试操作一个测试信号。

22. 发明申请

US20110109348A1 DYNAMIC COMPARATOR WITH BACKGROUND OFFSET CALIBRATION 有权
标题翻译：具有背景偏移校准的动态比较器
公开(公告)号：US20110109348A1
公开(公告)日：2011-05-12
申请号：US12640016
申请日：2009-12-17
申请人： Bo-Wei Chen , Tim-Kuei Shia , Ji-Eun Jang
发明人： Bo-Wei Chen , Tim-Kuei Shia , Ji-Eun Jang
IPC分类号： H03K5/22
CPC分类号： H03K5/2481
摘要： A dynamic comparator with background offset calibration is provided. The dynamic comparator includes at least one input differential pair, a first back-to-back inverter, a second back-to-back inverter, and an integrator. The input differential pair includes two current branches, wherein one of the current branches has an input referred offset. The first back-to-back inverter determines which one of the two current branches has the input referred offset in response to a first clock signal and generates two control signals accordingly. The integrator generates two calibration voltages for the input differential pair in response to the two control signals, so as to calibrate the input referred offset. The second back-to-back inverter determines a difference between two input signals received by the input differential pair after the input referred offset is calibrated in response to a second clock signal and outputs two comparison signals accordingly.
摘要翻译：提供了具有背景偏移校准的动态比较器。动态比较器包括至少一个输入差分对，第一背对背反相器，第二背对背反相器和积分器。输入差分对包括两个电流分支，其中当前分支中的一个具有输入参考偏移。第一背对背反相器确定两个电流分支中的哪一个响应于第一时钟信号而具有参考的输入偏移，并相应地产生两个控制信号。积分器响应于两个控制信号为输入差分对产生两个校准电压，以校准输入参考偏移。第二背对背逆变器确定在响应于第二时钟信号校准输入参考偏移之后由输入差分对接收的两个输入信号之间的差异，并相应地输出两个比较信号。

23. 发明授权

US07818526B2 Semiconductor memory device having test mode for data access time 有权
标题翻译：半导体存储器件具有用于数据存取时间的测试模式
公开(公告)号：US07818526B2
公开(公告)日：2010-10-19
申请号：US11022828
申请日：2004-12-28
申请人： Ji-Eun Jang , Kee-Teok Park
发明人： Ji-Eun Jang , Kee-Teok Park
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C29/022 , G11C29/028 , G11C29/50012
摘要： A semiconductor memory device for measuring a data access time by controlling data output operation, including: a pipe latch control unit for generating an input control signal based on a test mode signal; a pipe latch unit for receiving data and controlling the data according to a CAS latency in synchronization with a clock signal at a normal mode or passing the data without synchronization with the clock signal at a test mode based on the input control signal; an output control unit for generating an output node control signal based on the test mode signal; and an output unit for controlling an output data outputted from the pipe latch means according to the CAS latency in synchronization with the clock signal at the normal mode or passing the output data without synchronization with the clock signal at the test mode based on the output node control signal.
摘要翻译：一种用于通过控制数据输出操作来测量数据访问时间的半导体存储器件，包括：管锁存器控制单元，用于基于测试模式信号产生输入控制信号; 管道锁存单元，用于基于所述输入控制信号，在测试模式下，与正常模式下的时钟信号同步地接收数据并根据CAS延迟来控制所述数据，或者与所述时钟信号同步地传送所述数据; 输出控制单元，用于基于测试模式信号产生输出节点控制信号; 以及输出单元，用于基于所述输出节点，在与所述正常模式下的所述时钟信号同步地控制从所述管锁存装置输出的输出数据，或者使所述输出数据与所述测试模式下的所述时钟信号同步，控制信号。

24. 发明授权

US07706196B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07706196B2
公开(公告)日：2010-04-27
申请号：US12003680
申请日：2007-12-31
申请人： Kyung-Whan Kim , Ji-Eun Jang
发明人： Kyung-Whan Kim , Ji-Eun Jang
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1045 , G11C11/4076 , G11C11/408 , G11C2207/2254
摘要： A semiconductor memory device is provided to improve the tAA characteristics. The semiconductor memory device includes: a discrimination signal generating unit for generating a first discrimination signal denoting a write operation of the semiconductor memory device; a selective delay unit for delaying a command-group signal in response to a second discrimination signal; and a fuse unit for generating the second discrimination signal based on the first discrimination signal, the second discrimination signal determining whether the selective delay unit selectively delays the command-group signal in response to the first discrimination signal.
摘要翻译：提供半导体存储器件以改善tAA特性。半导体存储器件包括：识别信号产生单元，用于产生表示半导体存储器件的写入操作的第一鉴别信号; 选择延迟单元，用于响应于第二鉴别信号延迟命令组信号; 以及熔丝单元，用于基于所述第一判别信号产生所述第二判别信号，所述第二判别信号确定所述选择延迟单元是否响应于所述第一判别信号有选择地延迟所述命令组信号。

25. 发明授权

US07576596B2 Internal voltage generator of semiconductor device 有权
标题翻译：半导体器件的内部电压发生器
公开(公告)号：US07576596B2
公开(公告)日：2009-08-18
申请号：US11714194
申请日：2007-03-06
申请人： Kang-Seol Lee , Ji-Eun Jang
发明人： Kang-Seol Lee , Ji-Eun Jang
IPC分类号： G05F1/10
CPC分类号： G05F1/465
摘要： Embodiments of the present invention are directed to provide an internal voltage generator of a semiconductor memory device for generating a predetermined stable level of an internal voltage. The semiconductor memory device includes a control signal generator, an internal voltage generator and an internal voltage compensator. The control signal generator generates a reference signal and a compensating signal which are corresponding to voltage level of the reference signal. The internal voltage generator generates an internal voltage in response to the reference signal. The internal voltage compensator compensates the internal voltage in response to the compensating signal.
摘要翻译：本发明的实施例旨在提供一种用于产生内部电压的预定稳定电平的半导体存储器件的内部电压发生器。半导体存储器件包括控制信号发生器，内部电压发生器和内部电压补偿器。控制信号发生器产生对应于参考信号的电压电平的参考信号和补偿信号。内部电压发生器响应于参考信号产生内部电压。内部电压补偿器根据补偿信号补偿内部电压。

26. 发明申请

US20090013225A1 TEST MODE CONTROL CIRCUIT 失效
标题翻译：测试模式控制电路
公开(公告)号：US20090013225A1
公开(公告)日：2009-01-08
申请号：US12209966
申请日：2008-09-12
申请人： Ji-Eun Jang , Kee-Teok Park
发明人： Ji-Eun Jang , Kee-Teok Park
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31701
摘要： Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test mode control signal to output a latch control signal. A test mode control unit detects a test mode entry and a test mode exit to selectively activate one of a test mode set signal and a test mode exit signal, and outputs the test mode control signal having different voltage levels according to an activation state of the test mode set signal or the test mode exit signal. An address latch latches an input address when the MRS signal is activated, and outputs the latched input address as the MRS address when the latch control signal is activated.
摘要翻译：提供了一种测试模式控制电路，其能够在测试模式进入之后防止在测试模式退出中的MRS（模式寄存器组）改变。在测试模式控制电路中，MRS控制器逻辑地组合MRS信号，存储体地址，MRS地址和测试模式控制信号以输出锁存控制信号。测试模式控制单元检测测试模式条目和测试模式退出以选择性地激活测试模式设置信号和测试模式退出信号之一，并且根据所述测试模式输入和测试模式退出信号的激活状态输出具有不同电压电平的测试模式控制信号测试模式设置信号或测试模式退出信号。当激活MRS信号时，地址锁存器锁存输入地址，并且当锁存控制信号被激活时，输出锁存的输入地址作为MRS地址。

27. 发明授权

US07449965B2 Self refresh oscillator and oscillation signal generation method of the same 失效
标题翻译：自刷振荡器和振荡信号产生方法相同
公开(公告)号：US07449965B2
公开(公告)日：2008-11-11
申请号：US11319718
申请日：2005-12-29
申请人： Ji-Eun Jang
发明人： Ji-Eun Jang
IPC分类号： H03L1/00 , G11C5/00
CPC分类号： G11C11/406 , G11C2211/4065
摘要： A self refresh period signal generator includes: a voltage detection unit for detecting a voltage level of a power supply voltage in order to generate a plurality of period control signals according to the detected voltage level; and an oscillation unit for generating a ring oscillation signal having a constant period determined by a resistance of a period control resistor when a self refresh signal is activated, wherein the resistance of the period control resistor is controlled according to logic levels of the plurality of period control signals.
摘要翻译：自刷新周期信号发生器包括：电压检测单元，用于检测电源电压的电压电平，以便根据检测的电压电平产生多个周期控制信号; 以及振荡单元，用于当自刷新信号被激活时产生具有由周期控制电阻器的电阻确定的恒定周期的环形振荡信号，其中周期控制电阻器的电阻根据多个周期的逻辑电平进行控制控制信号。

28. 发明授权

US07434120B2 Test mode control circuit 失效
标题翻译：测试模式控制电路
公开(公告)号：US07434120B2
公开(公告)日：2008-10-07
申请号：US11323382
申请日：2005-12-29
申请人： Ji-Eun Jang , Kee-Teok Park
发明人： Ji-Eun Jang , Kee-Teok Park
IPC分类号： G11C29/00
CPC分类号： G01R31/31701
摘要： Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test mode control signal to output a latch control signal. A test mode control unit detects a test mode entry and a test mode exit to selectively activate one of a test mode set signal and a test mode exit signal, and outputs the test mode control signal having different voltage levels according to an activation state of the test mode set signal or the test mode exit signal. An address latch latches an input address when the MRS signal is activated, and outputs the latched input address as the MRS address when the latch control signal is activated.
摘要翻译：提供了一种测试模式控制电路，其能够在测试模式进入之后防止在测试模式退出中的MRS（模式寄存器组）改变。在测试模式控制电路中，MRS控制器逻辑地组合MRS信号，存储体地址，MRS地址和测试模式控制信号以输出锁存控制信号。测试模式控制单元检测测试模式输入和测试模式退出以选择性地激活测试模式设置信号和测试模式退出信号之一，并且根据所述测试模式输入和测试模式退出信号的激活状态输出具有不同电压电平的测试模式控制信号测试模式设置信号或测试模式退出信号。当激活MRS信号时，地址锁存器锁存输入地址，并且当锁存控制信号被激活时，输出锁存的输入地址作为MRS地址。

29. 发明申请

US20080159045A1 Semiconductor memory device capable of controlling drivability of overdriver 失效
公开(公告)号：US20080159045A1
公开(公告)日：2008-07-03
申请号：US12073738
申请日：2008-03-10
申请人： Ji-Eun Jang
发明人： Ji-Eun Jang
IPC分类号： G11C5/14
CPC分类号： G11C29/14 , G11C7/08 , G11C2207/065
摘要： A semiconductor memory device capable of controlling a drivability of an overdriver is provided. The semiconductor memory device includes: a first power supply for supplying a normal driving voltage; a memory cell array block; a bit line sense amplifier block for sensing and amplifying voltage difference between bit line pair of the memory cell array block; a first driver for driving a power supply line of the bit line sense amplifier block to a voltage of a node connected with the first power supply in response to a driving control signal; a plurality of second drivers for driving the node to an overdriving voltage higher than the normal driving voltage; and an overdriving drivability controller for selectively activating the second drivers in response to a test-mode drivability control signal inputted during an activation period of an overdriving signal.

30. 发明申请

US20080136767A1 DISPLAY APPARATUS 有权
标题翻译：显示设备
公开(公告)号：US20080136767A1
公开(公告)日：2008-06-12
申请号：US11855194
申请日：2007-09-14
申请人： Sang-youn Kim , Cheal-gi Kim , Min-sung Choi , Seung-ho Baek , Hyoung-wook Kim , Byoung-haw Park , Ji-eun Jang
发明人： Sang-youn Kim , Cheal-gi Kim , Min-sung Choi , Seung-ho Baek , Hyoung-wook Kim , Byoung-haw Park , Ji-eun Jang
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G2320/0271 , G09G2320/041 , G09G2340/16
摘要： A display apparatus and a driving method thereof, in which the display apparatus includes a temperature sensor detecting a temperature, a first memory, a timing controller that receives an (n−1)th image signal and an nth image signal of consecutive frames, corrects the nth image signal and outputs the nth image signal, wherein the timing controller generates a clock signal whose phase varies according to the detected temperature, writes the nth image signal in the first memory in synchronization with the clock signal, reads the (n−1)th image signal from the first memory, and compares the nth image signal and the (n−1)th image signal with each other to then correct the nth image signal based on the comparison result, a data driver that provides an image-data voltage corresponding to the corrected signal of the nth image signal, and a liquid crystal panel that displays an image corresponding to the image-data voltage.
摘要翻译：一种显示装置及其驱动方法，其中显示装置包括检测温度的温度传感器，第一存储器，接收第（n-1）个图像信号和连续帧的第n个图像信号的定时控制器，校正第n个图像信号并输出第n个图像信号，其中定时控制器产生相位根据检测到的温度而变化的时钟信号，与时钟信号同步地将第n个图像信号写入第一个存储器中，读取第n个图像信号）图像信号，并且将第n图像信号和第（n-1）个图像信号彼此比较，然后基于比较结果校正第n个图像信号，提供图像数据的数据驱动器与第n图像信号的校正信号相对应的电压，以及显示与图像数据电压对应的图像的液晶面板。

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