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21. 发明授权

US08095831B2 Programmable error actions for a cache in a data processing system 有权
标题翻译：数据处理系统中缓存的可编程错误操作
公开(公告)号：US08095831B2
公开(公告)日：2012-01-10
申请号：US12273155
申请日：2008-11-18
申请人： William C. Moyer , Gary L. Whisenhunt
发明人： William C. Moyer , Gary L. Whisenhunt
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/073 , G06F12/0802
摘要： A data processing system and method of operation has a processor coupled to a cache. Cache control circuitry is coupled to the cache and performs error detection. A user programmable error action control register stores a control value for selecting a type of error action to be taken when a cache error is detected. A first value of the control value permits handling of a cache error that is transparent to the processor, and a second value permits handling of the cache error by taking an exception that is visible to the processor. Various alternate actions to a detected error, including error correction or cache line invalidation, may be taken in response to other values of the control value.
摘要翻译：数据处理系统和操作方法具有耦合到高速缓存的处理器。缓存控制电路耦合到高速缓存并执行错误检测。用户可编程错误动作控制寄存器存储用于选择检测到高速缓存错误时要采取的错误动作的类型的控制值。控制值的第一个值允许处理对处理器透明的高速缓存错误，第二个值允许通过处理器可见的异常来处理高速缓存错误。响应于控制值的其他值，可以采取针对检测到的错误的各种替代动作，包括纠错或高速缓存线无效。

22. 发明申请

US20100107243A1 PERMISSIONS CHECKING FOR DATA PROCESSING INSTRUCTIONS 有权
标题翻译：许可证检查数据处理指令
公开(公告)号：US20100107243A1
公开(公告)日：2010-04-29
申请号：US12259369
申请日：2008-10-28
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F21/00
CPC分类号： G06F12/1416
摘要： A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. The transactions include an indication of an instruction operation, an address associated with the instruction operation, a decoration value (i.e. a command to the target device to perform a function in addition to a primary function of the executed instruction), and access permissions associated with the address. The target device (e.g. a memory with functionality in addition to storage functionality) determines whether a decoration operation specified by the decoration value is permissible based on the received access permissions. The target device performs the decoration operation if appropriate permissions exist.
摘要翻译：具有处理器和目标设备的数据处理系统处理装饰指令（即具有装饰值的指令）。诸如处理器之类的数据处理系统的设备通过系统互连将事务发送到目标设备。交易包括指令操作的指示，与指令操作相关联的地址，装饰值（即除了执行的指令的主要功能之外的对目标设备执行功能的命令）以及与地址。目标设备（例如具有除了存储功能之外的功能的存储器）基于所接收的访问许可来确定装饰值指定的装饰操作是否被允许。如果存在适当的权限，则目标设备执行装饰操作。

23. 发明授权

US07702881B2 Method and system for data transfers across different address spaces 有权
标题翻译：跨不同地址空间进行数据传输的方法和系统
公开(公告)号：US07702881B2
公开(公告)日：2010-04-20
申请号：US11669804
申请日：2007-01-31
申请人： Becky G. Bruce , Michael D. Snyder , Gary L. Whisenhunt , Kumar Gala
发明人： Becky G. Bruce , Michael D. Snyder , Gary L. Whisenhunt , Kumar Gala
IPC分类号： G06F12/00
CPC分类号： G06F12/0284
摘要： A processing device includes a first storage location configured to store a first value associated with a first address space, a second storage location configured to store a second value associated with a second address space, and a third storage location configured to store a third value associated with a third address space. The processing device further includes a memory management unit, which includes a first input configured to receive a first address value associated with a data transfer operation, a second input configured to receive an identifier associated with the data transfer operation, and an address space select module configured to identify a select value from the first value, the second value and the third value based on the identifier. The memory management module further includes an address modification module configured to generate a second address value based on the first address value and the select value.
摘要翻译：处理设备包括被配置为存储与第一地址空间相关联的第一值的第一存储位置，被配置为存储与第二地址空间相关联的第二值的第二存储位置以及被配置为存储与第二地址空间相关联的第三值的第三存储位置具有第三个地址空间。处理装置还包括存储器管理单元，其包括被配置为接收与数据传送操作相关联的第一地址值的第一输入，被配置为接收与数据传送操作相关联的标识符的第二输入以及地址空间选择模块被配置为基于所述标识符从所述第一值，所述第二值和所述第三值中识别选择值。存储器管理模块还包括地址修改模块，该地址修改模块被配置为基于第一地址值和选择值生成第二地址值。

24. 发明申请

US20100095039A1 INTERRUPT ACKNOWLEDGMENT IN A DATA PROCESSING SYSTEM 有权
标题翻译：数据处理系统中的中断确认
公开(公告)号：US20100095039A1
公开(公告)日：2010-04-15
申请号：US12250682
申请日：2008-10-14
申请人： Bryan D. Marietta , Michael D. Snyder , Gary L. Whisenhunt , Daniel L. Bouvier
发明人： Bryan D. Marietta , Michael D. Snyder , Gary L. Whisenhunt , Daniel L. Bouvier
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.
摘要翻译：数据处理系统具有中断控制器，其向处理器提供中断请求以及对应的中断标识符和相应的中断向量。如果处理器接受中断，处理器将通过中断标识符和中断确认返回相同的中断标识符值给中断控制器。还可以提供中断/未采取的指示符。用于协调中断控制器和处理器之间的中断处理的通信接口可能是异步的。

25. 发明申请

US20090235059A1 QUALIFICATION OF CONDITIONAL DEBUG INSTRUCTIONS BASED ON ADDRESS 有权
标题翻译：基于地址的条件调试指令的资格
公开(公告)号：US20090235059A1
公开(公告)日：2009-09-17
申请号：US12049984
申请日：2008-03-17
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F9/30
CPC分类号： G06F9/30076 , G06F9/30189
摘要： A processor implementation supports selection of an execution mode for debug instruction instances based on respective addresses thereof in addressable memory can provide an attractive mechanism for executing debug instructions in a way that allows some instances of the instructions to operate with debug semantics while suppressing other instances by executing them with no-operation (NOP) semantics. In some embodiments, selection of operative execution semantics may be based on attributes of a memory page in which a particular debug instruction instance resides. In some embodiments, portions of an address space may be delimited (e.g., using values stored in bounding registers and addresses of particular debug instruction instances compared against the delimited portions to select appropriate execution semantics. In some embodiments, both types of evaluations may be used in selecting appropriate execution semantics for a particular debug instruction instance.
摘要翻译：处理器实现支持基于其可寻址存储器中的相应地址来选择用于调试指令实例的执行模式可以提供用于以允许指令的某些实例以调试语义来操作的方式来执行调试指令的有吸引力的机制，同时通过执行它们与无操作（NOP）语义。在一些实施例中，可操作执行语义的选择可以基于特定调试指令实例驻留在其中的存储器页的属性。在一些实施例中，可以对地址空间的部分进行限定（例如，使用存储在边界寄存器中的值和特定调试指令实例的地址与定界部分进行比较以选择适当的执行语义在一些实施例中，可以使用两种类型的评估在为特定调试指令实例选择适当的执行语义。

26. 发明申请

US20090100432A1 FORWARD PROGRESS MECHANISM FOR A MULTITHREADED PROCESSOR 有权
标题翻译：多元化加工商的前进进展机制
公开(公告)号：US20090100432A1
公开(公告)日：2009-04-16
申请号：US11871626
申请日：2007-10-12
申请人： David C. Holloway , Trinh H. Nguyen , Michael D. Snyder , Gary L. Whisenhunt
发明人： David C. Holloway , Trinh H. Nguyen , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： A processing device includes a storage component configured to store instructions associated with a corresponding thread of a plurality of threads, and an execution unit configured to fetch and execute instructions. The processing device further includes a period timer comprising an output to provide an indicator in response to a count value of the period timer reaching a predetermined value based on a clock signal. The processing device additionally includes a plurality of thread forward-progress counter components, each configured to adjust a corresponding execution counter value based on an occurrence of a forward-progress indicator while instructions of a corresponding thread are being executed. The processing device further includes a thread select module configured to select threads of the plurality of threads for execution by the execution unit based a state of the period timer and a state of each of the plurality of thread forward-progress counter components.
摘要翻译：处理装置包括：存储部件，被配置为存储与多个线程的相应线程相关联的指令;以及执行单元，被配置为获取并执行指令。处理装置还包括周期定时器，其包括输出，以响应于周期定时器基于时钟信号达到预定值的计数值来提供指示符。处理装置还包括多个线程正向进行计数器组件，每个组件被配置成在正在执行对应的线程的指令的同时基于前进进度指示符的发生来调整相应的执行计数器值。所述处理装置还包括线程选择模块，所述线程选择模块被配置为基于所述周期定时器的状态和所述多个线程前进进程计数器组件中的每一个的状态来选择所述多个线程的线程以由所述执行单元执行。

27. 发明申请

US20090100254A1 DEBUG INSTRUCTION FOR USE IN A DATA PROCESSING SYSTEM 有权
标题翻译：用于数据处理系统的调试指令
公开(公告)号：US20090100254A1
公开(公告)日：2009-04-16
申请号：US11871847
申请日：2007-10-12
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F9/44
CPC分类号： G06F11/3656 , G06F9/3005 , G06F9/30072 , G06F9/30181
摘要： A method includes providing a debug instruction and providing a debug control register field, where if the debug control register field has a first value, the debug instruction executes a debug operation and where if the debug control register field has a second value, the debug instruction is to be executed as a no-operation (NOP) instruction. A data processing system includes instruction fetch circuitry for receiving a debug instruction, a debug control register field, and debug execution control circuitry for controlling execution of the debug instruction in a first manner if the debug control register field has a first value and in a second manner if the debug control register field has a second value, where in the first manner a debug operation is performed and in the second manner no debug operation is performed.
摘要翻译：一种方法包括提供调试指令并提供调试控制寄存器字段，其中如果调试控制寄存器字段具有第一值，则调试指令执行调试操作，并且如果调试控制寄存器字段具有第二值，则调试指令将作为无操作（NOP）指令执行。数据处理系统包括用于接收调试指令的指令提取电路，调试控制寄存器字段和调试执行控制电路，用于如果调试控制寄存器字段具有第一值，则以第一方式控制调试指令的执行如果调试控制寄存器字段具有第二值，则以第一种方式执行调试操作，并且在第二方式中不执行调试操作。

28. 发明申请

US20090037666A1 CACHE LOCKING DEVICE AND METHODS THEREOF 有权
标题翻译：缓存设备及其方法
公开(公告)号：US20090037666A1
公开(公告)日：2009-02-05
申请号：US11832797
申请日：2007-08-02
申请人： Syed R. Rahman , David F. Greenberg , Kathryn C. Stacer , Klas M. Bruce , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
发明人： Syed R. Rahman , David F. Greenberg , Kathryn C. Stacer , Klas M. Bruce , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/0846 , G06F12/0891
摘要： A method and device for locking a cache line of a cache is disclosed. The method includes automatically changing a state of a cache line from a valid locked state to an invalid locked state in response to receiving an indication that a memory location external to the cache and corresponding to the cache line is associated with an access request by a processor or other data access module. Thus, the locked state of a cache line is maintained even after data in the locked cache line is invalidated. By maintaining the invalid locked state, the cache line is not available for reallocation by the cache. This allows locked cache lines that become invalidated to remain locked without additional software overhead to periodically determine whether the lock has been lost due to invalidation of the cache line.
摘要翻译：公开了一种用于锁定高速缓存的高速缓存行的方法和设备。该方法包括响应于接收到高速缓存行外部的对应于高速缓存行的存储器位置与处理器的访问请求相关联的指示，自动将高速缓存行的状态从有效锁定状态改变为无效锁定状态或其他数据访问模块。因此，即使在锁定的高速缓存行中的数据无效之后，也保持高速缓存行的锁定状态。通过保持无效的锁定状态，高速缓存行不可用于高速缓存的重新分配。这允许被锁定的高速缓存行保持锁定，而不需要额外的软件开销来定期确定锁是否由于高速缓存行的无效而丢失。

29. 发明申请

US20080282251A1 THREAD DE-EMPHASIS INSTRUCTION FOR MULTITHREADED PROCESSOR 有权
标题翻译：螺纹加工器的螺纹切割指令
公开(公告)号：US20080282251A1
公开(公告)日：2008-11-13
申请号：US11746998
申请日：2007-05-10
申请人： Klas M. Bruce , Sergio Schuler , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
发明人： Klas M. Bruce , Sergio Schuler , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F9/46 , G06F9/50
CPC分类号： G06F9/485 , G06F9/3009 , G06F9/3013 , G06F9/3824 , G06F9/3834 , G06F9/3851
摘要： A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.
摘要翻译：公开了一种用于在处理器处调度线程执行的技术。该技术包括执行线程的线程去加重指令，该线程去加强线程，直到与线程相关联的等待存储器事务（例如高速缓存未命中）的数量处于或低于阈值。当该线程被去加强时，处理器中具有较高优先级的其他线程可以执行或分配系统资源。因此，处理器中失速的可能性降低。

30. 发明授权

US06792502B1 Microprocessor having a content addressable memory (CAM) device as a functional unit therein and method of operation 有权
标题翻译：具有内容可寻址存储器（CAM）装置作为功能单元的微处理器及其操作方法
公开(公告)号：US06792502B1
公开(公告)日：2004-09-14
申请号：US09689028
申请日：2000-10-12
申请人： Mihir A. Pandya , Gary L. Whisenhunt
发明人： Mihir A. Pandya , Gary L. Whisenhunt
IPC分类号： G06F1200
CPC分类号： G06F9/3885 , G11C15/00
摘要： A microprocessor architecture (310) has a plurality of functional units arranged in a parallel manner between one or more source buses (412 and/or 414) and one or more result buses (490). At least one of the functional units within the architecture is a content addressable memory (CAM) functional unit (430) which can be issued CPU instructions via a sequencer (480) much like any other functional unit. The operation of the CAM (430) may be pipelined in one or more stages so that the CAM's throughput may be increased to accommodate the higher clock rates that are likely used within the architecture (310). One embodiment involves pipelining the CAM operation in three stages (510, 520, and 530) in order to sequentially perform data input and precharge operations, followed by match operations, and followed Finally by priority encoding and data output.
摘要翻译：微处理器架构（310）具有在一个或多个源总线（412和/或414）与一个或多个结果总线（490）之间并行布置的多个功能单元。架构内的功能单元中的至少一个是内容可寻址存储器（CAM）功能单元（430），其可以与任何其他功能单元类似地经由定序器（480）发出CPU指令。 CAM（430）的操作可以在一个或多个阶段中流水线化，使得可以增加CAM的吞吐量以适应架构（310）中可能使用的较高时钟速率。一个实施例涉及以三个阶段（510,520和530）流水线CAM操作，以便顺序执行数据输入和预充电操作，随后进行匹配操作，随后最后通过优先编码和数据输出。

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