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1. 发明授权

US09395983B2 Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operation 有权
标题翻译：调试指令由第一个线程执行以在第二个线程中生成调试事件以导致暂停操作
公开(公告)号：US09395983B2
公开(公告)日：2016-07-19
申请号：US12195220
申请日：2008-08-20
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30 , G06F11/36
CPC分类号： G06F9/3005 , G06F9/3009 , G06F11/3648
摘要： For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug related instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread, wherein processing the debug event comprises causing a halting operation related to the processor.
摘要翻译：为了在包括处理器的数据处理系统中使用，该处理器被配置为执行对应于第一线程的第一组指令和对应于第二线程的第二组指令，提供了一种方法。该方法包括响应于在执行第一组指令时由第一线程执行与调试相关的指令，生成用于由第二线程处理的调试事件，其中处理调试事件包括引起与处理器相关的暂停操作。

2. 发明申请

US20100125750A1 PROGRAMMABLE ERROR ACTIONS FOR A CACHE IN A DATA PROCESSING SYSTEM 有权
标题翻译：数据处理系统中缓存的可编程错误操作
公开(公告)号：US20100125750A1
公开(公告)日：2010-05-20
申请号：US12273155
申请日：2008-11-18
申请人： William C. Moyer , Gary L. Whisenhunt
发明人： William C. Moyer , Gary L. Whisenhunt
IPC分类号： G06F11/20
CPC分类号： G06F11/0793 , G06F11/073 , G06F12/0802
摘要： A data processing system and method of operation has a processor coupled to a cache. Cache control circuitry is coupled to the cache and performs error detection. A user programmable error action control register stores a control value for selecting a type of error action to be taken when a cache error is detected. A first value of the control value permits handling of a cache error that is transparent to the processor, and a second value permits handling of the cache error by taking an exception that is visible to the processor. Various alternate actions to a detected error, including error correction or cache line invalidation, may be taken in response to other values of the control value.
摘要翻译：数据处理系统和操作方法具有耦合到高速缓存的处理器。缓存控制电路耦合到高速缓存并执行错误检测。用户可编程错误动作控制寄存器存储用于选择检测到高速缓存错误时要采取的错误动作的类型的控制值。控制值的第一个值允许处理对处理器透明的高速缓存错误，第二个值允许通过处理器可见的异常来处理高速缓存错误。响应于控制值的其他值，可以采取针对检测到的错误的各种替代动作，包括纠错或高速缓存线无效。

3. 发明授权

US07584344B2 Instruction for conditionally yielding to a ready thread based on priority criteria 有权
标题翻译：根据优先级标准有条件地屈服于准备好的线程的指令
公开(公告)号：US07584344B2
公开(公告)日：2009-09-01
申请号：US11381284
申请日：2006-05-02
申请人： William C. Moyer , Gary L. Whisenhunt
发明人： William C. Moyer , Gary L. Whisenhunt
IPC分类号： G06F9/40
CPC分类号： G06F9/4843 , G06F2209/507
摘要： An integrated circuit (10) has a conditional yield instruction (305) which may be used to conditionally yield execution of a currently active thread based on priority and status of other threads. In one embodiment, an I bit 304 may be used to designate whether the priority selection bits (50) are stored in the instruction itself. If the priority selection bits (50) are not stored in the instruction itself, a portion of the instruction (302) may be used to store a location indicator which indicates where the priority selection bits (50) are located (e.g. register file 22).
摘要翻译：集成电路（10）具有条件收益率指令（305），其可以用于基于其他线程的优先级和状态有条件地产生当前活动线程的执行。在一个实施例中，可以使用I比特304来指示优先权选择比特（50）是否被存储在指令本身中。如果优先级选择位（50）未被存储在指令本身中，则指令（302）的一部分可以用于存储指示优先级选择位（50）所在位置的位置指示符（例如寄存器文件22）。

4. 发明授权

US08627471B2 Permissions checking for data processing instructions 有权
标题翻译：权限检查数据处理说明
公开(公告)号：US08627471B2
公开(公告)日：2014-01-07
申请号：US12259369
申请日：2008-10-28
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F11/00
CPC分类号： G06F12/1416
摘要： A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. The transactions include an indication of an instruction operation, an address associated with the instruction operation, a decoration value (i.e. a command to the target device to perform a function in addition to a primary function of the executed instruction), and access permissions associated with the address. The target device (e.g. a memory with functionality in addition to storage functionality) determines whether a decoration operation specified by the decoration value is permissible based on the received access permissions. The target device performs the decoration operation if appropriate permissions exist.
摘要翻译：具有处理器和目标设备的数据处理系统处理装饰指令（即具有装饰值的指令）。诸如处理器之类的数据处理系统的设备通过系统互连将事务发送到目标设备。交易包括指令操作的指示，与指令操作相关联的地址，装饰值（即除了执行的指令的主要功能之外的对目标设备执行功能的命令）以及与地址。目标设备（例如具有除了存储功能之外的功能的存储器）基于所接收的访问许可来确定装饰值指定的装饰操作是否被允许。如果存在适当的权限，则目标设备执行装饰操作。

5. 发明申请

US20100049956A1 DEBUG INSTRUCTION FOR USE IN A MULTI-THREADED DATA PROCESSING SYSTEM 审中-公开
标题翻译：用于多线程数据处理系统的调试指令
公开(公告)号：US20100049956A1
公开(公告)日：2010-02-25
申请号：US12195225
申请日：2008-08-20
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F9/30
CPC分类号： G06F9/3005
摘要： For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread.
摘要翻译：为了在包括处理器的数据处理系统中使用，该处理器被配置为执行对应于第一线程的第一组指令和对应于第二线程的第二组指令，提供了一种方法。该方法包括响应于在执行第一组指令时由第一线程执行调试指令，生成调试事件以供第二线程处理。

6. 发明申请

US20100049955A1 DEBUG INSTRUCTION FOR USE IN A MULTI-THREADED DATA PROCESSING SYSTEM 有权
标题翻译：用于多线程数据处理系统的调试指令
公开(公告)号：US20100049955A1
公开(公告)日：2010-02-25
申请号：US12195220
申请日：2008-08-20
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F9/30
CPC分类号： G06F9/3005 , G06F9/3009 , G06F11/3648
摘要： For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug related instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread, wherein processing the debug event comprises causing a halting operation related to the processor.
摘要翻译：为了在包括处理器的数据处理系统中使用，该处理器被配置为执行对应于第一线程的第一组指令和对应于第二线程的第二组指令，提供了一种方法。该方法包括响应于在执行第一组指令时由第一线程执行与调试相关的指令，生成用于由第二线程处理的调试事件，其中处理调试事件包括引起与处理器相关的暂停操作。

7. 发明授权

US09213665B2 Data processor for processing a decorated storage notify 有权
标题翻译：用于处理装饰存储的数据处理器通知
公开(公告)号：US09213665B2
公开(公告)日：2015-12-15
申请号：US12259368
申请日：2008-10-28
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F12/02 , G06F13/42 , G06F13/16 , G06F9/30 , G06F9/38
CPC分类号： G06F13/4217 , G06F9/3004 , G06F9/30043 , G06F9/3834 , G06F9/3885 , G06F13/16 , G06F2213/0054
摘要： A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. A decorated storage notify (DSN) transaction includes an indication of an instruction operation, an address associated with the instruction operation, and a decoration value (i.e. a command to the target device to perform a function in addition to a store or a load). The transaction on the system interconnect includes an address phase and no data phase, thereby improving system bandwidth. In one form the target device (e.g. a memory with functionality in addition to storage functionality) performs a read-modify-write operation using information at a storage location of the target device.
摘要翻译：具有处理器和目标设备的数据处理系统处理装饰指令（即具有装饰值的指令）。诸如处理器之类的数据处理系统的设备通过系统互连将事务发送到目标设备。装饰存储通知（DSN）事务包括指令操作的指示，与指令操作相关联的地址和装饰值（即，除了存储或负载之外还执行功能的目标设备的命令）。系统互连上的事务包括地址阶段和数据阶段，从而提高系统带宽。在一种形式中，目标设备（例如具有除了存储功能之外的功能的存储器）使用目标设备的存储位置处的信息执行读取 - 修改 - 写入操作。

8. 发明授权

US08095831B2 Programmable error actions for a cache in a data processing system 有权
标题翻译：数据处理系统中缓存的可编程错误操作
公开(公告)号：US08095831B2
公开(公告)日：2012-01-10
申请号：US12273155
申请日：2008-11-18
申请人： William C. Moyer , Gary L. Whisenhunt
发明人： William C. Moyer , Gary L. Whisenhunt
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/073 , G06F12/0802
摘要： A data processing system and method of operation has a processor coupled to a cache. Cache control circuitry is coupled to the cache and performs error detection. A user programmable error action control register stores a control value for selecting a type of error action to be taken when a cache error is detected. A first value of the control value permits handling of a cache error that is transparent to the processor, and a second value permits handling of the cache error by taking an exception that is visible to the processor. Various alternate actions to a detected error, including error correction or cache line invalidation, may be taken in response to other values of the control value.
摘要翻译：数据处理系统和操作方法具有耦合到高速缓存的处理器。缓存控制电路耦合到高速缓存并执行错误检测。用户可编程错误动作控制寄存器存储用于选择检测到高速缓存错误时要采取的错误动作的类型的控制值。控制值的第一个值允许处理对处理器透明的高速缓存错误，第二个值允许通过处理器可见的异常来处理高速缓存错误。响应于控制值的其他值，可以采取针对检测到的错误的各种替代动作，包括纠错或高速缓存线无效。

9. 发明申请

US20100107243A1 PERMISSIONS CHECKING FOR DATA PROCESSING INSTRUCTIONS 有权
标题翻译：许可证检查数据处理指令
公开(公告)号：US20100107243A1
公开(公告)日：2010-04-29
申请号：US12259369
申请日：2008-10-28
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F21/00
CPC分类号： G06F12/1416
摘要： A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. The transactions include an indication of an instruction operation, an address associated with the instruction operation, a decoration value (i.e. a command to the target device to perform a function in addition to a primary function of the executed instruction), and access permissions associated with the address. The target device (e.g. a memory with functionality in addition to storage functionality) determines whether a decoration operation specified by the decoration value is permissible based on the received access permissions. The target device performs the decoration operation if appropriate permissions exist.
摘要翻译：具有处理器和目标设备的数据处理系统处理装饰指令（即具有装饰值的指令）。诸如处理器之类的数据处理系统的设备通过系统互连将事务发送到目标设备。交易包括指令操作的指示，与指令操作相关联的地址，装饰值（即除了执行的指令的主要功能之外的对目标设备执行功能的命令）以及与地址。目标设备（例如具有除了存储功能之外的功能的存储器）基于所接收的访问许可来确定装饰值指定的装饰操作是否被允许。如果存在适当的权限，则目标设备执行装饰操作。

10. 发明申请

US20090235059A1 QUALIFICATION OF CONDITIONAL DEBUG INSTRUCTIONS BASED ON ADDRESS 有权
标题翻译：基于地址的条件调试指令的资格
公开(公告)号：US20090235059A1
公开(公告)日：2009-09-17
申请号：US12049984
申请日：2008-03-17
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F9/30
CPC分类号： G06F9/30076 , G06F9/30189
摘要： A processor implementation supports selection of an execution mode for debug instruction instances based on respective addresses thereof in addressable memory can provide an attractive mechanism for executing debug instructions in a way that allows some instances of the instructions to operate with debug semantics while suppressing other instances by executing them with no-operation (NOP) semantics. In some embodiments, selection of operative execution semantics may be based on attributes of a memory page in which a particular debug instruction instance resides. In some embodiments, portions of an address space may be delimited (e.g., using values stored in bounding registers and addresses of particular debug instruction instances compared against the delimited portions to select appropriate execution semantics. In some embodiments, both types of evaluations may be used in selecting appropriate execution semantics for a particular debug instruction instance.
摘要翻译：处理器实现支持基于其可寻址存储器中的相应地址来选择用于调试指令实例的执行模式可以提供用于以允许指令的某些实例以调试语义来操作的方式来执行调试指令的有吸引力的机制，同时通过执行它们与无操作（NOP）语义。在一些实施例中，可操作执行语义的选择可以基于特定调试指令实例驻留在其中的存储器页的属性。在一些实施例中，可以对地址空间的部分进行限定（例如，使用存储在边界寄存器中的值和特定调试指令实例的地址与定界部分进行比较以选择适当的执行语义在一些实施例中，可以使用两种类型的评估在为特定调试指令实例选择适当的执行语义。

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