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21. 发明授权

US07548844B2 Sequential tester for longest prefix search engines 失效
标题翻译：最长前缀搜索引擎的顺序测试器
公开(公告)号：US07548844B2
公开(公告)日：2009-06-16
申请号：US11706943
申请日：2007-02-13
申请人： Alexander E. Andreev , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Anatoli A. Bolotov
IPC分类号： G06F9/45
CPC分类号： G01R31/31917 , Y10S707/99933
摘要： The present invention is directed to a sequential tester for longest prefix search engines. The tester may include a longest prefix search engine, an inputs generator for providing a nearly random flow of input commands to the longest prefix search engine and for outputting a floating rectangle which may represent a search table of the longest prefix search engine, a coding module for providing address and prefix information to the longest prefix search engine, a mapping module for providing data information to the longest prefix search engine, a super search engine for performing super search operations, and an analyzer for computing predicted outputs of the longest prefix search engine and for comparing the predicted outputs with actual outputs computed by the longest prefix search engine.
摘要翻译：本发明涉及一种用于最长前缀搜索引擎的顺序测试器。测试器可以包括最长的前缀搜索引擎，用于向最长的前缀搜索引擎提供几乎随机的输入命令的输入生成器，并输出可以表示最长前缀搜索引擎的搜索表的浮动矩形，编码模块用于向最长前缀搜索引擎提供地址和前缀信息，用于向最长前缀搜索引擎提供数据信息的映射模块，用于执行超级搜索操作的超级搜索引擎和用于计算最长前缀搜索引擎的预测输出的分析器并将预测输出与由最长前缀搜索引擎计算的实际输出进行比较。

22. 发明授权

US07430694B2 Memory BISR architecture for a slice 有权
标题翻译：内存BISR架构为一片
公开(公告)号：US07430694B2
公开(公告)日：2008-09-30
申请号：US11038698
申请日：2005-01-20
申请人： Alexander E. Andreev , Sergey V. Gribok , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Sergey V. Gribok , Anatoli A. Bolotov
IPC分类号： G11C29/00 , G06F12/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/72
摘要： The present invention provides a memory BISR architecture for a slice. The architecture includes (1) a plurality of physical memory instances; (2) a Mem_BIST controller, communicatively coupled to the plurality of physical memory instances, for testing the plurality of physical memory instances; (3) a FLARE module, communicatively coupled to the Mem_BIST controller, including a scan chain of registers for storing test results of the plurality of physical memory instances, each of the plurality of physical memory instances M_i being assigned one FLARE bit f_i, i=1, 2, . . . , n, the FLARE module being used by the Mem_BIST controller to scan in an error vector F=(f—1, f—2, . . . , f_n); (4) a BISR controller, communicatively coupled to the FLARE module, a ROM module and a REPAIR_CONFIGURATION module, for scanning out the error vector F from the FLARE module to computer a repair configuration vector R=(r—1, r—2, . . . , r_n); and (5) a FUSE module, communicatively coupled to the BISR controller and the REPAIR_CONFIGURATION module, for storing the repair configuration vector R. The REPAIR_CONFIGURATION module, communicatively coupled to the plurality of physical memory instances M_i and an integrated circuit design D, includes switch module instances S for switching among the plurality of physical memory instances in accordance with the repair configuration vector R. The ROM module stores a vector U indicating usage of the plurality of physical memory instances M_i by the integrated circuit design D.
摘要翻译：本发明提供了一种用于切片的存储器BISR架构。该架构包括（1）多个物理存储器实例; （2）通信地耦合到所述多个物理存储器实例的用于测试所述多个物理存储器实例的Mem_BIST控制器; （3）FLARE模块，通信地耦合到所述Mem_BIST控制器，包括用于存储所述多个物理存储器实例的测试结果的寄存器扫描链，所述多个物理存储器实例M_i中的每一个被分配一个FLARE位f_i，i = 1，2，... 。。，n，由Mem_BIST控制器使用的FLARE模块以错误向量F =（f 1 - 1，f 2 - ，...，f_n）进行扫描; （4）通信地耦合到FLARE模块的BISR控制器，ROM模块和REPAIR_CONFIGURATION模块，用于从FLARE模块向计算机扫描出错误向量F，修复配置向量R =（r - > 1，r 2，...，r_n）; 和（5）通信地耦合到BISR控制器和REPAIR_CONFIGURATION模块的FUSE模块，用于存储修复配置向量R.通信地耦合到多个物理存储器实例M_i和集成电路设计D的REPAIR_CONFIGURATION模块包括开关模块实例S，用于根据修复配置向量R在多个物理存储器实例之间切换.ROM模块通过集成电路设计D存储指示多个物理存储器实例M_i的使用的向量U。

23. 发明申请

US20080130873A1 Flexible hardware architecture for ECC/HECC based crytography 失效
标题翻译：基于ECC / HECC的基于冰箱的灵活硬件架构
公开(公告)号：US20080130873A1
公开(公告)日：2008-06-05
申请号：US11999211
申请日：2007-12-04
申请人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Paul G. Filseth , Lav D. Ivanovic
发明人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Paul G. Filseth , Lav D. Ivanovic
IPC分类号： H04L9/28
CPC分类号： H04L9/3066 , H04L2209/122
摘要： A circuit for implementing elliptic curve and hyperelliptic curve encryption and decryption operations, having a read only memory with no more than about two kilobytes of accessible memory, containing first programming instructions. An arithmetic logic unit has access to second programming instructions that are resident in a gate-level program disposed in the arithmetic logic unit, and is operable to receive data from no more than one input FIFO register. A microcontroller has no more than about two thousand gates, and is adapted to read the first programming instructions from the read only memory, send control signals to the arithmetic logic unit, and receive flags from the arithmetic logic unit. The arithmetic unit reads the third programming instructions, selectively performs elliptic curve and hyperelliptic curve encryption and decryption operations on the data according to the second programming instructions and the microcontroller, and sends output to no more than one output FIFO register.
摘要翻译：用于实现椭圆曲线和超椭圆曲线加密和解密操作的电路，具有不超过约两千字节可访问存储器的只读存储器，其包含第一编程指令。算术逻辑单元可访问驻留在算术逻辑单元中的门级程序中的第二编程指令，并且可操作以从不超过一个输入FIFO寄存器接收数据。微控制器不超过约二千门，适用于从只读存储器中读取第一个编程指令，向控制逻辑单元发送控制信号，并从算术逻辑单元接收标志。算术单元读取第三个编程指令，根据第二个编程指令和微控制器选择性地对数据执行椭圆曲线和超椭圆曲线加密和解密操作，并将输出发送到不超过一个输出FIFO寄存器。

24. 发明申请

US20080130872A1 MULTIMODE BLOCK CIPHER ARCHITECTURES 有权
标题翻译：多模块式碳水化合物结构
公开(公告)号：US20080130872A1
公开(公告)日：2008-06-05
申请号：US11928628
申请日：2007-10-30
申请人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Paul G. Filseth , Anton I. Sabev
发明人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Paul G. Filseth , Anton I. Sabev
IPC分类号： H04L9/28
CPC分类号： H04L9/0637 , H04L2209/125
摘要： An architecture for a block cipher, where the architecture includes functional units that are logically reconfigurable so as to be able to both encrypt clear text into cipher text and decrypt cipher text into clear text using more than one block cipher mode based on at least one of advanced encryption standard and data encryption standard.
摘要翻译：一种用于块密码的架构，其中该架构包括在逻辑上可重新配置的功能单元，以便能够将明文加密为密文，并使用多于一个的块加密模式，将密文解密为明文，高级加密标准和数据加密标准。

25. 发明授权

US07328382B2 Memory BISR controller architecture 失效
标题翻译：内存BISR控制器架构
公开(公告)号：US07328382B2
公开(公告)日：2008-02-05
申请号：US11270077
申请日：2005-11-09
申请人： Alexander E. Andreev , Sergey V. Gribok , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Sergey V. Gribok , Anatoli A. Bolotov
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/44 , G06F11/00 , G11C29/4401 , G11C29/72
摘要： The present invention provides an architecture of a memory Built-In Self Repair (BISR) controller for connecting to N memory instances, where N is a positive integer greater than 1. The architecture includes N groups of data ports, N BISR_SUBMOD modules for connecting to the N memory instances, and a CLK_IN input port and a BISR_IN input port for setting configuration of the memory BISR controller. Each of the N groups of data ports includes (1) a PHY_IN output port for connecting to input of a corresponding memory instance; (2) a PHY_OUT input port for connecting to output of the corresponding memory instance; (3) a LOG_IN input port for sending signals to the corresponding memory instance; and (4) a LOG_OUT output port for receiving signals from the corresponding memory instance. Each of the N BISR_SUBMOD modules includes a flip-flop, a first mux and a second mux. The CLK_IN input port is connected to clock inputs of all N flip-flops of the memory BISR controller. The BISR_IN input port is connected to data input of a first flip-flop, and output of a K-th flip-flop is connected to input of a (K+1)-th flip-flop, K=1, 2, . . . , N-1. When at least one of the N memory instances is defective, the memory BISR controller may reconfigure connections among the N memory instances to use other memory instance(s) instead of the defective memory instance(s).
摘要翻译：本发明提供了一种用于连接到N个存储器实例的存储器内置自修复（BISR）控制器的架构，其中N是大于1的正整数。该架构包括N组数据端口，N个BISR_SUBMOD模块用于连接到 N个内存实例，以及用于设置内存BISR控制器配置的CLK_IN输入端口和BISR_IN输入端口。 N组数据端口中的每一个包括（1）用于连接到相应存储器实例的输入的PHY_IN输出端口; （2）用于连接到相应存储器实例的输出的PHY_OUT输入端口; （3）用于向相应的存储器实例发送信号的LOG_IN输入端口; 和（4）用于从相应的存储器实例接收信号的LOG_OUT输出端口。 N BISR_SUBMOD模块中的每一个包括触发器，第一多路复用器和第二复用器。 CLK_IN输入端口连接到存储器BISR控制器的所有N个触发器的时钟输入。 BISR_IN输入端口连接到第一触发器的数据输入，第K触发器的输出连接到第（K + 1）个触发器的输入，K = 1,2。。。，N-1。当N个存储器实例中的至少一个存在缺陷时，存储器BISR控制器可以重新配置N个存储器实例之间的连接以使用其他存储器实例而不是缺陷存储器实例。

26. 发明授权

US07216278B2 Method and BIST architecture for fast memory testing in platform-based integrated circuit 有权
标题翻译：方法和BIST架构，用于基于平台的集成电路中的快速内存测试
公开(公告)号：US07216278B2
公开(公告)日：2007-05-08
申请号：US10999493
申请日：2004-11-30
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/26 , G11C2029/2602
摘要： The present invention provides a method and BIST architecture for fast memory testing in a platform-based integrated circuit. The method may include steps as follows. An Mem-BIST controller transmitter is started to generate input signals for a memory in a platform using a deterministic and unconditional test algorithm. The input signals are delayed by a first group of pipelines by n clock cycles. The delayed input signals are received by the memory and an output signal is generated by the memory. The output signal is delayed by a second pipeline by m clock cycles. An Mem-BIST controller receiver is started to receive the delayed output signal for comparison.
摘要翻译：本发明提供了一种用于基于平台的集成电路中的快速存储器测试的方法和BIST架构。该方法可以包括以下步骤。启动Mem-BIST控制器发送器，使用确定性和无条件测试算法为平台中的存储器生成输入信号。输入信号被第一组管道延迟了n个时钟周期。延迟的输入信号由存储器接收，并且由存储器产生输出信号。输出信号被第二个流水线延迟了m个时钟周期。启动Mem-BIST控制器接收器以接收延迟的输出信号进行比较。

27. 发明授权

US06505336B1 Channel router with buffer insertion 失效
标题翻译：通道路由器插入缓冲区
公开(公告)号：US06505336B1
公开(公告)日：2003-01-07
申请号：US09804939
申请日：2001-03-13
申请人： Alexander E. Andreev , Pedja Raspopovic , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Pedja Raspopovic , Anatoli A. Bolotov
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： Channels are routed in an integrated circuit layout by reserving grid positions for buffers. Cell pins are identified at different y-coordinates to be connected by the channel. A determination is made as to the necessity of a jog between vertical segments, and if so, a y-coordinate is assigned to each such jog. An x-coordinate is assigned to each channel segment extending across the y-coordinates. Y-coordinates are assigned to buffers to be connected to the channel.
摘要翻译：通过为缓冲器保留网格位置，通道以集成电路布局布线。单元引脚在不同的y坐标处被识别，以通过通道连接。确定垂直段之间的点动的必要性，如果是，则对每个这样的点动分配y坐标。 x坐标被分配给延伸穿过y坐标的每个通道段。 Y坐标被分配给要连接到通道的缓冲器。

28. 发明申请

US20130346824A1 DYNAMICALLY CONTROLLING THE NUMBER OF LOCAL ITERATIONS IN AN ITERATIVE DECODER 有权
标题翻译：动态地控制迭代解码器中的本地迭代数
公开(公告)号：US20130346824A1
公开(公告)日：2013-12-26
申请号：US13528237
申请日：2012-06-20
申请人： Anatoli A. Bolotov , Aleksey Alexandrovich Letunovskiy , Ivan Leonidovich Mazurenko , Lav D. Ivanovic , Fan Zhang
发明人： Anatoli A. Bolotov , Aleksey Alexandrovich Letunovskiy , Ivan Leonidovich Mazurenko , Lav D. Ivanovic , Fan Zhang
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/6325 , H03M13/1111 , H03M13/1128 , H03M13/2957
摘要： An iterative decoder dynamically controls the number of local iterations of error-correction decoding performed for each global iteration of channel detection. In so doing, the iterative decoder (i) limits the number of local iterations that are performed after error-correction decoding has likely encountered a trapping set and (ii) permits decoding to continue when error-correction decoding is on the path to converging on a valid codeword. To predict whether error-correction decoding is on the path to encountering a trapping set or converging on a valid codeword, a model is generated based on observed numbers of unsatisfied check nodes for a specified number of local iterations. For local iterations following the specified number of local iterations, the observed numbers of unsatisfied check nodes are then compared to the model to determine whether to continue or terminate local iterations of error-correction decoding.
摘要翻译：迭代解码器动态地控制针对信道检测的每个全局迭代执行的纠错解码的局部迭代次数。在这样做时，迭代解码器（i）限制纠错解码可能遇到陷阱集之后执行的局部迭代次数，并且（ii）当纠错解码在路径上收敛时允许解码继续一个有效的代码字。为了预测误差校正解码是否在遇到陷阱集合或收敛于有效码字的路径上，基于观察到的针对指定数量的本地迭代的不满足的校验节点的数量来生成模型。对于在指定数量的本地迭代之后的局部迭代，观察到的不满足校验节点的数量然后与模型进行比较，以确定是否继续或终止纠错解码的本地迭代。

29. 发明授权

US08359479B2 High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks 有权
标题翻译：用于加密应用的高性能算术逻辑单元（ALU），具有针对侧面信道攻击的内置对策
公开(公告)号：US08359479B2
公开(公告)日：2013-01-22
申请号：US12218756
申请日：2008-07-17
申请人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic , Paul G. Filseth
发明人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic , Paul G. Filseth
IPC分类号： G06F12/14
CPC分类号： G06F7/723 , G06F2207/7223 , G06F2207/7266 , H04L9/002 , H04L9/0662
摘要： The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device.
摘要翻译：本发明是一种配置用于提供针对攻击的对策的密码引擎，包括：输入/输出（I / O）控制单元，存储器，控制器和算术逻辑单元（ALU）。存储器与I / O控制单元通信地耦合，从I / O控制单元接收输入，并根据接收的输入向I / O控制单元提供输出。控制器与I / O控制单元通信耦合，用于发送和接收控制信号。 ALU包括多个存储组件和计算组件。 ALU与控制器通信耦合，并从控制器接收/发送状态位和标志的命令。 ALU进一步与存储器通信耦合，并且被配置为向存储器提供/接收输入信号的输出信号。此外，密码引擎被配置为与主机计算设备通信地耦合。

30. 发明授权

US08023644B2 Multimode block cipher architectures 有权
标题翻译：多模块分组密码体系结构
公开(公告)号：US08023644B2
公开(公告)日：2011-09-20
申请号：US11928628
申请日：2007-10-30
申请人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Paul G. Filseth , Anton I. Sabev
发明人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Paul G. Filseth , Anton I. Sabev
IPC分类号： H04L9/00
CPC分类号： H04L9/0637 , H04L2209/125
摘要： An architecture for a block cipher, where the architecture includes functional units that are logically reconfigurable so as to be able to both encrypt clear text into cipher text and decrypt cipher text into clear text using more than one block cipher mode based on at least one of advanced encryption standard and data encryption standard.
摘要翻译：一种用于块密码的架构，其中该架构包括在逻辑上可重新配置的功能单元，以便能够将明文加密为密文，并使用多于一个的块加密模式，将密文解密为明文，高级加密标准和数据加密标准。

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