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1. 发明授权

US08832532B2 Dynamically controlling the number of local iterations in an iterative decoder 有权
标题翻译：动态地控制迭代解码器中的局部迭代次数
公开(公告)号：US08832532B2
公开(公告)日：2014-09-09
申请号：US13528237
申请日：2012-06-20
申请人： Anatoli A. Bolotov , Aleksey Alexandrovich Letunovskiy , Ivan Leonidovich Mazurenko , Lav D. Ivanovic , Fan Zhang
发明人： Anatoli A. Bolotov , Aleksey Alexandrovich Letunovskiy , Ivan Leonidovich Mazurenko , Lav D. Ivanovic , Fan Zhang
IPC分类号： H03M13/00
CPC分类号： H03M13/6325 , H03M13/1111 , H03M13/1128 , H03M13/2957
摘要： An iterative decoder dynamically controls the number of local iterations of error-correction decoding performed for each global iteration of channel detection. In so doing, the iterative decoder (i) limits the number of local iterations that are performed after error-correction decoding has likely encountered a trapping set and (ii) permits decoding to continue when error-correction decoding is on the path to converging on a valid codeword. To predict whether error-correction decoding is on the path to encountering a trapping set or converging on a valid codeword, a model is generated based on observed numbers of unsatisfied check nodes for a specified number of local iterations. For local iterations following the specified number of local iterations, the observed numbers of unsatisfied check nodes are then compared to the model to determine whether to continue or terminate local iterations of error-correction decoding.
摘要翻译：迭代解码器动态地控制针对信道检测的每个全局迭代执行的纠错解码的局部迭代次数。在这样做时，迭代解码器（i）限制纠错解码可能遇到陷阱集之后执行的局部迭代次数，并且（ii）当纠错解码在路径上收敛时允许解码继续一个有效的代码字。为了预测误差校正解码是否在遇到陷阱集合或收敛于有效码字的路径上，基于观察到的针对指定数量的本地迭代的不满足的校验节点的数量来生成模型。对于在指定数量的本地迭代之后的局部迭代，观察到的不满足校验节点的数量然后与模型进行比较，以确定是否继续或终止纠错解码的本地迭代。

2. 发明申请

US20130283114A1 Systems and Methods for Locating and Correcting Decoder Mis-Corrections 有权
标题翻译：用于定位和校正解码器误差校正的系统和方法
公开(公告)号：US20130283114A1
公开(公告)日：2013-10-24
申请号：US13450289
申请日：2012-04-18
申请人： Shaohua Yang , Yang Han , Chung-Li Wang , Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic
发明人： Shaohua Yang , Yang Han , Chung-Li Wang , Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic
IPC分类号： G06F11/07 , H03M13/05 , G06F11/10 , H03M13/09
CPC分类号： H03M13/00 , G11B20/1833 , G11B2020/1843 , G11B2020/185 , G11B2220/2516 , G11B2220/415 , H03M7/6005 , H03M13/093 , H03M13/1102 , H03M13/1108 , H03M13/1128 , H03M13/3723 , H03M13/3746 , H03M13/41 , H03M13/6511 , H03M13/6513
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括具有数据解码器电路，元件修改电路，元件修改日志和错误校正检测电路的数据解码电路的数据处理系统。

3. 发明申请

US20130346824A1 DYNAMICALLY CONTROLLING THE NUMBER OF LOCAL ITERATIONS IN AN ITERATIVE DECODER 有权
标题翻译：动态地控制迭代解码器中的本地迭代数
公开(公告)号：US20130346824A1
公开(公告)日：2013-12-26
申请号：US13528237
申请日：2012-06-20
申请人： Anatoli A. Bolotov , Aleksey Alexandrovich Letunovskiy , Ivan Leonidovich Mazurenko , Lav D. Ivanovic , Fan Zhang
发明人： Anatoli A. Bolotov , Aleksey Alexandrovich Letunovskiy , Ivan Leonidovich Mazurenko , Lav D. Ivanovic , Fan Zhang
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/6325 , H03M13/1111 , H03M13/1128 , H03M13/2957
摘要： An iterative decoder dynamically controls the number of local iterations of error-correction decoding performed for each global iteration of channel detection. In so doing, the iterative decoder (i) limits the number of local iterations that are performed after error-correction decoding has likely encountered a trapping set and (ii) permits decoding to continue when error-correction decoding is on the path to converging on a valid codeword. To predict whether error-correction decoding is on the path to encountering a trapping set or converging on a valid codeword, a model is generated based on observed numbers of unsatisfied check nodes for a specified number of local iterations. For local iterations following the specified number of local iterations, the observed numbers of unsatisfied check nodes are then compared to the model to determine whether to continue or terminate local iterations of error-correction decoding.
摘要翻译：迭代解码器动态地控制针对信道检测的每个全局迭代执行的纠错解码的局部迭代次数。在这样做时，迭代解码器（i）限制纠错解码可能遇到陷阱集之后执行的局部迭代次数，并且（ii）当纠错解码在路径上收敛时允许解码继续一个有效的代码字。为了预测误差校正解码是否在遇到陷阱集合或收敛于有效码字的路径上，基于观察到的针对指定数量的本地迭代的不满足的校验节点的数量来生成模型。对于在指定数量的本地迭代之后的局部迭代，观察到的不满足校验节点的数量然后与模型进行比较，以确定是否继续或终止纠错解码的本地迭代。

4. 发明授权

US08411853B2 Alternate galois field advanced encryption standard round 有权
标题翻译：替代galois域高级加密标准轮
公开(公告)号：US08411853B2
公开(公告)日：2013-04-02
申请号：US12200037
申请日：2008-08-28
申请人： Paul G. Filseth , Mikhail Grinchuk , Anatoli Bolotov , Lav D. Ivanovic
发明人： Paul G. Filseth , Mikhail Grinchuk , Anatoli Bolotov , Lav D. Ivanovic
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , H04L2209/125
摘要： An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate second Galois Field elements by performing a first Galois Field inversion on first Galois Field elements, the first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard and (ii) generate third Galois Field elements by multiplying the second Galois Field elements by an inverse of a predetermined matrix. The second circuit may be configured to (i) generate fourth Galois Field elements by processing the third Galois Field elements in a current encryption round while in a non-skip mode, (ii) generate fifth Galois Field elements by multiplying the fourth Galois Field elements by the predetermined matrix and (iii) present the fifth Galois Field elements as updated versions of the first Galois Field elements in advance of a next encryption round.
摘要翻译：公开了一种具有第一电路和第二电路的装置。第一电路可以被配置为（i）通过在第一伽罗瓦域元件上执行第一伽罗瓦域反演来产生第二伽罗瓦域元件，第一伽罗瓦域反转与由高级加密标准定义的第二伽罗瓦域反演不同，）通过将第二伽罗瓦域元素乘以预定矩阵的倒数来产生第三伽罗瓦域元素。第二电路可以被配置为（i）通过在非跳过模式下处理当前加密循环中的第三伽罗瓦域元素来产生第四伽罗瓦域元素，（ii）通过将第四伽罗瓦域元素乘以第四伽罗瓦域元素通过预定矩阵和（iii）在下一个加密轮次之前将第五伽罗瓦域元素呈现为第一伽罗瓦域元素的更新版本。

5. 发明授权

US08359479B2 High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks 有权
标题翻译：用于加密应用的高性能算术逻辑单元（ALU），具有针对侧面信道攻击的内置对策
公开(公告)号：US08359479B2
公开(公告)日：2013-01-22
申请号：US12218756
申请日：2008-07-17
申请人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic , Paul G. Filseth
发明人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic , Paul G. Filseth
IPC分类号： G06F12/14
CPC分类号： G06F7/723 , G06F2207/7223 , G06F2207/7266 , H04L9/002 , H04L9/0662
摘要： The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device.
摘要翻译：本发明是一种配置用于提供针对攻击的对策的密码引擎，包括：输入/输出（I / O）控制单元，存储器，控制器和算术逻辑单元（ALU）。存储器与I / O控制单元通信地耦合，从I / O控制单元接收输入，并根据接收的输入向I / O控制单元提供输出。控制器与I / O控制单元通信耦合，用于发送和接收控制信号。 ALU包括多个存储组件和计算组件。 ALU与控制器通信耦合，并从控制器接收/发送状态位和标志的命令。 ALU进一步与存储器通信耦合，并且被配置为向存储器提供/接收输入信号的输出信号。此外，密码引擎被配置为与主机计算设备通信地耦合。

6. 发明授权

US08063659B2 Low depth programmable priority encoders 有权
标题翻译：低深度可编程优先编码器
公开(公告)号：US08063659B2
公开(公告)日：2011-11-22
申请号：US12902376
申请日：2010-10-12
申请人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
发明人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译：公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。第二电路可以被配置为响应于第一信号而产生多个第二信号。第三电路可以被配置为响应于第二信号而产生多个使能信号。第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。可以独立于使能信号产生第二信号。

7. 发明授权

US08023644B2 Multimode block cipher architectures 有权
标题翻译：多模块分组密码体系结构
公开(公告)号：US08023644B2
公开(公告)日：2011-09-20
申请号：US11928628
申请日：2007-10-30
申请人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Paul G. Filseth , Anton I. Sabev
发明人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Paul G. Filseth , Anton I. Sabev
IPC分类号： H04L9/00
CPC分类号： H04L9/0637 , H04L2209/125
摘要： An architecture for a block cipher, where the architecture includes functional units that are logically reconfigurable so as to be able to both encrypt clear text into cipher text and decrypt cipher text into clear text using more than one block cipher mode based on at least one of advanced encryption standard and data encryption standard.
摘要翻译：一种用于块密码的架构，其中该架构包括在逻辑上可重新配置的功能单元，以便能够将明文加密为密文，并使用多于一个的块加密模式，将密文解密为明文，高级加密标准和数据加密标准。

8. 发明授权

US07839164B1 Low depth programmable priority encoders 有权
标题翻译：低深度可编程优先编码器
公开(公告)号：US07839164B1
公开(公告)日：2010-11-23
申请号：US12465810
申请日：2009-05-14
申请人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
发明人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译：公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。第二电路可以被配置为响应于第一信号而产生多个第二信号。第三电路可以被配置为响应于第二信号而产生多个使能信号。第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。可以独立于使能信号产生第二信号。

9. 发明申请

US20100057823A1 Alternate galois field advanced encryption standard round 有权
标题翻译：替代galois域高级加密标准轮
公开(公告)号：US20100057823A1
公开(公告)日：2010-03-04
申请号：US12200037
申请日：2008-08-28
申请人： Paul G. Filseth , Mikhail Grinchuk , Anatoli Bolotov , Lav D. Ivanovic
发明人： Paul G. Filseth , Mikhail Grinchuk , Anatoli Bolotov , Lav D. Ivanovic
IPC分类号： G06F7/72 , G06F17/10 , H04L9/28
CPC分类号： H04L9/0631 , H04L2209/125
摘要： An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate second Galois Field elements by performing a first Galois Field inversion on first Galois Field elements, the first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard and (ii) generate third Galois Field elements by multiplying the second Galois Field elements by an inverse of a predetermined matrix. The second circuit may be configured to (i) generate fourth Galois Field elements by processing the third Galois Field elements in a current encryption round while in a non-skip mode, (ii) generate fifth Galois Field elements by multiplying the fourth Galois Field elements by the predetermined matrix and (iii) present the fifth Galois Field elements as updated versions of the first Galois Field elements in advance of a next encryption round.
摘要翻译：公开了一种具有第一电路和第二电路的装置。第一电路可以被配置为（i）通过在第一伽罗瓦域元件上执行第一伽罗瓦域反演来产生第二伽罗瓦域元件，第一伽罗瓦域反转与由高级加密标准定义的第二伽罗瓦域反演不同，）通过将第二伽罗瓦域元素乘以预定矩阵的倒数来产生第三伽罗瓦域元素。第二电路可以被配置为（i）通过在非跳过模式下处理当前加密循环中的第三伽罗瓦域元素来产生第四伽罗瓦域元素，（ii）通过将第四伽罗瓦域元素乘以第四伽罗瓦域元素通过预定矩阵和（iii）在下一个加密轮次之前将第五伽罗瓦域元素呈现为第一伽罗瓦域元素的更新版本。

10. 发明申请

US20100017622A1 High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks 有权
标题翻译：用于加密应用的高性能算术逻辑单元（ALU），具有针对侧面信道攻击的内置对策
公开(公告)号：US20100017622A1
公开(公告)日：2010-01-21
申请号：US12218756
申请日：2008-07-17
申请人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic , Paul G. Filseth
发明人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic , Paul G. Filseth
IPC分类号： H04L9/06
CPC分类号： G06F7/723 , G06F2207/7223 , G06F2207/7266 , H04L9/002 , H04L9/0662
摘要： The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device.
摘要翻译：本发明是一种配置用于提供针对攻击的对策的密码引擎，包括：输入/输出（I / O）控制单元，存储器，控制器和算术逻辑单元（ALU）。存储器与I / O控制单元通信地耦合，从I / O控制单元接收输入，并根据接收的输入向I / O控制单元提供输出。控制器与I / O控制单元通信耦合，用于发送和接收控制信号。 ALU包括多个存储组件和计算组件。 ALU与控制器通信耦合，并从控制器接收/发送状态位和标志的命令。 ALU进一步与存储器通信耦合，并且被配置为向存储器提供/接收输入信号的输出信号。此外，密码引擎被配置为与主机计算设备通信地耦合。

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