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1. 发明授权

US08898539B2 Correcting errors in miscorrected codewords using list decoding 有权
标题翻译：使用列表解码校正错误码字中的错误
公开(公告)号：US08898539B2
公开(公告)日：2014-11-25
申请号：US13611158
申请日：2012-09-12
申请人： Yang Han , Shaohua Yang , Zongwang Li , Fan Zhang , Anatoli A. Bolotov , Mikhail I. Grinchuk , Paul G. Filseth , Lav D. Ivanovic
发明人： Yang Han , Shaohua Yang , Zongwang Li , Fan Zhang , Anatoli A. Bolotov , Mikhail I. Grinchuk , Paul G. Filseth , Lav D. Ivanovic
IPC分类号： H03M13/00
CPC分类号： H03M13/6337 , H03M13/09 , H03M13/1102 , H03M13/1128 , H03M13/152 , H03M13/2957 , H03M13/3707 , H03M13/3753 , H03M13/451
摘要： A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.
摘要翻译：通信系统的接收路径包括纠错解码器，错误检测解码器和码字调节器。误差校正解码器对接收的码字进行纠错解码，以生成有效的码字。错误检测解码器对有效码字执行错误检测解码，以确定有效码字是否是发送的正确码字。如果有效码字不是正确的码字，则码字调节器通过向有效码字应用误差向量来生成经调整的有效码字。错误检测解码器对经调整的有效码字执行错误检测解码，以确定调整后的有效码字是否为正确码字。当纠错解码器产生不正确的有效码字时，调整有效码字使得接收路径能够恢复正确的码字而不重传或重新检测码字。

2. 发明授权

US08359479B2 High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks 有权
标题翻译：用于加密应用的高性能算术逻辑单元（ALU），具有针对侧面信道攻击的内置对策
公开(公告)号：US08359479B2
公开(公告)日：2013-01-22
申请号：US12218756
申请日：2008-07-17
申请人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic , Paul G. Filseth
发明人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic , Paul G. Filseth
IPC分类号： G06F12/14
CPC分类号： G06F7/723 , G06F2207/7223 , G06F2207/7266 , H04L9/002 , H04L9/0662
摘要： The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device.
摘要翻译：本发明是一种配置用于提供针对攻击的对策的密码引擎，包括：输入/输出（I / O）控制单元，存储器，控制器和算术逻辑单元（ALU）。存储器与I / O控制单元通信地耦合，从I / O控制单元接收输入，并根据接收的输入向I / O控制单元提供输出。控制器与I / O控制单元通信耦合，用于发送和接收控制信号。 ALU包括多个存储组件和计算组件。 ALU与控制器通信耦合，并从控制器接收/发送状态位和标志的命令。 ALU进一步与存储器通信耦合，并且被配置为向存储器提供/接收输入信号的输出信号。此外，密码引擎被配置为与主机计算设备通信地耦合。

3. 发明授权

US08023644B2 Multimode block cipher architectures 有权
标题翻译：多模块分组密码体系结构
公开(公告)号：US08023644B2
公开(公告)日：2011-09-20
申请号：US11928628
申请日：2007-10-30
申请人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Paul G. Filseth , Anton I. Sabev
发明人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Paul G. Filseth , Anton I. Sabev
IPC分类号： H04L9/00
CPC分类号： H04L9/0637 , H04L2209/125
摘要： An architecture for a block cipher, where the architecture includes functional units that are logically reconfigurable so as to be able to both encrypt clear text into cipher text and decrypt cipher text into clear text using more than one block cipher mode based on at least one of advanced encryption standard and data encryption standard.
摘要翻译：一种用于块密码的架构，其中该架构包括在逻辑上可重新配置的功能单元，以便能够将明文加密为密文，并使用多于一个的块加密模式，将密文解密为明文，高级加密标准和数据加密标准。

4. 发明申请

US20100017622A1 High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks 有权
标题翻译：用于加密应用的高性能算术逻辑单元（ALU），具有针对侧面信道攻击的内置对策
公开(公告)号：US20100017622A1
公开(公告)日：2010-01-21
申请号：US12218756
申请日：2008-07-17
申请人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic , Paul G. Filseth
发明人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic , Paul G. Filseth
IPC分类号： H04L9/06
CPC分类号： G06F7/723 , G06F2207/7223 , G06F2207/7266 , H04L9/002 , H04L9/0662
摘要： The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device.
摘要翻译：本发明是一种配置用于提供针对攻击的对策的密码引擎，包括：输入/输出（I / O）控制单元，存储器，控制器和算术逻辑单元（ALU）。存储器与I / O控制单元通信地耦合，从I / O控制单元接收输入，并根据接收的输入向I / O控制单元提供输出。控制器与I / O控制单元通信耦合，用于发送和接收控制信号。 ALU包括多个存储组件和计算组件。 ALU与控制器通信耦合，并从控制器接收/发送状态位和标志的命令。 ALU进一步与存储器通信耦合，并且被配置为向存储器提供/接收输入信号的输出信号。此外，密码引擎被配置为与主机计算设备通信地耦合。

5. 发明申请

US20080130873A1 Flexible hardware architecture for ECC/HECC based crytography 失效
标题翻译：基于ECC / HECC的基于冰箱的灵活硬件架构
公开(公告)号：US20080130873A1
公开(公告)日：2008-06-05
申请号：US11999211
申请日：2007-12-04
申请人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Paul G. Filseth , Lav D. Ivanovic
发明人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Paul G. Filseth , Lav D. Ivanovic
IPC分类号： H04L9/28
CPC分类号： H04L9/3066 , H04L2209/122
摘要： A circuit for implementing elliptic curve and hyperelliptic curve encryption and decryption operations, having a read only memory with no more than about two kilobytes of accessible memory, containing first programming instructions. An arithmetic logic unit has access to second programming instructions that are resident in a gate-level program disposed in the arithmetic logic unit, and is operable to receive data from no more than one input FIFO register. A microcontroller has no more than about two thousand gates, and is adapted to read the first programming instructions from the read only memory, send control signals to the arithmetic logic unit, and receive flags from the arithmetic logic unit. The arithmetic unit reads the third programming instructions, selectively performs elliptic curve and hyperelliptic curve encryption and decryption operations on the data according to the second programming instructions and the microcontroller, and sends output to no more than one output FIFO register.
摘要翻译：用于实现椭圆曲线和超椭圆曲线加密和解密操作的电路，具有不超过约两千字节可访问存储器的只读存储器，其包含第一编程指令。算术逻辑单元可访问驻留在算术逻辑单元中的门级程序中的第二编程指令，并且可操作以从不超过一个输入FIFO寄存器接收数据。微控制器不超过约二千门，适用于从只读存储器中读取第一个编程指令，向控制逻辑单元发送控制信号，并从算术逻辑单元接收标志。算术单元读取第三个编程指令，根据第二个编程指令和微控制器选择性地对数据执行椭圆曲线和超椭圆曲线加密和解密操作，并将输出发送到不超过一个输出FIFO寄存器。

6. 发明申请

US20080130872A1 MULTIMODE BLOCK CIPHER ARCHITECTURES 有权
标题翻译：多模块式碳水化合物结构
公开(公告)号：US20080130872A1
公开(公告)日：2008-06-05
申请号：US11928628
申请日：2007-10-30
申请人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Paul G. Filseth , Anton I. Sabev
发明人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Paul G. Filseth , Anton I. Sabev
IPC分类号： H04L9/28
CPC分类号： H04L9/0637 , H04L2209/125
摘要： An architecture for a block cipher, where the architecture includes functional units that are logically reconfigurable so as to be able to both encrypt clear text into cipher text and decrypt cipher text into clear text using more than one block cipher mode based on at least one of advanced encryption standard and data encryption standard.
摘要翻译：一种用于块密码的架构，其中该架构包括在逻辑上可重新配置的功能单元，以便能够将明文加密为密文，并使用多于一个的块加密模式，将密文解密为明文，高级加密标准和数据加密标准。

7. 发明申请

US20140075264A1 CORRECTING ERRORS IN MISCORRECTED CODEWORDS USING LIST DECODING 有权
标题翻译：使用列表解码纠正错误的代码中的错误
公开(公告)号：US20140075264A1
公开(公告)日：2014-03-13
申请号：US13611158
申请日：2012-09-12
申请人： Yang Han , Shaohua Yang , Zongwang Li , Fan Zhang , Anatoli A. Bolotov , Mikhail I. Grinchuk , Paul G. Filseth , Lav D. Ivanovic
发明人： Yang Han , Shaohua Yang , Zongwang Li , Fan Zhang , Anatoli A. Bolotov , Mikhail I. Grinchuk , Paul G. Filseth , Lav D. Ivanovic
IPC分类号： H03M13/05 , H03M13/13
CPC分类号： H03M13/6337 , H03M13/09 , H03M13/1102 , H03M13/1128 , H03M13/152 , H03M13/2957 , H03M13/3707 , H03M13/3753 , H03M13/451
摘要： A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.
摘要翻译：通信系统的接收路径包括纠错解码器，错误检测解码器和码字调节器。误差校正解码器对接收的码字进行纠错解码，以生成有效的码字。错误检测解码器对有效码字执行错误检测解码，以确定有效码字是否是发送的正确码字。如果有效码字不是正确的码字，则码字调节器通过向有效码字应用误差向量来生成经调整的有效码字。错误检测解码器对经调整的有效码字执行错误检测解码，以确定调整后的有效码字是否为正确码字。当纠错解码器产生不正确的有效码字时，调整有效码字使得接收路径能够恢复正确的码字而不重传或重新检测码字。

8. 发明申请

US20130283114A1 Systems and Methods for Locating and Correcting Decoder Mis-Corrections 有权
标题翻译：用于定位和校正解码器误差校正的系统和方法
公开(公告)号：US20130283114A1
公开(公告)日：2013-10-24
申请号：US13450289
申请日：2012-04-18
申请人： Shaohua Yang , Yang Han , Chung-Li Wang , Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic
发明人： Shaohua Yang , Yang Han , Chung-Li Wang , Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic
IPC分类号： G06F11/07 , H03M13/05 , G06F11/10 , H03M13/09
CPC分类号： H03M13/00 , G11B20/1833 , G11B2020/1843 , G11B2020/185 , G11B2220/2516 , G11B2220/415 , H03M7/6005 , H03M13/093 , H03M13/1102 , H03M13/1108 , H03M13/1128 , H03M13/3723 , H03M13/3746 , H03M13/41 , H03M13/6511 , H03M13/6513
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括具有数据解码器电路，元件修改电路，元件修改日志和错误校正检测电路的数据解码电路的数据处理系统。

9. 发明授权

US09417847B2 Low depth combinational finite field multiplier 有权
标题翻译：低深度组合有限域乘法器
公开(公告)号：US09417847B2
公开(公告)日：2016-08-16
申请号：US13231129
申请日：2011-09-13
申请人： Sergey B. Gashkov , Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Anatoly A. Chasovshikh , Alexei V. Galatenko , Igor V. Kucherenko
发明人： Sergey B. Gashkov , Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Anatoly A. Chasovshikh , Alexei V. Galatenko , Igor V. Kucherenko
IPC分类号： G06F7/72 , G06F17/50
CPC分类号： G06F7/724 , G06F17/505
摘要： A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising a plurality of polynomial results of a particular multiplier scheme based on a plurality of parameters of the multiplier. The first circuit is generally configured to multiply a plurality of polynomials. Step (B) may generate a second circuit comprising a plurality of polynomial evaluators based on the parameters. The second circuit may be (i) connected to the first circuit and (ii) configured to evaluate a polynomial modulo operation. Step (C) may generate the design of the multiplier in combinational logic by optimizing a depth of a plurality of logic gates through the first circuit and the second circuit. A product of the polynomials generally resides in a finite field.
摘要翻译：公开了一种生成乘法器设计的方法。该方法通常包括步骤（A）至（C）。步骤（A）可以基于乘法器的多个参数来生成包括特定乘法器方案的多个多项式结果的第一电路。第一电路通常被配置为乘以多个多项式。步骤（B）可以基于参数生成包括多个多项式评估器的第二电路。第二电路可以是（i）连接到第一电路，（ii）被配置为评估多项式模运算。步骤（C）可以通过优化通过第一电路和第二电路的多个逻辑门的深度来生成组合逻辑中乘法器的设计。多项式的乘积通常位于有限域中。

10. 发明授权

US08782487B2 Systems and methods for locating and correcting decoder mis-corrections 有权
标题翻译：用于定位和纠正解码器错误校正的系统和方法
公开(公告)号：US08782487B2
公开(公告)日：2014-07-15
申请号：US13450289
申请日：2012-04-18
申请人： Shaohua Yang , Yang Han , Chung-Li Wang , Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic
发明人： Shaohua Yang , Yang Han , Chung-Li Wang , Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic
IPC分类号： H03M13/00 , G06F11/00 , H04L1/00 , G11C29/00 , H03M13/41 , H03M13/37 , H03M13/09 , H03M13/11 , H03M7/30 , G11B20/18
CPC分类号： H03M13/00 , G11B20/1833 , G11B2020/1843 , G11B2020/185 , G11B2220/2516 , G11B2220/415 , H03M7/6005 , H03M13/093 , H03M13/1102 , H03M13/1108 , H03M13/1128 , H03M13/3723 , H03M13/3746 , H03M13/41 , H03M13/6511 , H03M13/6513
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括具有数据解码器电路，元件修改电路，元件修改日志和错误校正检测电路的数据解码电路的数据处理系统。

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