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1. 发明授权

US06453453B1 Process for solving assignment problems in integrated circuit designs with unimodal object penalty functions and linearly ordered set of boxes 有权
标题翻译：用单向对象惩罚函数和线性有序集合集合来解决集成电路设计中的赋值问题的过程
公开(公告)号：US06453453B1
公开(公告)日：2002-09-17
申请号：US09833142
申请日：2001-04-11
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Pedja Raspopovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Pedja Raspopovic
IPC分类号： G06F945
CPC分类号： G06F17/5068
摘要： A linear assignment problem for an ordered system containing a plurality of boxes each containing an object having an associated penalty function is solved. A hierarchy contains a bottom level containing at least as many generalized boxes as there are boxes in the assignment problem, and top and intermediate levels. The objects of the assignment problem are placed in the generalized box of the top level. A first local task is executed to transition the contents of a generalized box of a higher level to at least two generalized boxes of the next lower level. A second local task is executed on the generalized boxes of the lower level to minimize a global penalty function. The first and second tasks are executed through successive iterations until all of the objects are placed in the generalized boxes in the bottom level in a layout having minimal penalty function.
摘要翻译：解决了包含多个框的有序系统的线性分配问题，每个框包含具有相关惩罚函数的对象。层次结构包含底层，包含至少与分配问题中的框以及顶级和中级相同的通用框。分配问题的对象被放置在顶层的广义框中。执行第一本地任务以将较高级别的广义框的内容转换到下一较低级的至少两个广义框。在较低级别的广义框上执行第二个本地任务，以最小化全局惩罚函数。第一和第二任务通过连续迭代执行，直到所有对象都放置在具有最小惩罚函数的布局中的底层中的广义框中。

2. 发明授权

US06505336B1 Channel router with buffer insertion 失效
标题翻译：通道路由器插入缓冲区
公开(公告)号：US06505336B1
公开(公告)日：2003-01-07
申请号：US09804939
申请日：2001-03-13
申请人： Alexander E. Andreev , Pedja Raspopovic , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Pedja Raspopovic , Anatoli A. Bolotov
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： Channels are routed in an integrated circuit layout by reserving grid positions for buffers. Cell pins are identified at different y-coordinates to be connected by the channel. A determination is made as to the necessity of a jog between vertical segments, and if so, a y-coordinate is assigned to each such jog. An x-coordinate is assigned to each channel segment extending across the y-coordinates. Y-coordinates are assigned to buffers to be connected to the channel.
摘要翻译：通过为缓冲器保留网格位置，通道以集成电路布局布线。单元引脚在不同的y坐标处被识别，以通过通道连接。确定垂直段之间的点动的必要性，如果是，则对每个这样的点动分配y坐标。 x坐标被分配给延伸穿过y坐标的每个通道段。 Y坐标被分配给要连接到通道的缓冲器。

3. 发明授权

US06324674B2 Method and apparatus for parallel simultaneous global and detail routing 失效
标题翻译：并行同时全局和细节路由的方法和装置
公开(公告)号：US06324674B2
公开(公告)日：2001-11-27
申请号：US09062309
申请日：1998-04-17
申请人： Alexander E. Andreev , Elyar E. Gasanov , Ranko Scepanovic , Pedja Raspopovic
发明人： Alexander E. Andreev , Elyar E. Gasanov , Ranko Scepanovic , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A method for routing nets in an integrated circuit design, said method comprising the steps of dividing the integrated circuit design with lines in a first direction and lines in a second direction, forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction, routing nets as a function of said routing graph with parallel processors operating substantially simultaneously, determining the relative wire congestion among different areas in the integrated circuit design, and rerouting nets passing though areas with a relatively high wire congestion.
摘要翻译：一种用于在集成电路设计中布线网络的方法，所述方法包括以下步骤：将集成电路设计与沿第一方向和第二方向的线分开，形成具有顶点和边缘的路由图，其中顶点对应于第一方向上的线在第二方向上交叉线，将并行网络作为所述路由图的函数，并行处理器基本上同时运行，确定集成电路设计中的不同区域之间的相对电线拥塞，以及重新路由通过区域的网络电线拥塞比较高

4. 发明授权

US06154874A Memory-saving method and apparatus for partitioning high fanout nets 失效
标题翻译：用于分割高扇出网络的存储器保存方法和装置
公开(公告)号：US06154874A
公开(公告)日：2000-11-28
申请号：US62219
申请日：1998-04-17
申请人： Ranko Scepanovic , Alexander E. Andreev , Pedja Raspopovic
发明人： Ranko Scepanovic , Alexander E. Andreev , Pedja Raspopovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An object of the present invention is to provide for a method and apparatus to partition high fanout nets into smaller subnets. Said method includes the steps of identifying elementary pairs of pins in the net, each such elementary pair defining a line; eliminating lines such that a planar graph is formed; eliminating further lines such that a spanning tree is formed, said spanning tree connecting each pin in the net; identifying basic elements, each basic element forming a portion of said spanning tree; and constructing a connected cover for said net, said connected cover comprising a plurality of said basic elements. Said elementary pairs are identified by determining for each pin in said net a relative x-coordinate and a relative y-coordinate, constructing for each pin a combined binary coordinate as a function of the pin's relative x-coordinate and relative y-coordinate, ordering the pins in accordance with their respective combined binary coordinates, iteratively combining the pins until one pin remains, and iteratively expanding the pins.
摘要翻译：本发明的目的是提供一种将高扇出网分成较小子网的方法和装置。所述方法包括以下步骤：识别网中的基本对引脚，每个这样的基本对定义一条线; 消除形成平面图形的线条; 消除形成生成树的更多的线，所述生成树连接网中的每个引脚; 识别基本元素，形成所述生成树的一部分的每个基本元素; 以及构建所述网的连接的盖，所述连接的盖包括多个所述基本元件。通过确定所述网中的每个针的相对x坐标和相对的y坐标来识别所述基本对，所述相对的x坐标和相对的y坐标构成了作为销的相对x坐标和相对y坐标的函数的组合二进制坐标根据它们各自组合的二进制坐标的引脚，迭代地组合引脚直到保持一个引脚，并且迭代地扩展引脚。

5. 发明授权

US06247167B1 Method and apparatus for parallel Steiner tree routing 失效
标题翻译：并行Steiner树路由的方法和装置
公开(公告)号：US06247167B1
公开(公告)日：2001-06-12
申请号：US09062432
申请日：1998-04-17
申请人： Pedja Raspopovic , Ranko Scepanovic , Alexander E. Andreev
发明人： Pedja Raspopovic , Ranko Scepanovic , Alexander E. Andreev
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： The present invention provides for a method and apparatus to partition high fanout nets into smaller subnets. Said method includes the steps of identifying elementary pairs of pins in the net, each such elementary pair defining a line; eliminating lines such that a planar graph is formed; eliminating further lines such that a spanning tree is formed, said spanning tree connecting each pin in the net; identifying basic elements, each basic element forming a portion of said spanning tree; and constructing a connected cover for said net, said connected cover comprising a plurality of said basic elements.
摘要翻译：本发明提供了一种将高扇出网分成较小子网的方法和装置。所述方法包括以下步骤：识别网中的基本对引脚，每个这样的基本对定义一条线; 消除形成平面图形的线条; 消除形成生成树的更多的线，所述生成树连接网中的每个引脚; 识别基本元素，形成所述生成树的一部分的每个基本元素; 以及构建所述网的连接的盖，所述连接的盖包括多个所述基本元件。

6. 发明授权

US06175950B1 Method and apparatus for hierarchical global routing descend 失效
标题翻译：分级全局路由下降的方法和装置
公开(公告)号：US06175950B1
公开(公告)日：2001-01-16
申请号：US09062217
申请日：1998-04-17
申请人： Ranko Scepanovic , Alexander E. Andreev , Elyar E. Gasanov , Pedja Raspopovic
发明人： Ranko Scepanovic , Alexander E. Andreev , Elyar E. Gasanov , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： Net routing is optimized in an integrated circuit device by dividing an integrated circuit design with a first group of substantially parallel lines in a first direction and with a group of substantially parallel lines in a second direction, with the second direction being substantially perpendicular to the first direction. A first routing graph is formed with vertices corresponding to locations where lines in the first direction and lines in the second direction cross, and nets are globally routed as a function of the first routing graph. The integrated circuit design is further subdivided with a second group of substantially parallel lines in the first direction, and a second routing graph is formed with vertices corresponding to locations where lines in the first and second groups of substantially parallel lines in the first direction cross lines in the group of substantially parallel lines in the second direction. For a net globally routed using the first routing graph, a first local net is formed in a first fragment of the second routing graph, and the first local net is rerouted within the first fragment by computing edge penalty values for edges in the first fragment and rerouting the first local net as a function of the edge penalty values.
摘要翻译：通过将集成电路设计与第一方向上的第一组基本上平行的线分隔开并且在第二方向上与一组基本上平行的线分开，使得第二方向基本上垂直于第一方向方向。第一路由图形成为与第一方向上的线和第二方向上的线交叉的位置相对应的顶点，并且网络作为第一路由图的函数被全局路由。集成电路设计在第一方向上被进一步细分为第二组基本上平行的线，并且第二路由图形成为与第一方向交叉线上的基本上平行的第一组和第二组中的线对应的顶点在第二方向上基本平行的线组。对于使用第一路由图全局路由的网络，在第二路由图的第一片段中形成第一本地网，并且通过计算第一片段中的边缘的边缘惩罚值，在第一片段内重新路由第一本地网，作为边缘惩罚值的函数重新路由第一个本地网络。

7. 发明授权

US06230306B1 Method and apparatus for minimization of process defects while routing 失效
标题翻译：在路由时最小化过程缺陷的方法和装置
公开(公告)号：US06230306B1
公开(公告)日：2001-05-08
申请号：US09062310
申请日：1998-04-17
申请人： Pedja Raspopovic , Ranko Scepanovic , Alexander E. Andreev
发明人： Pedja Raspopovic , Ranko Scepanovic , Alexander E. Andreev
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A method for optimizing the routing of nets in an integrated circuit device, said method comprising the steps of dividing an integrated circuit design with lines in a first direction and lines in a second direction, wherein said first direction is substantially orthogonal to said second direction, forming a routing graph with vertices corresponding to locations where lines in said first direction and lines in said second direction cross and edges connect vertices, for each edge in a plurality of edges in said routing graph, computing an individual edge occupancy value, for an edge in said plurality of edges, computing a penalty value as a function of the individual edge occupancy value of a different edge, and routing a net as a function of said penalty value.
摘要翻译：一种用于优化集成电路器件中网络布线的方法，所述方法包括以下步骤：将集成电路设计与沿第一方向的线和第二方向的线分开，其中所述第一方向基本上与所述第二方向正交，形成具有对应于所述第一方向上的线和所述第二方向上的线交叉并且边缘连接顶点的位置的顶点的路线图，对于所述路线图中的多个边缘中的每个边缘，计算边缘的边缘占用值在所述多个边缘中，计算作为不同边缘的各个边缘占用值的函数的惩罚值，并且将网络作为所述惩罚值的函数进行路由。

8. 发明授权

US06289495B1 Method and apparatus for local optimization of the global routing 失效
标题翻译：用于局部优化全局路由的方法和装置
公开(公告)号：US06289495B1
公开(公告)日：2001-09-11
申请号：US09062205
申请日：1998-04-17
申请人： Pedja Raspopovic , Ranko Scepanovic , Alexander E. Andreev
发明人： Pedja Raspopovic , Ranko Scepanovic , Alexander E. Andreev
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A method for routing nets in an integrated circuit design, said method comprising the steps of forming a routing graph for an integrated circuit design, said routing graph have edges in a first direction and edges in a second direction, globally routing said integrated circuit design in accordance with said routing graph, dividing the routing graph into strips, for each strip in the routing graph, generating a general task for optimizing the routing in the strip, solving general tasks in parallel by assigning different processors different strips to process.
摘要翻译：一种用于在集成电路设计中路由网络的方法，所述方法包括以下步骤：形成用于集成电路设计的路由图，所述路由图具有沿第一方向的边缘和沿第二方向的边缘，将所述集成电路设计全局地路由根据所述路由图，将路由图划分成条，对于路由图中的每个条，生成用于优化条带中的路由的一般任务，通过分配不同的处理器来处理不同的条来并行地解决一般任务。

9. 发明授权

US06260183B1 Method and apparatus for coarse global routing 失效
标题翻译：粗略全局路由的方法和装置
公开(公告)号：US06260183B1
公开(公告)日：2001-07-10
申请号：US09062246
申请日：1998-04-17
申请人： Pedja Raspopovic , Ranko Scepanovic , Alexander E. Andreev
发明人： Pedja Raspopovic , Ranko Scepanovic , Alexander E. Andreev
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： Nets are routed on an integrated circuit device by dividing a portion of the integrated circuit device into a first group of tiles. A first routing graph is then formed as a function of the first group of tiles and nets are routed as a function of the first routing graph. A new group of tiles is formed by dividing the tiles of the first group of tiles, a new routing graph is formed as a function of the new group of tiles, and nets are rerouted as a function of the new routing graph. The steps of the preceding sentence are then repeated and each time a new group of tiles is formed, the tiles are divided in a same first dimension, resulting in tiles have progressively smaller lengths in that first dimension, while the size of the tiles in a second dimension does not change.
摘要翻译：网络通过将集成电路设备的一部分划分成第一组瓦片而布线在集成电路设备上。然后形成第一路由图作为第一组瓦片的函数，并且网络根据第一路由图被路由。通过划分第一组瓦片的瓦片形成新的瓦片组，作为新的瓦片组的函数形成新的路线图，并且网络被重新路由为新路线图的函数。然后重复前一句的步骤，并且每次形成新的瓦片组时，瓦片被划分成相同的第一维度，导致瓦片在该第一维度上具有逐渐更小的长度，而在一个第二维不变。

10. 发明授权

US06253363B1 Net routing using basis element decomposition 失效
标题翻译：网络路由使用基元分解
公开(公告)号：US06253363B1
公开(公告)日：2001-06-26
申请号：US09062218
申请日：1998-04-17
申请人： Elyar E. Gasanov , Ranko Scepanovic , Pedja Raspopovic , Alexander E. Andreev
发明人： Elyar E. Gasanov , Ranko Scepanovic , Pedja Raspopovic , Alexander E. Andreev
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A method for routing a net on an integrated circuit device, said method comprising the steps of creating a list of basis elements of the net, said basis elements being defined by a predetermined size limitation, determining a complexity value for each basis element as a function of the distance between pins in the basis element, forming a hypertree for the net as a function of complexity values of basis elements so determined, and routing the net as a function of the hypertree.
摘要翻译：一种用于在集成电路设备上路由网络的方法，所述方法包括以下步骤：创建网络的基本元素的列表，所述基本元素由预定大小限制定义，将每个基元元素的复杂度值确定为函数在基元中的引脚之间的距离，形成网的强度作为如此确定的基本元素的复杂度的函数，并且将网作为强调函数来布线。

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