专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07575958B2 Programmable fuse with silicon germanium 有权
标题翻译：可编程熔丝与硅锗
公开(公告)号：US07575958B2
公开(公告)日：2009-08-18
申请号：US11247479
申请日：2005-10-11
申请人： Alexander B. Hoefler , Marius K. Orlowski
发明人： Alexander B. Hoefler , Marius K. Orlowski
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A programmable fuse and method of formation utilizing a layer of silicon germanium (SiGe) (e.g. monocrystalline) as a thermal insulator to contain heat generated during programming. The programmable fuse, in some examples, may be devoid of any dielectric materials between a conductive layer and a substrate. In one example, the conductive layer serves as programmable material, that in a low impedance state, electrically couples conductive structures. A programming current is applied to the programmable material to modify the programmable material to place the fuse in a high impedance state.
摘要翻译：一种可编程保险丝和利用硅锗层（SiGe）（例如单晶）作为热绝缘体的层的形成方法，以包含编程期间产生的热。在一些示例中，可编程熔丝可以在导电层和衬底之间没有任何介电材料。在一个示例中，导电层用作可编程材料，其在低阻抗状态下电耦合导电结构。将编程电流施加到可编程材料以修改可编程材料以将熔丝置于高阻抗状态。

22. 发明授权

US07560965B2 Scannable flip-flop with non-volatile storage element and method 有权
标题翻译：具有非易失性存储元件和方法的可扫描触发器
公开(公告)号：US07560965B2
公开(公告)日：2009-07-14
申请号：US11741920
申请日：2007-04-30
申请人： Jeffrey W. Waldrip , Alexander B. Hoefler
发明人： Jeffrey W. Waldrip , Alexander B. Hoefler
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： G01R31/318541
摘要： A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for providing an output data signal. A non-volatile storage element stores a predetermined value. The non-volatile storage element has an output coupled to the first input of the slave latch. The output data signal corresponds to one of either the input data signal or the predetermined value stored by the non-volatile storage element in response to a control signal.
摘要翻译：电路具有主锁存器，具有用于接收输入数据信号的输入端和输出端。从锁存器具有耦合到主锁存器的输出的第一输入端和用于提供输出数据信号的输出端。非易失性存储元件存储预定值。非易失性存储元件具有耦合到从锁存器的第一输入的输出。输出数据信号响应于控制信号对应于输入数据信号或由非易失性存储元件存储的预定值之一。

23. 发明申请

US20080212388A1 INTEGRATED CIRCUIT FUSE ARRAY 审中-公开
标题翻译：集成电路保险丝阵列
公开(公告)号：US20080212388A1
公开(公告)日：2008-09-04
申请号：US11681424
申请日：2007-03-02
申请人： Alexander B. Hoefler
发明人： Alexander B. Hoefler
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18
摘要： The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses.
摘要翻译：这里描述的熔丝阵列是非常紧凑的，由于其交叉点架构而使用很少的半导体区域。所公开的交叉点架构减少了必须通过每个位单元水平或垂直运行的导体的数量。结果，每个位单元所需的面积显着减小。在一个实施例中，使用各种字线和位线上的所选择的一组电压来对保险丝编程以产生具有更紧密的阻抗分布的编程保险丝。类似地，使用各种字线和位线上的一组选定的电压来读取保险丝。

24. 发明授权

US07206214B2 One time programmable memory and method of operation 有权
公开(公告)号：US07206214B2
公开(公告)日：2007-04-17
申请号：US11197814
申请日：2005-08-05
申请人： Alexander B. Hoefler , Gowrishankar L. Chindalore
发明人： Alexander B. Hoefler , Gowrishankar L. Chindalore
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18 , H01L27/112
摘要： A one time programmable (OTP) memory has two-bit cells for increasing density. Each cell has two select transistors and a programmable transistor in series between the two select transistors. The programmable transistor has two independent storage locations. One is between the gate and a first source/drain region and the second is between the gate and a second source/drain region. The storage locations are portions of the gate dielectric where the sources or drains overlap the gate and are independently programmed by selectively passing a programming current through them. The programming current is of sufficient magnitude and duration to permanently reduce the impedance by more than three orders of magnitude of the storage locations to be programmed. The programming current is limited in magnitude to avoid damage to other circuit elements and is preferably induced at least in part by applying a negative voltage to the gate of the programming transistor.

25. 发明授权

US07161822B2 Compact non-volatile memory array with reduced disturb 有权
标题翻译：紧凑型非易失性存储阵列，减少干扰
公开(公告)号：US07161822B2
公开(公告)日：2007-01-09
申请号：US11068625
申请日：2005-02-28
申请人： Alexander B. Hoefler
发明人： Alexander B. Hoefler
IPC分类号： G11C5/06
CPC分类号： H01L27/115 , G11C16/0433
摘要： A non-volatile memory (NVM) array is made of NVM cells that have a floating gate transistor and a select transistor in which the floating gate transistor requires only a single layer of polysilicon. Adjacent cells are arranged so that the floating gates are staggered rather than being in the same line. This results in being able to put the cells closer together because of the reduction of the significance of what is commonly called poly-to-poly spacing. In this case, the termination of one floating gate is not lined-up with the floating gate of the adjacent NVM cell in the same row. Adjacent memory cells in the same column are made to have different configurations from each other which results in the floating gates in adjacent columns not being aligned, thus avoiding the poly-to-poly spacing limitation.
摘要翻译：非易失性存储器（NVM）阵列由具有浮置栅极晶体管和选择晶体管的NVM单元制成，其中浮栅晶体管仅需要单层多晶硅。相邻的电池被布置成使得浮动栅极交错而不是在同一条线上。这导致能够将细胞更靠近在一起，因为通常称为多聚 - 间隔的意义的降低。在这种情况下，一个浮动栅极的端接不与相邻NVM单元的浮动栅极排列在同一行中。相同列中的相邻存储器单元被制成具有彼此不同的配置，这导致相邻列中的浮动栅极不对准，从而避免了多对多间隔限制。

26. 发明授权

US06791883B2 Program and erase in a thin film storage non-volatile memory 有权
标题翻译：在薄膜存储非易失性存储器中编程和擦除
公开(公告)号：US06791883B2
公开(公告)日：2004-09-14
申请号：US10178658
申请日：2002-06-24
申请人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
发明人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
IPC分类号： G11C1600
CPC分类号： G11C16/0466
摘要： A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.
摘要翻译：具有薄膜电介质存储元件的非易失性存储器通过热载流子注入（HCI）编程并通过隧道擦除。这种存储器的存储单元的典型结构是硅，氧化物，氮化物，氧化物和硅（SONOS）。热载波注入为SONOS提供相对快速的编程，而隧道提供擦除，避免了通常伴随热载流子注入进行编程的热孔擦除（HHE）类型擦除的困难。 HHE对电介质的破坏性更大，导致可靠性问题。 HHE还具有相对较窄的擦除区域，可能不完全匹配HCI编程的模式，从而导致不完整的擦除。隧道擦除有效地覆盖整个区域，所以不用担心不完全擦除。虽然隧道擦除比HHE慢，但擦除时间在系统操作中通常不如编程时间那么重要。

27. 发明授权

US06724032B2 Multi-bit non-volatile memory cell and method therefor 有权
标题翻译：多位非易失性存储单元及其方法
公开(公告)号：US06724032B2
公开(公告)日：2004-04-20
申请号：US10202697
申请日：2002-07-25
申请人： Gowrishankar L. Chindalore , James D. Burnett , Alexander B. Hoefler
发明人： Gowrishankar L. Chindalore , James D. Burnett , Alexander B. Hoefler
IPC分类号： H01L27108
CPC分类号： H01L27/11568 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L29/7782 , H01L29/7923
摘要： A non-volatile multiple bit memory (10, 50) has electrically isolated storage elements (17, 21, 78, 80) that overlie a channel region having a central area (24, 94) with high impurity concentration. A planar gate (30, 84) overlies the storage elements. The high impurity concentration may be formed by a centrally located region (24) or by two peripheral regions (70, 72) having lower impurity concentration than the central portion of the channel. During a read or program operation, the channel area of high impurity concentration effectively controls a channel depletion region to enhance reading or programming of stored data bits. During a hot carrier program operation, the channel area of high impurity concentration enhances the programming efficiency by decreasing leakage currents in a memory array.
摘要翻译：非易失性多位存储器（10,50）具有覆盖在具有高杂质浓度的中心区域（24,94）的沟道区域上的电隔离存储元件（17,21,78,80）。平面栅极（30,84）覆盖存储元件。高杂质浓度可以由中心定位的区域（24）或具有比通道中心部分低的杂质浓度的两个外围区域（70,72）形成。在读取或编程操作期间，高杂质浓度的沟道区域有效地控制沟道耗尽区域以增强对存储的数据位的读取或编程。在热载波编程操作期间，高杂质浓度的沟道区域通过减少存储器阵列中的漏电流来提高编程效率。

28. 发明授权

US06713812B1 Non-volatile memory device having an anti-punch through (APT) region 有权
标题翻译：具有抗冲穿（APT）区域的非易失性存储器件
公开(公告)号：US06713812B1
公开(公告)日：2004-03-30
申请号：US10267199
申请日：2002-10-09
申请人： Alexander B. Hoefler , Gowrishankar L. Chindalore , Paul A. Ingersoll , Craig T. Swift
发明人： Alexander B. Hoefler , Gowrishankar L. Chindalore , Paul A. Ingersoll , Craig T. Swift
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L27/11521 , H01L29/105 , H01L29/66833 , H01L29/792
摘要： A memory device (70) that uses a non-volatile storage element (38), such as nitride, has reduced read disturb, which is the problem of tending to increase the threshold voltage of a memory device (70) during a read. To reduce this effect, the memory device (70) uses a counterdoped channel (86) to lower the natural threshold voltage of the device (70). This counterdoping can even be of sufficient dosage to reverse the conductivity type of the channel (86) and causing a negative natural threshold voltage. This allows for a lower gate voltage during read to reduce the adverse effect of performing a read. An anti-punch through (ATP) region (74) below the channel (86) allows for the lightly doped or reversed conductivity type channel (86) to avoid short channel leakage. A halo implant (46) on the drain side (54, 53) assists in hot carrier injection (HCI) so that the HCI is effective even though the channel (86) is lightly doped or of reversed conductivity type.
摘要翻译：使用诸如氮化物的非易失性存储元件（38）的存储器件（70）具有减少的读取干扰，这是读取期间倾向于增加存储器件（70）的阈值电压的问题。为了减少这种影响，存储装置（70）使用反向通道（86）来降低装置（70）的自然阈值电压。这种反渗透甚至可以具有足够的剂量来反转通道（86）的导电类型并导致负的自然阈值电压。这在读取期间允许较低的栅极电压以减少执行读取的不利影响。在沟道（86）下方的抗穿透（ATP）区域（74）允许轻掺杂或反向导电型通道（86）避免短沟道泄漏。漏极侧（54,53）上的卤素注入（46）有助于热载流子注入（HCI），使得尽管通道（86）被轻掺杂或反向导电类型，HCI也是有效的。

29. 发明申请

US20160027529A1 Address Fault Detection Circuit 有权
标题翻译：地址故障检测电路
公开(公告)号：US20160027529A1
公开(公告)日：2016-01-28
申请号：US14339049
申请日：2014-07-23
申请人： Alexander B. Hoefler , Scott I. Remington , Shayan Zhang
发明人： Alexander B. Hoefler , Scott I. Remington , Shayan Zhang
IPC分类号： G11C29/02 , G11C11/418
CPC分类号： G11C29/785 , G11C8/08 , G11C11/408 , G11C11/4087 , G11C11/41 , G11C11/418 , G11C29/024 , G11C29/808 , G11C2029/1202
摘要： A semiconductor memory device and method of operation are provided for a multi-bank memory array (100) with an address fault detector circuit (24, 28) connected to split word lines (WLn-WLm) across multiple banks, where the address fault detector circuit includes at least a first MOSFET transistor (51-54) connected to each word line for detecting an error-free operation mode and a plurality of different transient address faults including a “no word line select,” “false word line select,” and “multiple word line select” failure mode at one of the first and second memory banks. In selected embodiments, the address fault detector provides resistive coupling (33-40) between split word lines across multiple banks to create interaction or contention between split word lines to create a unique voltage level on a fault detection bit line during an address fault depending on the fault type.
摘要翻译：提供一种半导体存储器件和操作方法，用于具有连接到多个存储体上的分割字线（WLn-WLm）的地址故障检测器电路（24,28）的多存储体存储器阵列（100），其中地址故障检测器电路至少包括连接到每个字线的第一MOSFET晶体管（51-54），用于检测无错误操作模式和多个不同的瞬态地址故障，包括“无字线选择”，“假字线选择” 和第一和第二存储体之一的“多字线选择”故障模式。在选择的实施例中，地址故障检测器在多个分组之间的分离字线之间提供电阻耦合（33-40），以产生分离字线之间的相互作用或竞争，以在地址故障期间根据故障检测位线创建唯一的电压电平，这取决于故障类型。

30. 发明授权

US09117534B2 Fuse circuit with test mode 有权
标题翻译：保险丝电路具有测试模式
公开(公告)号：US09117534B2
公开(公告)日：2015-08-25
申请号：US14161927
申请日：2014-01-23
申请人： Alexander B. Hoefler
发明人： Alexander B. Hoefler
IPC分类号： G11C17/16 , G11C29/00
CPC分类号： G11C17/16 , G11C17/18 , G11C29/00 , G11C29/027
摘要： During a program operation of a fuse cell of a fuse circuit, all of a group of select transistors of a fuse cell are made conductive to program the fuse cell. During a test operation of a fuse cell of the fuse circuit, less than all of the group of select transistors are made conductive so that current less than a programming current flows through the fuse cell.
摘要翻译：在保险丝电路的熔丝单元的编程操作期间，使熔丝单元的一组选择晶体管导通以对熔丝单元进行编程。在保险丝电路的熔丝单元的测试操作期间，小于全部选择晶体管的组导通，使得小于编程电流的电流流过熔丝单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式