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211. 发明申请

US20080248626A1 SHALLOW TRENCH ISOLATION SELF-ALIGNED TO TEMPLATED RECRYSTALLIZATION BOUNDARY 审中-公开
标题翻译： SHOWOW TRENCH ISOLATION自对准至模拟重构边界
公开(公告)号：US20080248626A1
公开(公告)日：2008-10-09
申请号：US11697102
申请日：2007-04-05
申请人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
发明人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
IPC分类号： H01L21/762
CPC分类号： H01L21/26506 , H01L21/02667 , H01L21/187 , H01L21/76224
摘要： A hybrid orientation direct-semiconductor-bond (DSB) substrate with shallow trench isolation (STI) that is self-aligned to recrystallization boundaries is formed by patterning a hard mask layer for STI, a first amorphization implantation into openings in the hard mask layer, lithographic patterning of portions of a top semiconductor layer, a second amorphization implantation into exposed portions of the DSB substrate, recrystallization of the portions of the top semiconductor layer, and formation of STI utilizing the pattern in the hard mask layer. The edges of patterned photoresist for the second amorphization implantation are located within the openings in the patterned hard mask layer. Defective boundary regions formed underneath the openings in the hard mask layer are removed during the formation of STI to provide a leakage path free substrate. Due to elimination of a requirement for increased STI width, device density is increased compared to non-self-aligning process integration schemes.
摘要翻译：通过将STI的硬掩模层图案化，在硬掩模层的开口中进行第一非晶化注入，形成具有与重结晶边界自对准的浅沟槽隔离（STI）的混合取向直接半导体结合（DSB）顶部半导体层的部分的平版印刷图案化，第二非晶化注入到DSB衬底的暴露部分中，顶部半导体层的部分的再结晶，以及利用硬掩模层中的图案形成STI。用于第二非晶化注入的图案化光致抗蚀剂的边缘位于图案化的硬掩模层的开口内。在形成STI期间去除在硬掩模层中形成在开口下面的有缺陷的边界区域，以提供无泄漏路径的衬底。由于消除了对于增加的STI宽度的要求，与非自对准工艺集成方案相比，器件密度增加。

212. 发明申请

US20080185636A1 SEMICONDUCTOR STRUCTURE INCLUDING DOPED SILICON CARBON LINER LAYER AND METHOD FOR FABRICATION THEREOF 有权
标题翻译：包括掺杂硅碳板层的半导体结构及其制造方法
公开(公告)号：US20080185636A1
公开(公告)日：2008-08-07
申请号：US11672109
申请日：2007-02-07
申请人： Zhijiong Luo , Yaocheng Liu
发明人： Zhijiong Luo , Yaocheng Liu
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66545 , H01L29/1083 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： A semiconductor structure and related method for fabrication thereof includes a liner layer interposed between: (1) a pedestal shaped channel region within a semiconductor substrate; and (2) a source region and a drain region within a semiconductor material layer located upon the liner layer and further laterally separated from the pedestal shaped channel region within the semiconductor substrate. The liner layer comprises an active doped silicon carbon material. The semiconductor material layer may comprises a semiconductor material other than a silicon carbon semiconductor material. The semiconductor material layer may alternatively comprise a silicon carbon semiconductor material having an opposite dopant polarity and lower carbon content in comparison with the liner layer. Due to presence of the silicon carbon material, the liner layer inhibits dopant diffusion therefrom into the pedestal shaped channel region. Electrical performance of a field effect device that uses the pedestal shaped channel region is thus enhanced.
摘要翻译：半导体结构及其相关制造方法包括：衬垫层，介于：（1）半导体衬底内的基座形沟道区; 以及（2）位于衬里层上的半导体材料层内的源极区域和漏极区域，并且与半导体衬底内的基座形状沟道区域进一步横向分离。衬里层包括有源掺杂硅碳材料。半导体材料层可以包括除了硅碳半导体材料之外的半导体材料。可选地，半导体材料层可以包含与衬里层相比具有相反掺杂剂极性和较低碳含量的硅碳半导体材料。由于存在硅碳材料，衬垫层阻止掺杂剂从其中扩散到基座形沟道区域中。因此，增强了使用基座形状的通道区域的场效应装置的电气性能。

213. 发明申请

US20080173946A1 CMOS STRUCTURE INCLUDING DUAL METAL CONTAINING COMPOSITE GATES 有权
标题翻译： CMOS结构包括双金属复合栅
公开(公告)号：US20080173946A1
公开(公告)日：2008-07-24
申请号：US11625984
申请日：2007-01-23
申请人： Huilong Zhu , Dae-Gyu Park , Zhijiong Luo , Ying Zhang
发明人： Huilong Zhu , Dae-Gyu Park , Zhijiong Luo , Ying Zhang
IPC分类号： H01L27/00 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28088 , H01L27/092 , H01L29/4966 , H01L29/517 , H01L29/665
摘要： A CMOS structure and a method for fabricating the CMOS structure include a first transistor located within a first semiconductor substrate region having a first polarity. The first transistor includes a first gate electrode that includes a first metal containing material layer and a first silicon containing material layer located upon the first metal containing material layer. The CMOS structure also includes a second transistor located within a laterally separated second semiconductor substrate region having a second polarity that is different than the first polarity The second transistor includes a second gate electrode comprising a second metal containing material layer of a composition that is different than the first metal containing material layer, and a second silicon containing material layer located upon the second metal containing material layer. The first silicon containing material layer and the first semiconductor substrate region comprise different materials. The second silicon containing material layer and the second semiconductor substrate region also comprise different materials.
摘要翻译： CMOS结构和制造CMOS结构的方法包括位于具有第一极性的第一半导体衬底区域内的第一晶体管。第一晶体管包括第一栅电极，其包括第一含金属材料层和位于第一含金属材料层上的第一含硅材料层。 CMOS结构还包括位于横向分离的第二半导体衬底区域内的第二晶体管，其具有与第一极性不同的第二极性。第二晶体管包括第二栅电极，第二栅电极包括不同于第一含金属材料层和位于第二含金属材料层上的第二含硅材料层。第一含硅材料层和第一半导体衬底区域包括不同的材料。第二含硅材料层和第二半导体衬底区域也包括不同的材料。

214. 发明申请

US20080023752A1 BORON DOPED SiGe HALO FOR NFET TO CONTROL SHORT CHANNEL EFFECT 审中-公开
标题翻译： BORON DOPED SiGe HALO用于NFET控制短路通道效应
公开(公告)号：US20080023752A1
公开(公告)日：2008-01-31
申请号：US11460766
申请日：2006-07-28
申请人： Xiangdong Chen , Yung Fu Chong , Zhijiong Luo , Xinlin Wang , Haining S. Yang
发明人： Xiangdong Chen , Yung Fu Chong , Zhijiong Luo , Xinlin Wang , Haining S. Yang
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1045 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： An n-type field effect transistor (NFET) and methods of forming a halo for an NFET to control the short channel effect are disclosed. One method includes forming a gate over a silicon substrate; recessing the silicon adjacent to the gate; forming a halo by epitaxially growing boron in-situ doped silicon germanium (SiGe) in the recess; and epitaxially growing silicon over the silicon germanium. Alternatively, the halo can be formed by ion implanting boron into an embedded SiGe region within the silicon substrate. The resulting NFET includes a boron doped SiGe halo embedded within the silicon substrate. The embedded SiGe layer may be a relaxed layer without inserting strain in the channel. The high solid solubility of boron in SiGe and low diffusion rate allows formation of a halo that will maintain the sharp profile, which provides better control of the short channel effect and increasing control over NFET threshold voltage roll-off.
摘要翻译：公开了一种n型场效应晶体管（NFET）和用于形成用于NFET的光晕以控制短沟道效应的方法。一种方法包括在硅衬底上形成栅极; 凹陷与栅极相邻的硅; 通过在凹槽中外延生长硼原位掺杂硅锗（SiGe）来形成卤素; 并在硅锗上外延生长硅。或者，可以通过将硼离子注入到硅衬底内的嵌入的SiGe区域中来形成卤素。所得NFET包括嵌入在硅衬底内的硼掺杂SiGe光晕。嵌入的SiGe层可以是松弛层，而不会在通道中插入应变。硼在SiGe中的高固体溶解度和低扩散速率允许形成将保持尖锐轮廓的光晕，这提供了对短通道效应的更好控制并增加了对NFET阈值电压滚降的控制。

215. 发明申请

US20080006854A1 MOSFETS COMPRISING SOURCE/DRAIN REGIONS WITH SLANTED UPPER SURFACES, AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：包含上述上表面的源/漏区域的MOSFETs及其制造方法
公开(公告)号：US20080006854A1
公开(公告)日：2008-01-10
申请号：US11425542
申请日：2006-06-21
申请人： Zhijiong Luo , Yung F. Chong , Judson R. Holt , Zhao Lun , Huilong Zhu
发明人： Zhijiong Luo , Yung F. Chong , Judson R. Holt , Zhao Lun , Huilong Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7848 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate. The surface recesses preferable each has a bottom surface that is parallel to the substrate surface, which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces can be readily formed by crystallographic etching of the semiconductor substrate, followed by epitaxial growth of a semiconductor material.
摘要翻译：本发明涉及包括源极和漏极（S / D）区域的改进的金属氧化物半导体场效应晶体管（MOSFET）器件，其具有相对于衬底表面倾斜的上表面。这样的S / D区域可以包括在半导体衬底中的表面凹槽中外延生长的半导体结构。优选的表面凹部具有平行于基板表面的底表面，该底表面沿着第一组等效晶面中的一个取向，并且沿着第二不同组的等效晶面定向的一个或多个侧壁表面。 S / D区域的倾斜上表面用于改善沟道区域中的应力分布以及降低MOSFET的接触电阻。具有倾斜的上表面的这种S / D区域可以容易地通过半导体衬底的晶体蚀刻形成，随后半导体材料的外延生长。

216. 发明申请

US20070278583A1 GATE STRESS ENGINEERING FOR MOSFET 失效
标题翻译： MOSFET的栅极应力工程
公开(公告)号：US20070278583A1
公开(公告)日：2007-12-06
申请号：US11421510
申请日：2006-06-01
申请人： Zhijiong Luo , Yung Fu Chong , Huilong Zhu
发明人： Zhijiong Luo , Yung Fu Chong , Huilong Zhu
IPC分类号： H01L29/94
CPC分类号： H01L29/7833 , H01L29/66507 , H01L29/7845
摘要： Methods of stressing a channel of a transistor as a result of a material volume change in a gate structure and a related structure are disclosed. In one embodiment, a method includes forming a gate over the channel, wherein the gate includes several materials, such as layers of silicon materials and a conducting material layer, above a gate dielectric, and is surrounded by a spacer, and then providing a volume change to some of the materials in the gate so that a stress is induced in the channel as a result of the volume change. A gate structure for a MOSFET structure may include a layer of silicon material over a gate dielectric and a first silicide and second silicide over the silicon material, where the first silicide induces a stress in a channel of the device. The first and second suicides may be separated by a layer of silicon material or in contact with each other.
摘要翻译：公开了由于栅极结构的材料体积变化和相关结构而对晶体管的沟道施加应力的方法。在一个实施例中，一种方法包括在通道上形成栅极，其中栅极包括若干材料，例如硅材料层和导电材料层，在栅极电介质上方，并被间隔物环绕，然后提供体积改变为门中的一些材料，使得由于体积变化而在通道中引起应力。用于MOSFET结构的栅极结构可以包括在栅极电介质上的硅材料层，以及硅材料上的第一硅化物和第二硅化物，其中第一硅化物在器件的沟道中引起应力。第一和第二自杀剂可以被硅材料层分离或彼此接触。

217. 发明授权

US07279758B1 N-channel MOSFETs comprising dual stressors, and methods for forming the same 有权
标题翻译：包含双重应力的N沟道MOSFET及其形成方法
公开(公告)号：US07279758B1
公开(公告)日：2007-10-09
申请号：US11420047
申请日：2006-05-24
申请人： Jinghong H. Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
发明人： Jinghong H. Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/324 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S257/90
摘要： The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.
摘要翻译：本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。具体地说，n-FET包括均包含碳取代和拉伸应力单晶半导体的第一和第二图案应力层。第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

218. 发明申请

US20070138570A1 Formation of raised source/drain structures in NFET with embedded SiGe in PFET 有权
标题翻译：在PFET中嵌入SiGe的NFET中形成凸起的源极/漏极结构
公开(公告)号：US20070138570A1
公开(公告)日：2007-06-21
申请号：US11305584
申请日：2005-12-16
申请人： Yung Chong , Zhijiong Luo , Joo Kim , Judson Holt
发明人： Yung Chong , Zhijiong Luo , Joo Kim , Judson Holt
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.
摘要翻译：用于在NFET器件中形成凸起的源极/漏极结构并在PFET器件中形成嵌入的SiGe源极/漏极的结构和方法。我们在衬底上的NFET区域和PFET区域上的PFET栅极结构提供NFET栅极结构。我们提供与NFET栅极相邻的NFET SDE区域，并提供与PFET栅极相邻的PFET SDE区域。我们在邻近PFET第二间隔物的衬底中的PFET区域中形成凹陷。我们在凹槽中形成PFET嵌入式源极/漏极应力器。我们在NFET SDE区域上形成NFET S / D外延Si层，并在PFET嵌入式源极/漏极应力器上形成PFET S / D外延Si层。在随后的自对准硅化物步骤中，在PFET嵌入式源极/漏极应力源上的外延Si层被消耗，以在PFET嵌入式源极/漏极应力器上形成稳定和低电阻率的硅化物。我们通过将N型离子注入到与NFET栅极结构相邻的NFET区域中并进入NFET S / D应力Si层来形成NFET S / D注入，以形成升高的NFET源极/漏极。

219. 发明申请

US20070120154A1 FINFET STRUCTURE WITH MULTIPLY STRESSED GATE ELECTRODE 有权
标题翻译：具有多重应力门电极的FINFET结构
公开(公告)号：US20070120154A1
公开(公告)日：2007-05-31
申请号：US11164621
申请日：2005-11-30
申请人： Huilong Zhu , Zhijiong Luo
发明人： Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , H01L29/7842
摘要： A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and a second stress which is different than the first stress in a second region located further from the semiconductor fin. The semiconductor fin may also be aligned over a pedestal within the substrate. The semiconductor structure is annealed under desirable stress conditions to obtain an enhancement of semiconductor device performance.
摘要翻译：半导体结构及其制造方法包括位于衬底上的半导体鳍片。栅电极位于半导体鳍上方。栅电极在位于更靠近半导体鳍片的第一区域中具有第一应力，并且在远离半导体鳍片的第二区域中具有与第一应力不同的第二应力。半导体鳍片也可以对准衬底内的基座。半导体结构在期望的应力条件下退火以获得半导体器件性能的增强。

220. 发明授权

US07220662B2 Fully silicided field effect transistors 有权
标题翻译：全硅化场效应晶体管
公开(公告)号：US07220662B2
公开(公告)日：2007-05-22
申请号：US10905549
申请日：2005-01-10
申请人： Huilong Zhu , Sunfei Fang , Zhijiong Luo
发明人： Huilong Zhu , Sunfei Fang , Zhijiong Luo
IPC分类号： H01L21/3205
CPC分类号： H01L21/28097 , H01L21/28518 , H01L29/665 , H01L29/66545
摘要： Fully silicided planar field effect transistors are formed by avoiding the conventional chemical-mechanical polishing step to expose the silicon gate by etching the sidewalls down to the silicon; depositing a sacrificial oxide layer thinner on the top of gate and sidewall of spacers, but thicker over the S/D areas, etching the oxide to expose the top of stacked gate while protecting the S/D; recessing the silicon; stripping the oxide; depositing metal and annealing to form silicide over the gate and S/D.
摘要翻译：通过避免常规的化学机械抛光步骤通过将侧壁蚀刻到硅来暴露硅栅来形成全硅化平面场效应晶体管; 在间隔物的栅极和侧壁的顶部上沉积牺牲氧化物层，但在S / D区域上较厚，在保护S / D的同时蚀刻氧化物以露出堆叠栅极的顶部; 凹陷硅; 剥离氧化物; 沉积金属和退火以在栅极和S / D上形成硅化物。

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