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191. 发明授权

US6101563A Configuration access system 失效
标题翻译：配置接入系统
公开(公告)号：US6101563A
公开(公告)日：2000-08-08
申请号：US80031
申请日：1998-05-15
申请人： James Stephen Fields, Jr. , Guy Lynn Guthrie , Kenneth Alan Riek
发明人： James Stephen Fields, Jr. , Guy Lynn Guthrie , Kenneth Alan Riek
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/404
摘要： A methodology and implementing system are provided in which PCI system configuration data is made available to a host X86 system CPU through an intermediate PowerPC system. A bus converter circuit connected between the X86 bus and the PowerPC bus is effective to translate configuration addresses between the X86 and the PowerPC system. A PCI host bridge arrangement includes a primary PCI host bridge circuit and a plurality of secondary peer PCI host bridge circuits. The primary host bridge circuit is effective to process configuration data requests from the bus converter circuit which are directed to any of the secondary PCI host bridge circuits.
摘要翻译：提供了一种方法和实现系统，其中PCI系统配置数据通过中间PowerPC系统可用于主机X86系统CPU。连接在X86总线和PowerPC总线之间的总线转换器电路有效地在X86和PowerPC系统之间转换配置地址。 PCI主机桥机构包括主PCI主桥电路和多个次要对等PCI主桥电路。主主机桥电路有效地处理来自总线转换器电路的配置数据请求，其指向任何辅助PCI主机桥电路。

192. 发明授权

US5887144A Method and system for increasing the load and expansion capabilities of a bus through the use of in-line switches 失效
标题翻译：通过使用在线开关增加总线的负载和扩展能力的方法和系统
公开(公告)号：US5887144A
公开(公告)日：1999-03-23
申请号：US753116
申请日：1996-11-20
申请人： Guy Lynn Guthrie , Danny Marvin Neal , Richard Allen Kelley
发明人： Guy Lynn Guthrie , Danny Marvin Neal , Richard Allen Kelley
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4068
摘要： A method and system for expanding the load capabilities of a bus, such as the PCI bus. The system includes a primary bus, a plurality of secondary buses for connecting additional devices, a plurality of in-line switches, an arbiter, and control logic means. The plurality of in-line switches are used for connecting the primary bus to a corresponding one of the secondary buses, each one of the switches having an enable line for receiving a signal to enable or disable the switch. The arbiter is used for receiving requests for control of the primary bus, and for selecting one of the requests as a master for the control. The control logic means is used for enabling and disabling each of the switches, via the corresponding enable line, for connection or disconnection to the primary bus. The control logic means includes means, coupled to the arbiter, for gaining control over the primary bus prior to granting control to the master, and means for transmitting, during control over the primary bus, an enable signal to the switches corresponding to the secondary buses desired to be connected to the primary bus.
摘要翻译：一种用于扩展总线（如PCI总线）的负载能力的方法和系统。该系统包括主总线，用于连接附加设备的多个次总线，多个在线交换机，仲裁器和控制逻辑装置。多个在线开关用于将主总线连接到相应的一个辅助总线，每个开关具有用于接收信号以启用或禁用开关的使能线。仲裁器用于接收对主总线的控制请求，并用于选择其中一个请求作为控制主机。控制逻辑装置用于通过相应的使能线路使能和禁用每个开关用于连接或断开到主总线。控制逻辑装置包括耦合到仲裁器的装置，用于在向主机授予控制之前获得对主总线的控制，以及用于在对主总线进行控制期间向对应于辅助总线的开关发送使能信号的装置希望连接到主总线。

193. 发明授权

US5784576A Method and apparatus for adding and removing components of a data processing system without powering down 失效
标题翻译：用于在不掉电的情况下添加和移除数据处理系统的组件的方法和装置
公开(公告)号：US5784576A
公开(公告)日：1998-07-21
申请号：US741466
申请日：1996-10-31
申请人： Guy Lynn Guthrie , Danny Marvin Neal , Richard Allen Kelley
发明人： Guy Lynn Guthrie , Danny Marvin Neal , Richard Allen Kelley
IPC分类号： G06F13/40 , G06F13/00 , H03K17/693 , H04B1/44
CPC分类号： G06F13/4081
摘要： A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter, residing within a Host Bridge, Control & Power logic, and a plurality of in-line switch modules coupled to a bus. Each of the in-line switch modules provide isolation for load(s) connected thereto. The Host Bridge in combination with the Control & Power Logic implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).
摘要翻译：一种方法和系统，用于提供在不向系统供电的情况下添加或删除数据处理系统的组件的能力（“热插拔”）。该系统包括驻留在主机桥中的仲裁器，控制和电源逻辑以及耦合到总线的多个在线开关模块。每个在线开关模块为连接到其上的负载提供隔离。主机桥与控制和电源逻辑结合实施热插拔操作，例如将功率上升和下降到选定的插槽，并激活适当的在线开关以进行从负载（目标/控制）的通信主）。

194. 发明授权

US07533227B2 Method for priority scheduling and priority dispatching of store conditional operations in a store queue 有权
标题翻译：存储条件操作在存储队列中的优先级调度和优先级调度的方法
公开(公告)号：US07533227B2
公开(公告)日：2009-05-12
申请号：US12033441
申请日：2008-02-19
申请人： Guy Lynn Guthrie , Hugh Shen , Derek Edward Williams
发明人： Guy Lynn Guthrie , Hugh Shen , Derek Edward Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3824 , G06F9/3834 , G06F9/3851
摘要： A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.
摘要翻译：一种方法，系统和处理器芯片设计，用于减少完成LARX操作和接收相关联的STCX操作之间的延迟，以完成对高速缓存行的更新。向发行处理器的存储队列的每个条目提供附加跟踪位（优先级位）。每当在条目中放置STCX操作时，优先级位置位。在选择由仲裁逻辑发送的条目期间，仲裁逻辑扫描每个合格条目的优先级位的值。具有优先级位的条目在架构规则中的选择过程中被赋予优先级。然后在既定规则内尽可能早地选择该条目进行发送。

195. 发明授权

US07366844B2 Data processing system and method for handling castout collisions 有权
标题翻译：数据处理系统及其处理方法
公开(公告)号：US07366844B2
公开(公告)日：2008-04-29
申请号：US11054888
申请日：2005-02-10
申请人： Sanjeev Ghai , Guy Lynn Guthrie , John Thomas Hollaway, Jr.
发明人： Sanjeev Ghai , Guy Lynn Guthrie , John Thomas Hollaway, Jr.
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0831
摘要： A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and second castout operations, the memory controller performs a single update to the system memory.
摘要翻译：数据处理系统包括系统存储器的存储器控制器，其接收指定相同地址的第一和第二突变操作。响应于接收到所述第一和第二停顿操作，存储器控制器对系统存储器执行单次更新。

196. 发明授权

US06629210B1 Intelligent cache management mechanism via processor access sequence analysis 失效
标题翻译：智能缓存管理机制通过处理器访问序列分析
公开(公告)号：US06629210B1
公开(公告)日：2003-09-30
申请号：US09696888
申请日：2000-10-26
申请人： Ravi K. Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： Ravi K. Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： G06F1208
CPC分类号： G06F12/121 , G06F12/0815
摘要： In addition to an address tag, a coherency state and an LRU position, each cache directory entry includes historical processor access information for the corresponding cache line. The historical processor access information includes different subentries for each different processor which has accessed the corresponding cache line, with subentries being “pushed” along the stack when a new processor accesses the subject cache line. Each subentries contains the processor identifier for the corresponding processor which accessed the cache line, one or more opcodes identifying the operations which were performed by the processor, and timestamps associated with each opcode. This historical processor access information may then be utilized by the cache controller to influence victim selection, coherency state transitions, LRU state transitions, deallocation timing, and other cache management functions so that smaller caches are given the effectiveness of very large caches through more intelligent cache management.
摘要翻译：除了地址标签，一致性状态和LRU位置之外，每个高速缓存目录条目包括对应的高速缓存行的历史处理器访问信息。历史处理器访问信息包括已经访问相应的高速缓存行的每个不同处理器的不同子条目，当新处理器访问对象高速缓存行时，子条目沿“栈”被“推送”。每个子条目包含访问高速缓存行的相应处理器的处理器标识符，标识由处理器执行的操作的一个或多个操作码以及与每个操作码相关联的时间戳。然后，该历史处理器访问信息可以由高速缓存控制器利用来影响受害者选择，一致性状态转换，LRU状态转换，解除分配定时和其他高速缓存管理功能，使得通过更智能高速缓存向更小的高速缓存提供非常大的高速缓存的有效性管理。

197. 发明授权

US06493779B1 Method and system for interrupt handling using device pipelined packet transfers 失效
标题翻译：使用设备流水线分组传输的中断处理方法和系统
公开(公告)号：US06493779B1
公开(公告)日：2002-12-10
申请号：US09224111
申请日：1998-12-21
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.
摘要翻译：提供了一种实现流水线分组传输（PPT）的方法和装置。 PPT方法包括请求阶段和响应阶段。 PPT请求阶段涉及PPT请求主机，向PPT请求目标传送要求的中断的源地址，目的地地址和信息分组。 PPT响应阶段涉及PPT请求目标成为PPT响应主机，PPT响应主机向PPT请求主机传递目的地地址和包括中断处理信息的数据分组。流水线分组传输（PPT）根据预定的处理优先级进行排序，以提高性能并避免死锁。

198. 发明授权

US06418497B1 Method and system for interrupt handling using system pipelined packet transfers 失效
标题翻译：使用系统流水线分组传输的中断处理方法和系统
公开(公告)号：US06418497B1
公开(公告)日：2002-07-09
申请号：US09224119
申请日：1998-12-21
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F948
CPC分类号： G06F13/26
摘要： A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.
摘要翻译：提供了一种实现流水线分组传输（PPT）的方法和装置。 PPT方法包括请求阶段和响应阶段。 PPT请求阶段涉及PPT请求主机，向PPT请求目标传送要求的中断的源地址，目的地地址和信息分组。 PPT响应阶段涉及PPT请求目标成为PPT响应主机，PPT响应主机向PPT请求主机传递目的地地址和包括中断处理信息的数据分组。流水线分组传输（PPT）根据预定的处理优先级进行排序，以提高性能并避免死锁。

199. 发明授权

US6049841A Method and apparatus of selecting data transmission channels 失效
标题翻译：选择数据传输通道的方法和装置
公开(公告)号：US6049841A
公开(公告)日：2000-04-11
申请号：US85196
申请日：1998-05-27
申请人： James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： G06F13/30
CPC分类号： G06F13/30
摘要： An apparatus and method of assigning communication channels for transmitting data through a host bridge are provided. In a preferred embodiment, a determination is made as to whether data is being transmitted through any one of the channels. If data is not being transmitted through one the channels, that channel is designated as the transmission channel for the present data transaction. If data is being transmitted through all of the channels, a least most recently used channel is selected as the data transmission channel. If however, more than one channel is not transmitting data, the data transmission channel assignments are made among the idle channels from a lowest channel number (e.g., channel 0) to a highest channel number (e.g., channel 7) or vice versa.
摘要翻译：提供了一种通过主机桥分配用于发送数据的通信信道的装置和方法。在优选实施例中，确定数据是否通过任何一个信道发送。如果数据没有通过一个通道发送，则该信道被指定为用于当前数据事务的传输信道。如果通过所有信道发送数据，则选择最不常用的信道作为数据传输信道。然而，如果多于一个信道不发送数据，则从最低信道号（例如，信道0）到最高信道号（例如，信道7）在空闲信道之间进行数据传输信道分配，反之亦然。

200. 发明授权

US08352712B2 Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted 失效
标题翻译：方法和系统，用于将处理器发出的存储操作特定发送到存储队列，并发出全信号
公开(公告)号：US08352712B2
公开(公告)日：2013-01-08
申请号：US10840560
申请日：2004-05-06
申请人： Robert H. Bell, Jr. , Thomas Michael Capasso , Guy Lynn Guthrie , Hugh Shen , Jeffrey Adam Stuecheli
发明人： Robert H. Bell, Jr. , Thomas Michael Capasso , Guy Lynn Guthrie , Hugh Shen , Jeffrey Adam Stuecheli
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/3861
摘要： A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is full. The processor core is configured with speculative store logic that enables the processor core to continue issuing store operations while the store queue full signal is asserted. A copy of the speculatively issued store operation is placed within a speculative store buffer. The core waits for a signal from the store queue indicating the store operation was accepted into the store queue. When the speculatively-issued store operation is accepted within the store queue, the copy is discarded from the buffer. However, when the store operation is rejected, the speculative store logic re-issues the store operation ahead of normal store operations.
摘要翻译：一种方法和处理器芯片设计，用于使得处理器核心能够在核心接收到存储队列已满的指示之后继续向商店队列发送存储操作。处理器核心配置有推测存储逻辑，使得处理器核心能够在存储队列满信号被断言的同时继续发出存储操作。投机发行的存储操作的副本放置在推测性存储缓冲区内。核心等待来自存储队列的信号，指示存储操作被接受到存储队列中。当存储队列中接受推测发出的存储操作时，该副本将从缓冲区中丢弃。然而，当存储操作被拒绝时，推测存储逻辑在正常存储操作之前重新发布存储操作。

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