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1. 发明授权

US06704843B1 Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange 失效
标题翻译：增强型多处理器响应总线协议，实现高速缓存行内参考交换
公开(公告)号：US06704843B1
公开(公告)日：2004-03-09
申请号：US09696890
申请日：2000-10-26
申请人： Ravi K. Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： Ravi K. Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： G06F1208
CPC分类号： G06F12/0831
摘要： System bus snoopers within a multiprocessor system in which dynamic application sequence behavior information is maintained within cache directories append the dynamic application sequence behavior information for the target cache line to their snoop responses. The system controller, which may also maintain dynamic application sequence behavior information in a history directory, employs the available dynamic application sequence behavior information to append “hints” to the combined response, appends the concatenated dynamic application sequence behavior information to the combined response, or both. Either the hints or the dynamic application sequence behavior information may be employed by the bus master and other snoopers in cache management.
摘要翻译：在多处理器系统内的系统总线监听器，其中动态应用程序行为信息保存在高速缓存目录中，将目标缓存行的动态应用程序序列行为信息附加到其监听响应。也可以在历史目录中维护动态应用序列行为信息的系统控制器使用可用的动态应用序列行为信息来向组合响应附加“提示”，将连接的动态应用序列行为信息附加到组合响应，或都。在高速缓存管理中，总线主控和其他侦听器可以使用提示或动态应用序列行为信息。

2. 发明授权

US06631450B1 Symmetric multiprocessor address bus protocol with intra-cache line access information 有权
标题翻译：具有高速缓存行接入信息的对称多处理器地址总线协议
公开(公告)号：US06631450B1
公开(公告)日：2003-10-07
申请号：US09696889
申请日：2000-10-26
申请人： Ravi K. Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： Ravi K. Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： G06F1208
CPC分类号： G06F12/0831
摘要： System bus masters within a multiprocessor system in which dynamic application sequence behavior information is maintained within cache directories append the historical access information for the target cache line to their requests. Snoopers and/or the system controller, which may also maintain dynamic application sequence behavior information in a history directory, employ the appended access information for cache management.
摘要翻译：多处理器系统内的系统总线主机，其中动态应用程序行为信息保存在高速缓存目录中，将目标缓存行的历史访问信息追加到其请求中。也可以在历史目录中维护动态应用序列行为信息的侦听器和/或系统控制器采用附加的访问信息进行高速缓存管理。

3. 发明授权

US06629210B1 Intelligent cache management mechanism via processor access sequence analysis 失效
标题翻译：智能缓存管理机制通过处理器访问序列分析
公开(公告)号：US06629210B1
公开(公告)日：2003-09-30
申请号：US09696888
申请日：2000-10-26
申请人： Ravi K. Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： Ravi K. Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： G06F1208
CPC分类号： G06F12/121 , G06F12/0815
摘要： In addition to an address tag, a coherency state and an LRU position, each cache directory entry includes historical processor access information for the corresponding cache line. The historical processor access information includes different subentries for each different processor which has accessed the corresponding cache line, with subentries being “pushed” along the stack when a new processor accesses the subject cache line. Each subentries contains the processor identifier for the corresponding processor which accessed the cache line, one or more opcodes identifying the operations which were performed by the processor, and timestamps associated with each opcode. This historical processor access information may then be utilized by the cache controller to influence victim selection, coherency state transitions, LRU state transitions, deallocation timing, and other cache management functions so that smaller caches are given the effectiveness of very large caches through more intelligent cache management.
摘要翻译：除了地址标签，一致性状态和LRU位置之外，每个高速缓存目录条目包括对应的高速缓存行的历史处理器访问信息。历史处理器访问信息包括已经访问相应的高速缓存行的每个不同处理器的不同子条目，当新处理器访问对象高速缓存行时，子条目沿“栈”被“推送”。每个子条目包含访问高速缓存行的相应处理器的处理器标识符，标识由处理器执行的操作的一个或多个操作码以及与每个操作码相关联的时间戳。然后，该历史处理器访问信息可以由高速缓存控制器利用来影响受害者选择，一致性状态转换，LRU状态转换，解除分配定时和其他高速缓存管理功能，使得通过更智能高速缓存向更小的高速缓存提供非常大的高速缓存的有效性管理。

4. 发明授权

US06763433B1 High performance cache intervention mechanism for symmetric multiprocessor systems 失效
标题翻译：对称多处理器系统的高性能缓存干预机制
公开(公告)号：US06763433B1
公开(公告)日：2004-07-13
申请号：US09696910
申请日：2000-10-26
申请人： Ravi K. Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： Ravi K. Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： G06F1208
CPC分类号： G06F12/0831 , G06F12/0888
摘要： Upon snooping an operation in which an intervention is permitted or required, an intervening cache may elect to source only that portion of a requested cache line which is actually required, rather than the entire cache line. For example, if the intervening cache determines that the requesting cache would likely be required to invalidate the cache line soon after receipt, less than the full cache line may be sourced to the requesting cache. The requesting cache will not cache less than a full cache line, but may forward the received data to the processor supported by the requesting cache. Data bus bandwidth utilization may therefore be reduced. Additionally, the need to subsequently invalidate the cache line within the requesting cache is avoided, together with the possibility that the requesting cache will retry an operation requiring invalidation of the cache line.
摘要翻译：在窥探允许或需要干预的操作时，中间缓存可以选择仅仅提供实际需要的所请求的高速缓存行的那部分，而不是整个高速缓存行。例如，如果中间缓存确定可能需要请求的高速缓存在接收之后不久使高速缓存行无效，则小于全缓存行可以被提供给请求的高速缓存。请求的高速缓存不会缓存小于完整的高速缓存行，而是可以将接收到的数据转发到由请求的高速缓存支持的处理器。因此可以减少数据总线带宽利用率。此外，避免了随后使请求高速缓存中的高速缓存行无效的需要，以及请求高速缓存将重试需要高速缓存行无效的操作的可能性。

5. 发明授权

US06721856B1 Enhanced cache management mechanism via an intelligent system bus monitor 失效
标题翻译：通过智能系统总线监视器增强缓存管理机制
公开(公告)号：US06721856B1
公开(公告)日：2004-04-13
申请号：US09696887
申请日：2000-10-26
申请人： Ravi K. Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： Ravi K. Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： In addition to an address tag, a coherency state and an LRU position, each cache directory entry includes historical processor access, snoop operation, and system controller hint information for the corresponding cache line. Each entry includes different subentries for different processors which have accessed the corresponding cache line, with subentries containing a processor access sequence segment, a snoop operation sequence segment, and a system controller hint history segment. In addition to an address tag, within each system controller bus transaction sequence log directory entry is contained one or more opcodes identifying bus operations addressing the corresponding cache line, a processor identifier associated with each opcode, and a timestamp associated with each opcode. Also, along with each system bus transaction's opcode, the individual snoop responses that were received from one or more snoopers and the hint information that was provided to the requester and the snoopers may also be included. This information may then be utilized by the system controller to append hints to the combined snoop responses in order to influence cache controllers (the requestor(s), snoopers, or both) handling of victim selection, coherency state transitions, LRU state transitions, deallocation timing, and other cache management functions.
摘要翻译：除了地址标签，一致性状态和LRU位置之外，每个缓存目录条目包括对应的高速缓存行的历史处理器访问，窥探操作和系统控制器提示信息。每个条目包括不同处理器的不同子条目，这些子进程已访问相应的高速缓存行，子条目包含处理器访问序列段，侦听操作序列段和系统控制器提示历史段。除了地址标签之外，在每个系统控制器总线事务序列日志目录条目中还包含一个或多个操作码，用于标识寻址相应高速缓存行的总线操作，与每个操作码相关联的处理器标识符以及与每个操作码相关联的时间戳。此外，连同每个系统总线事务的操作码，也可以包括从一个或多个窥探者接收到的各个窥探响应以及提供给请求者和窥探者的提示信息。该信息随后可被系统控制器利用来附加到组合侦听响应的提示，以便影响高层控制器（请求者，窥探者或两者）处理受害者选择，相关性状态转换，LRU状态转换，释放定时和其他缓存管理功能。

6. 发明授权

US06601144B1 Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis 失效
标题翻译：通过snoop操作序列分析在对称多处理器系统中进行动态缓存管理
公开(公告)号：US06601144B1
公开(公告)日：2003-07-29
申请号：US09696912
申请日：2000-10-26
申请人： Ravi K. Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： Ravi K. Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： G06F1208
CPC分类号： G06F12/0831 , G06F12/121 , G06F12/123
摘要： In addition to an address tag, a coherency state and an LRU position, each cache directory entry includes historical processor access and snoop operation information for the corresponding cache line. The historical processor access and snoop operation information includes different subentries for each different processor which has accessed the corresponding cache line, with subentries being “pushed” along the stack when a new processor accesses the subject cache line. Each subentries contains the processor identifier for the corresponding-processor which accessed the cache line, a processor access history segment, and a snoop operation history segment. The processor access history segment contains one or more opcodes identifying the operations which were performed by the processor, and timestamps associated with each opcode. The snoop operation history segment contains, for each operation snooped by the respective processor, a processor identifier for the processor originating the snooped operation, an opcode identifying the snooped operation, and a timestamp identifying when the operation was snooped. This historical processor access and snoop operation information may then be utilized by the cache controller to influence victim selection, coherency state transitions, LRU state transitions, deallocation timing, and other cache management functions so that smaller caches are given the effectiveness of very large caches through more intelligent cache management.
摘要翻译：除了地址标签，一致性状态和LRU位置之外，每个高速缓存目录条目包括对应的高速缓存行的历史处理器访问和窥探操作信息。历史处理器访问和窥探操作信息包括已经访问相应的高速缓存行的每个不同处理器的不同子条目，当新的处理器访问对象高速缓存行时，子进程沿堆栈被“推送”。每个子条目包含访问高速缓存线的对应处理器的处理器标识符，处理器访问历史段和窥探操作历史段。处理器访问历史段包含标识由处理器执行的操作的一个或多个操作码以及与每个操作码相关联的时间戳。对于由相应处理器窥探的每个操作，窥探操作历史段包含用于发起被窥探操作的处理器的处理器标识符，识别被窥探操作的操作码，以及标识该操作何时被窥探的时间戳。然后，该历史处理器访问和窥探操作信息可被高速缓存控制器用于影响受害者选择，一致性状态转换，LRU状态转换，释放定时和其他高速缓存管理功能，使得较小的高速缓存被给予非常大的缓存的有效性更智能的缓存管理。

7. 发明授权

US06393528B1 Optimized cache allocation algorithm for multiple speculative requests 失效
标题翻译：针对多个推测请求的优化缓存分配算法
公开(公告)号：US06393528B1
公开(公告)日：2002-05-21
申请号：US09345714
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F12/127
摘要： A method of operating a computer system is disclosed in which an instruction having an explicit prefetch request is issued directly from an instruction sequence unit to a prefetch unit of a processing unit. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hiearchy and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value.
摘要翻译：公开了一种操作计算机系统的方法，其中具有显式预取请求的指令直接从指令序列单元发送到处理单元的预取单元。在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。如果从存储器hiearchy请求另一个预取值，并且确定高速缓存的高速缓存使用的预取限制已被满足，则包含先前预取值中的一个的高速缓存行中的高速缓存行被分配用于接收另一个预取值。

8. 发明授权

US07284097B2 Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes 失效
标题翻译：修改的无效缓存状态，以减少用于推测发出的全缓存行写入的缓存到高速缓存数据传输操作
公开(公告)号：US07284097B2
公开(公告)日：2007-10-16
申请号：US10675744
申请日：2003-09-30
申请人： John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie , Kenneth Lee Wright
发明人： John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie , Kenneth Lee Wright
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F12/0831 , G06F2212/507
摘要： A cache coherency protocol that includes a modified-invalid (Mi) state, which enables execution of a DMA Claim or DClaim operation to assign sole ownership of a cache line to a device that is going to overwrite the entire cache line without cache-to-cache data transfer. The protocol enables completion of speculatively-issued full cache line writes without requiring cache-to-cache transfer of data on the data bus during a preceding DMA Claim or DClaim operation. The modified-invalid (Mi) state assigns sole ownership of the cache line to an I/O device that has speculatively-issued a DMA Write or a processor that has speculatively-issued a DCBZ operation to overwrite the entire cache line, and the Mi state prevents data being sent to the cache line from another cache since the data will most probably be overwritten.
摘要翻译：包括修改无效（Mi）状态的高速缓存一致性协议，其使得能够执行DMA声明或DClaim操作以将高速缓存行的唯一所有权分配给要覆盖整个高速缓存行的设备，而不进行高速缓存 - 缓存数据传输。该协议允许完成推测发出的完整高速缓存行写入，而不需要在先前的DMA声明或DClaim操作期间在数据总线上缓存到高速缓存传输数据。修改无效（Mi）状态将高速缓存行的唯一所有权分配给推测性地发出DMA写入的I / O设备或者推测发出DCBZ操作以覆盖整个高速缓存行的处理器，并且将Mi 状态可防止将数据从另一个缓存发送到高速缓存行，因为数据最有可能被覆盖。

9. 发明授权

US06581139B1 Set-associative cache memory having asymmetric latency among sets 有权
标题翻译：集合中具有不对称延迟的集合关联高速缓存存储器
公开(公告)号：US06581139B1
公开(公告)日：2003-06-17
申请号：US09339411
申请日：1999-06-24
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0864
摘要： A set-associative cache memory having asymmetric latency among sets is disclosed. The cache memory has multiple congruence classes of cache lines. Each congruence class includes a number of sets organized in a set-associative manner. The cache memory further includes a means for accessing at least one of the sets faster than the remaining sets having an identical access latency.
摘要翻译：公开了一组在集合中具有非对称等待时间的组合高速缓冲存储器。高速缓存存储器具有多个一致的缓存行类。每个同余类包括以组合方式组织的多个集合。高速缓冲存储器还包括用于比具有相同访问延迟的其余集合更快地访问集合中的至少一个集合的装置。

10. 发明授权

US06510494B1 Time based mechanism for cached speculative data deallocation 失效
标题翻译：缓存的推测数据释放的基于时间的机制
公开(公告)号：US06510494B1
公开(公告)日：2003-01-21
申请号：US09345716
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
IPC分类号： G06F1208
CPC分类号： G06F9/3802 , G06F9/383 , G06F12/0862 , G06F12/0897
摘要： A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the pref etch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit.
摘要翻译：一种操作计算机系统的处理单元的方法，通过从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。本发明适用于作为操作数数据或指令的值。在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别存储子系统，并用pref蚀刻请求发送将预取值加载到处理单元的较低级缓存中的指示。本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联。

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