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11. 发明授权

US09859414B2 Semiconductor device 有权
公开(公告)号：US09859414B2
公开(公告)日：2018-01-02
申请号：US14774125
申请日：2014-03-31
申请人： Shindengen Electric Manufacturing Co., Ltd.
发明人： Takeshi Asada , Mizue Kitada , Takeshi Yamaguchi , Noriaki Suzuki
IPC分类号： H01L29/768 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/10
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0696 , H01L29/0865 , H01L29/1095 , H01L29/7802 , H01L29/7811
摘要： A semiconductor device includes a drift layer 20 of a first conductivity type, a base layer 30 of a second conductivity type that is disposed on the drift layer 20 and is connected to a source electrode 90, and a column layer 50 of a second conductivity type that is connected to the source electrode 90 and penetrates the base layer 30 to extend into the drift layer 20.

12. 发明授权

US09799690B2 Solid-state image pickup device 有权
公开(公告)号：US09799690B2
公开(公告)日：2017-10-24
申请号：US15272905
申请日：2016-09-22
申请人： Sony Corporation
发明人： Takayuki Ezaki , Teruo Hirayama
IPC分类号： H01L27/148 , H01L29/768 , H01L27/146 , H01L31/02 , H01L29/423
CPC分类号： H01L27/14612 , H01L27/14603 , H01L27/14621 , H01L27/14627 , H01L27/1463 , H01L27/1464 , H01L27/14643 , H01L27/14689 , H01L29/4236 , H01L31/02
摘要： A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.

13. 发明授权

US09684213B2 BOA liquid crystal panel and manufacturing method thereof 有权
公开(公告)号：US09684213B2
公开(公告)日：2017-06-20
申请号：US14423128
申请日：2015-02-06
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Chuan Wu
IPC分类号： G02F1/1362 , G02F1/1339 , G02F1/1341 , G02F1/1343 , G02F1/1368 , H01L27/12 , H01L29/768 , H01L29/786 , G02F1/1333
CPC分类号： G02F1/136209 , G02F1/13394 , G02F1/1341 , G02F1/134309 , G02F1/13439 , G02F1/1368 , G02F2001/133302 , G02F2001/13398 , G02F2201/121 , G02F2202/103 , G02F2202/104 , H01L27/1222 , H01L27/124 , H01L27/127 , H01L29/78669 , H01L29/78678
摘要： The present invention provides a BOA liquid crystal panel and a manufacturing method thereof. The BOA liquid crystal panel includes a first substrate, a second substrate opposite to the first substrate, a black matrix arranged in the first substrate, a thin-film transistor arranged on the black matrix, a color resist layer arranged on the second substrate, a common electrode layer arranged on the second substrate and the color resist layer, a photoresist spacer arranged on the common electrode layer and located between the first substrate and the second substrate, and a liquid crystal layer arranged between the first substrate and the second substrate. The present invention arranges the black matrix of the liquid crystal panel in a channel that is pre-formed in a substrate to make the film thickness of the liquid crystal panel uniform and improve the display performance of the liquid crystal panel.

14. 发明授权

US09613970B2 Semiconductor nonvolatile memory element 有权
公开(公告)号：US09613970B2
公开(公告)日：2017-04-04
申请号：US15013540
申请日：2016-02-02
申请人： SII Semiconductor Corporation
发明人： Hirofumi Harada , Shinjiro Kato
IPC分类号： H01L29/768 , H01L27/11521 , H01L21/762 , H01L29/66
CPC分类号： H01L27/11524 , H01L21/76202 , H01L27/11521 , H01L29/36 , H01L29/42324 , H01L29/66825 , H01L29/7833 , H01L29/788
摘要： A semiconductor nonvolatile memory element is used to form a constant current source in a semiconductor integrated circuit device. The semiconductor nonvolatile memory element includes a control gate electrode, a floating gate electrode, source/drain terminals, a thin first gate insulating film, and a second gate insulating film that is thick enough not to be broken down even when a voltage higher than an operating voltage of the semiconductor integrated circuit device is applied thereto, the first and second gate insulating films being formed below the control gate electrode. Thus, provided is a normally on type semiconductor nonvolatile memory element in which a threshold voltage can be regulated through injection of a large amount of charge with respect to the operating voltage from a drain terminal into the floating gate electrode via the second gate insulating film, and injected carriers do not leak in an operating voltage range.

15. 发明授权

US09559134B2 Deep trench spacing isolation for complementary metal-oxide-semiconductor (CMOS) image sensors 有权
标题翻译：互补金属氧化物半导体（CMOS）图像传感器的深沟槽间隔隔离
公开(公告)号：US09559134B2
公开(公告)日：2017-01-31
申请号：US14564196
申请日：2014-12-09
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Tai-I Yang , Jung-I Lin , Ta-Chun Lin , Tien-Lu Lin , Chen-Jong Wang
IPC分类号： H01L27/148 , H01L29/768 , H01L29/00 , H01L27/146 , H01L27/092 , H01L29/94 , H01L27/12
CPC分类号： H01L21/764 , H01L21/76224 , H01L21/76227 , H01L21/76289 , H01L21/7682 , H01L21/76834 , H01L21/823481 , H01L21/823878 , H01L27/0921 , H01L27/1203 , H01L27/14612 , H01L27/1463 , H01L27/14632 , H01L27/14643 , H01L27/14654 , H01L27/14689 , H01L29/945
摘要： An image sensor employing deep trench spacing isolation is provided. A plurality of pixel sensors is arranged over or within a semiconductor substrate. A trench is arranged in the semiconductor substrate around and between adjacent ones of the plurality of pixel sensors, and the trench has a gap located between sidewalls of the trench. A cap is arranged over or within the trench at a position overlying the gap. The cap seals the gap within the trench. A method of manufacturing the image sensor is also provided.
摘要翻译：提供了采用深沟槽间隔隔离的图像传感器。多个像素传感器布置在半导体衬底之上或之内。沟槽在多个像素传感器周围和相邻的像素传感器之间并且在半导体衬底中布置，并且沟槽在沟槽的侧壁之间具有间隙。在覆盖间隙的位置处，在沟槽之上或之内布置盖。盖子密封沟槽内的间隙。还提供了一种制造图像传感器的方法。

16. 发明授权

US09368592B2 Metal gate structure 有权
标题翻译：金属门结构
公开(公告)号：US09368592B2
公开(公告)日：2016-06-14
申请号：US14166283
申请日：2014-01-28
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Yi-Fang Li , Chun-Sheng Wu
IPC分类号： H01L27/148 , H01L29/768 , H01L29/49 , H01L29/66 , H01L29/51
CPC分类号： H01L29/4966 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L29/51 , H01L29/66545 , H01L29/66606 , H01L29/66636
摘要： The present disclosure provides a semiconductor structure, including a substrate, a metal gate, a dielectric layer, and an etch stop layer. The metal gate is positioned on the substrate and possesses a first surface. The dielectric layer surrounds the metal gate and possesses a second surface. The etch stop layer is in contact with both the first surface and the second surface. The first surface is higher than the second surface. The present disclosure also provides a method for manufacturing a semiconductor structure, including forming a dummy gate on a substrate; forming a second etch stop layer over the dummy gate; forming a dielectric layer over the dummy gate; replacing the dummy gate with a metal gate; etching back the dielectric layer to form a second surface of the dielectric layer lower than a first surface of the metal gate; and forming a first etch stop layer over the metal gate and the dielectric layer.
摘要翻译：本公开提供了一种包括衬底，金属栅极，电介质层和蚀刻停止层的半导体结构。金属栅极位于基板上并具有第一表面。电介质层围绕金属栅极并具有第二表面。蚀刻停止层与第一表面和第二表面都接触。第一表面高于第二表面。本公开还提供了一种用于制造半导体结构的方法，包括在衬底上形成虚拟栅极; 在所述虚拟栅极上形成第二蚀刻停止层; 在所述伪栅极上形成介电层; 用金属门代替虚拟门; 蚀刻所述电介质层以形成所述电介质层的比所述金属栅极的第一表面低的第二表面; 以及在所述金属栅极和所述介电层上形成第一蚀刻停止层。

17. 发明授权

US09246096B2 Atomic layer deposition of metal oxides for memory applications 有权
公开(公告)号：US09246096B2
公开(公告)日：2016-01-26
申请号：US14624295
申请日：2015-02-17
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Zhendong Hong , Vidyut Gopal , Imran Hashim , Randall J. Higuchi , Tim Minvielle , Hieu Pham , Takeshi Yamaguchi
IPC分类号： H01L29/768 , H01L29/40 , H01L21/8222 , H01L21/20 , H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2463 , H01L45/04 , H01L45/08 , H01L45/1233 , H01L45/1616
摘要： Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.

18. 发明授权

US09245910B2 Method for manufacturing board device 有权
标题翻译：板装置制造方法
公开(公告)号：US09245910B2
公开(公告)日：2016-01-26
申请号：US14547650
申请日：2014-11-19
申请人： Japan Display Inc.
发明人： Yasunori Fukumoto , Toshihide Jinnai , Koji Sato
IPC分类号： H01L21/77 , H01L27/12 , G02F1/1333 , G02F1/1343 , H01L29/768
CPC分类号： H01L27/1259 , G02F1/133345 , G02F1/134363 , H01L29/768
摘要： According to one embodiment, provided is an array substrate that can effectively prevent an oxide conductive film and a silicon nitride film on the oxide conductive film from peeling without deteriorating reliability. A method for manufacturing the array substrate includes a surface treatment step and a nitride film forming step. In the surface treatment step, by plasma discharge, the oxide conductive film is cleaned without being reduced, and surface layers of the insulating film layer not covered by the oxide conductive film and portions of the insulating film layer in the regions covered by the oxide conductive film are etched to form recesses leading to portions under the oxide conductive film. In the nitride film forming step, successively from the surface treatment step, the silicon nitride film is formed by plasma CVD so as to cover the recesses and the oxide conductive film.
摘要翻译：根据一个实施方式，提供了能够有效地防止氧化物导电膜上的氧化物导电膜和氮化硅膜剥离而不劣化可靠性的阵列基板。阵列基板的制造方法包括表面处理工序和氮化膜形成工序。在表面处理步骤中，通过等离子体放电，氧化物导电膜被清洁而不被还原，并且绝缘膜层的表面层未被氧化物导电膜覆盖，并且绝缘膜层的部分被氧化物导电覆盖的区域蚀刻以形成通向氧化物导电膜下方的部分的凹部。在氮化膜形成工序中，从表面处理工序开始，通过等离子体CVD形成氮化硅膜，以覆盖凹部和氧化物导电膜。

19. 发明授权

US09231007B2 Image sensors operable in global shutter mode and having small pixels with high well capacity 有权
标题翻译：图像传感器可在全局快门模式下工作，并且具有高容量的小像素
公开(公告)号：US09231007B2
公开(公告)日：2016-01-05
申请号：US14468186
申请日：2014-08-25
申请人： Semiconductor Components Industries, LLC
发明人： Jaroslav Hynecek
IPC分类号： H01L27/146 , H01L29/768 , H01L27/148 , H04N5/3745
CPC分类号： H01L27/14612 , H01L27/14614 , H01L27/1463 , H01L27/1464 , H01L27/14643 , H01L27/14654 , H04N5/37452
摘要： An image sensor operable in global shutter mode ma include small pixels with high charge storage capacity, low dark current, and no image lag. Storage capacity of a photodiode and a charge storage diode may be increased by placing a p+ type doped layer under the photodiode and the charge storage diode. The p+ type doped layer ma include an opening for allowing photo-generated charge carriers to flow from the silicon bulk to the charge storage well located near the surface of the photodiode. A compensating n− type doped implant may be formed in the opening. Image lag is prevented by placing a p− type doped region under the p+ type doped photodiode pinning layer and aligned with the opening. The p+ type doped layer may extend under the entire pixel array.
摘要翻译：可在全局快门模式下操作的图像传感器包括具有高电荷存储容量，低暗电流和无图像滞后的小像素。可以通过在光电二极管和电荷存储二极管的下方放置p +型掺杂层来增加光电二极管和电荷存储二极管的存储容量。 p +型掺杂层ma包括用于允许光电载流子从硅体流到位于光电二极管表面附近的电荷存储阱的开口。可以在开口中形成补偿型n型掺杂植入物。通过将p型掺杂区域放置在p +型掺杂光电二极管钉扎层下方并与开口对准来防止图像滞后。 p +型掺杂层可以在整个像素阵列下延伸。

20. 发明授权

US09202902B2 Semiconductor element and solid-state imaging device 有权
标题翻译：半导体元件和固态成像器件
公开(公告)号：US09202902B2
公开(公告)日：2015-12-01
申请号：US14419341
申请日：2013-08-01
申请人： National University Corporation Shizuoka University
发明人： Shoji Kawahito
IPC分类号： H01L27/00 , H01L29/768 , H01L27/148 , H01L27/146 , H04N5/369 , H04N5/372 , H04N5/374
CPC分类号： H01L29/76833 , H01L27/146 , H01L27/1461 , H01L27/14612 , H01L27/148 , H01L27/14806 , H01L27/14812 , H01L27/14818 , H01L27/14825 , H01L27/14831 , H01L27/14843 , H01L27/1485 , H04N5/369 , H04N5/372 , H04N5/374
摘要： A semiconductor element encompasses a charge-transfer path defined in a semiconductor region (34.35), configured to transfer signal charges, (b) a pair of first field-control electrodes (42a, 42b) laminated via an insulating film on the semiconductor region so as to sandwich the charge-transfer path in between, and a pair of second field-control electrodes (43a, 43b) arranged separately from and adjacently to the first field-control electrodes (42a, 42b). By applying field-control voltages differing from each other, to the first and second field-control electrodes (43a, 43b), a depleted potential in the charge-transfer path is changed, and a movement of the signal charges transferring in the semiconductor region is controlled. Because electric field can be made constant over a long distance along the charge-transfer direction, a semiconductor element and a solid-state imaging device, in which problems caused by interface defects and the like are avoided, can be provided.
摘要翻译：半导体元件包括限定在半导体区域（34.35）中的电荷传输路径，被配置为传送信号电荷，（b）经由半导体区域上的绝缘膜层压的一对第一场控制电极（42a，42b），从而将电荷转移路径夹在中间，以及与第一场控制电极（42a，42b）分开并相邻配置的一对第二场控制电极（43a，43b）。通过施加彼此不同的场控制电压到第一和第二场控制电极（43a，43b），电荷传输路径中的耗尽电位改变，并且在半导体区域中传输的信号电荷的移动被控制。由于可以沿着电荷转移方向使电场长距离恒定，所以可以提供避免由界面缺陷等引起的问题的半导体元件和固体摄像器件。

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