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11. 发明授权

US10790373B2 Semiconductor device and method of manufacturing same 有权
公开(公告)号：US10790373B2
公开(公告)日：2020-09-29
申请号：US16123216
申请日：2018-09-06
申请人： Fuji Electric Co., Ltd.
发明人： Makoto Utsumi , Yoshiyuki Sakai
IPC分类号： H01L29/45 , H01L21/8234 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78 , H01L29/417 , H01L29/40 , H01L29/66 , H01L29/745
摘要： A semiconductor device includes a first barrier film covering the main surface of the active region and the insulating film layer, the first barrier film having an ohmic contact hole that exposes a contact portion of the ohmic contact formation region within the window of the insulating film layer; a base contact layer filled into the ohmic contact hole and making ohmic contact with the contact portion of the ohmic contact formation region; a second barrier film made of titanium, covering the base contact layer and the first barrier film; and a third barrier film made of titanium oxide and titanium nitride, covering a surface of the second barrier film.

12. 发明申请

US20200058740A1 INSULATED-GATE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20200058740A1
公开(公告)日：2020-02-20
申请号：US16661925
申请日：2019-10-23
申请人： FUJI ELECTRIC CO., LTD.
发明人： Keiji Okumura
IPC分类号： H01L29/10 , H01L29/16 , H01L29/66 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/08 , H01L29/739 , H01L29/745
摘要： An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.

13. 发明申请

US20190259864A1 VERTICAL BIDIRECTIONAL INSULATED GATE TURN-OFF DEVICE 审中-公开
公开(公告)号：US20190259864A1
公开(公告)日：2019-08-22
申请号：US16278566
申请日：2019-02-18
申请人： Pakal Technologies, Inc.
发明人： Richard A. Blanchard , Vladimir Rodov
IPC分类号： H01L29/745 , H01L29/747
摘要： A vertical bidirectional insulated gate turn-off (IGTO) device includes a top half formed over a top surface of a substrate and a bottom half formed over the bottom surface of the substrate. A top electrode is formed over the top half, and a bottom electrode is formed over the bottom half. The layered structure forms vertical NPN and PNP transistors. Each half includes trenched gates. When a first polarity voltage is applied across the electrodes, one of the halves may be turned on by biasing its gates to conduct current between the top and bottom electrodes. When a voltage of an opposite polarity is applied across the electrodes, the other one of the halves may be turned on by biasing its gates to conduct current between the two electrodes. In one embodiment, biasing the gates increases the beta of the NPN transistor to turn on the device.

14. 发明授权

US10096681B2 Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) device cells 有权
公开(公告)号：US10096681B2
公开(公告)日：2018-10-09
申请号：US15595611
申请日：2017-05-15
申请人： General Electric Company
发明人： Alexander Viktorovich Bolotnikov , Peter Almern Losee
IPC分类号： H01L29/78 , H01L29/16 , H01L29/06 , H01L21/04 , H01L29/66 , H01L29/10 , H01L29/745 , H01L29/739 , H01L29/74
摘要： The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to disconnected or connected shielding regions that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a widest portion of the JFET region between adjacent device cells such that a distance between a shielding region and well regions surrounding device cell is less than a parallel JFET width between two adjacent device cells, while maintaining a channel region width and/or a JFET region density that is greater than that of a comparable conventional stripe device. As such, the disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

15. 发明授权

US09922864B2 Trench separation diffusion for high voltage device 有权
公开(公告)号：US09922864B2
公开(公告)日：2018-03-20
申请号：US15452592
申请日：2017-03-07
申请人： IXYS Corporation
发明人： Elmar Wisotzki , Christoph Koerber
IPC分类号： H01L29/76 , H01L21/761 , H01L21/763 , H01L21/762 , H01L21/223 , H01L29/08 , H01L29/745 , H01L29/06 , H01L21/78 , H01L29/74 , H01L29/739
CPC分类号： H01L21/761 , H01L21/223 , H01L21/76 , H01L21/762 , H01L21/76224 , H01L21/76229 , H01L21/76237 , H01L21/763 , H01L21/768 , H01L21/78 , H01L24/05 , H01L29/0619 , H01L29/0638 , H01L29/0646 , H01L29/0834 , H01L29/407 , H01L29/7395 , H01L29/74 , H01L29/745 , H01L2224/056 , H01L2924/1301 , H01L2924/00014
摘要： A manufacturable and economically viable edge termination structure allows a semiconductor device to withstand a very high reverse blocking voltage (for example, 8500 volts) without suffering breakdown. A P type peripheral aluminum diffusion region extends around the bottom periphery of a thick die. The peripheral aluminum diffusion region extends upward from the bottom surface of the die, extending into N- type bulk silicon. A deep peripheral trench extends around the upper periphery of the die. The deep trench extends from the topside of the die down toward the peripheral aluminum diffusion region. A P type sidewall doped region extends laterally inward from the inner sidewall of the trench, and extends laterally outward from the outer sidewall of the trench. The P type sidewall doped region joins with the P type peripheral aluminum diffusion region, thereby forming a separation edge diffusion structure that surrounds the active area of the die.

16. 发明申请

US20170256614A1 VERTICAL INSULATED GATE TURN-OFF THYRISTOR WITH INTERMEDIATE P+ LAYER IN P-BASE 有权
公开(公告)号：US20170256614A1
公开(公告)日：2017-09-07
申请号：US15448530
申请日：2017-03-02
申请人： Pakal Technologies, LLC
发明人： Hidenori Akiyama
IPC分类号： H01L29/10 , H01L29/423 , H01L29/74 , H01L29/745
CPC分类号： H01L29/102 , H01L29/0696 , H01L29/0839 , H01L29/41716 , H01L29/4236 , H01L29/66734 , H01L29/744 , H01L29/745 , H01L29/7455 , H01L29/7827 , H01L2924/1301 , H01L2924/1302 , H01L2924/13021 , H01L2924/13022
摘要： An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an p-layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. The p-well has an intermediate highly doped portion. When the gate regions are sufficiently biased, an inversion layer surrounds the gate regions, causing the effective base of the npn transistor to be narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter), the emitter-base junction characteristics, and the overall dopant concentration and thickness of the p-type base.

17. 发明授权

US09401488B2 Cobalt-carbon eutectic metal alloy ohmic contact for carbon nanotube field effect transistors 有权
标题翻译：碳 - 碳共晶金属合金欧姆接触碳纳米管场效应晶体管
公开(公告)号：US09401488B2
公开(公告)日：2016-07-26
申请号：US14575078
申请日：2014-12-18
申请人： Northrop Grumman Systems Corporation
发明人： Monica P. Lilly , Matthew J. Walker , Wayne S. Miller , John X. Przybysz, Sr. , Andre E. Berghmans
IPC分类号： H01L21/00 , H01L21/8238 , H01L21/20 , H01L29/745 , H01L51/10 , H01L51/00 , H01L51/05
CPC分类号： H01L51/105 , H01L51/0021 , H01L51/0048 , H01L51/0508 , H01L51/0541 , H01L51/0545 , H01L51/0558 , H01L51/107
摘要： A cobalt-carbon (Co—C) eutectic metal alloy ohmic contact for a radio-frequency (RF) carbon nanotube (CNT) field effect transistor (FET) device and a method of manufacturing same are disclosed. Embodiments of a method include providing a graphite crucible, placing Co and a C source within the graphite crucible, heating the graphite crucible containing the Co and C source such that the Co and C source combine with graphite from the graphite crucible to thereby form a Co—C eutectic metal alloy, and creating an ohmic contact by depositing the Co—C eutectic metal alloy directly on top surfaces of CNTs of a RF CNT FET device such that the Co—C eutectic metal alloy is in direct contact with the CNTs. The Co—C eutectic metal alloy ohmic contact formed in this manner is consistently stabile and uniform and functions as a high work function layer that also serves as an adhesion layer to the CNTs.
摘要翻译：公开了一种用于射频（RF）碳纳米管（CNT）场效应晶体管（FET）器件的钴 - 碳（Co-C）共晶金属合金欧姆接触及其制造方法。方法的实施例包括提供石墨坩埚，将Co和C源放置在石墨坩埚内，加热含有Co和C源的石墨坩埚，使得Co和C源与石墨坩埚中的石墨组合从而形成Co -C共晶金属合金，并通过将Co-C共晶金属合金直接沉积在RF CNT FET器件的CNT的顶表面上而形成欧姆接触，使得Co-C共晶金属合金与CNT直接接触。以这种方式形成的Co-C共晶金属合金欧姆接触始终稳定且均匀，并且起到高功函数层的作用，其也用作CNT的粘附层。

18. 发明授权

US09385195B1 Vertical gate-all-around TFET 有权
标题翻译：垂直栅极全能TFET
公开(公告)号：US09385195B1
公开(公告)日：2016-07-05
申请号：US14675536
申请日：2015-03-31
申请人： STMICROELECTRONICS, INC.
发明人： John H. Zhang
IPC分类号： H01L29/745 , H01L27/148 , H01L21/00 , H01L21/8238 , H01L29/06 , H01L29/16 , H01L29/78 , H01L29/10 , H01L29/49 , H01L29/20 , H01L29/66 , H01L21/28
CPC分类号： H01L27/10879 , B82Y10/00 , H01L21/28008 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823878 , H01L21/823885 , H01L21/823892 , H01L27/0814 , H01L27/092 , H01L27/0928 , H01L29/0653 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/20 , H01L29/42392 , H01L29/495 , H01L29/4966 , H01L29/66439 , H01L29/66666 , H01L29/66795 , H01L29/66909 , H01L29/66977 , H01L29/7391 , H01L29/775 , H01L29/7827 , H01L29/7855 , H01L29/7856 , H01L29/78618 , H01L29/78642 , H01L29/78696 , H01L31/0392 , H01L33/04 , H01L45/1233 , H01L2029/7858
摘要： A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.
摘要翻译：垂直隧道FET（TFET）为关键尺寸低于7nm的晶体管提供低功耗，高速开关性能。垂直TFET使用全栅（GAA）器件结构，其具有在形成于硅衬底中的掺杂阱的表面上方延伸的圆柱形结构。圆柱形结构包括从掺杂阱外延生长的下部漏极区域，沟道和上部源极区域。该通道由本征硅制成，而源极和漏极区域原位掺杂。环形栅极围绕通道，电容性地控制从所有侧面通过通道的电流。源极可以通过前侧触点电接触，而漏极通过背面触点进行访问，该触点提供低接触电阻并且还用作散热器。垂直TFET集成电路的可靠性通过将垂直TFET耦合到静电放电（ESD）二极管来增强。

19. 发明申请

US20160133734A1 GATED THYRISTOR POWER DEVICE 审中-公开
公开(公告)号：US20160133734A1
公开(公告)日：2016-05-12
申请号：US14828326
申请日：2015-08-17
申请人： DAVID SCHIE
发明人： DAVID SCHIE
IPC分类号： H01L29/745 , H01L29/74
CPC分类号： H02M7/145 , H01L27/0921 , H01L27/1027 , H01L29/102 , H01L29/7455 , H02M7/1557 , H02M2001/4291 , H01L2924/1302 , H01L2924/13026
摘要： An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ccb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (

20. 发明授权

US09142657B2 Gated thyristor power device 有权
标题翻译：门控晶闸管功率器件
公开(公告)号：US09142657B2
公开(公告)日：2015-09-22
申请号：US14214816
申请日：2014-03-15
申请人： David Schie
发明人： David Schie
IPC分类号： H01L29/66 , H01L21/332 , H01L29/745 , H02M7/155 , H01L29/10
CPC分类号： H02M7/145 , H01L27/0921 , H01L27/1027 , H01L29/102 , H01L29/7455 , H02M7/1557 , H02M2001/4291 , H01L2924/1302 , H01L2924/13026
摘要： An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ccb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (
摘要翻译：提供了一种改进的门控晶闸管，其利用的硅面积小于IGBT，BIPOLAR或MOSFET的尺寸适用于相同的应用。本发明的晶闸管的实施例具有较低的栅极电荷，以及用于给定电流密度的较低的正向压降。一旦触发的晶闸管的实施例具有不具有必须从栅极充电的相同Cgd或Ccb电容器的锁存结构，因此门控晶闸管产生更便宜，并且需要较小的栅极驱动器并且占用更少的空间比标准解决方案。本发明的晶闸管的实施例提供比使用改进的MCT结构的典型> 600ns更快的关断速度，其导致改进的尾电流关断曲线（<250ns）。此外，器件的串联电阻降低，而不包括实现电压阻断能力。最后，教导了正的唯一的栅极驱动装置是使用栅极端子来模拟饱和电流的方法。

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